1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct6775 - Driver for the hardware monitoring functionality of
4 * Nuvoton NCT677x Super-I/O chips
6 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
8 * Derived from w83627ehf driver
9 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
10 * Copyright (C) 2006 Yuan Mu (Winbond),
11 * Rudolf Marek <r.marek@assembler.cz>
12 * David Hubbard <david.c.hubbard@gmail.com>
13 * Daniel J Blueman <daniel.blueman@gmail.com>
14 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
16 * Shamelessly ripped from the w83627hf driver
17 * Copyright (C) 2003 Mark Studebaker
19 * Supports the following chips:
21 * Chip #vin #fan #pwm #temp chip IDs man ID
22 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
23 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
24 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
25 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
26 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
27 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
28 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
29 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
30 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
31 * nct6797d 14 7 7 2+6 0xd450 0xc1 0x5ca3
33 * nct6798d 14 7 7 2+6 0xd428 0xc1 0x5ca3
36 * #temp lists the number of monitored temperature sources (first value) plus
37 * the number of directly connectable temperature sensors (second value).
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42 #include <linux/module.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/jiffies.h>
46 #include <linux/platform_device.h>
47 #include <linux/hwmon.h>
48 #include <linux/hwmon-sysfs.h>
49 #include <linux/hwmon-vid.h>
50 #include <linux/err.h>
51 #include <linux/mutex.h>
52 #include <linux/acpi.h>
53 #include <linux/bitops.h>
54 #include <linux/dmi.h>
56 #include <linux/nospec.h>
61 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
62 nct6795, nct6796, nct6797, nct6798 };
64 /* used to set data->name = nct6775_device_names[data->sio_kind] */
65 static const char * const nct6775_device_names[] = {
79 static const char * const nct6775_sio_names[] __initconst = {
93 static unsigned short force_id;
94 module_param(force_id, ushort, 0);
95 MODULE_PARM_DESC(force_id, "Override the detected device ID");
97 static unsigned short fan_debounce;
98 module_param(fan_debounce, ushort, 0);
99 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
101 #define DRVNAME "nct6775"
104 * Super-I/O constants and functions
107 #define NCT6775_LD_ACPI 0x0a
108 #define NCT6775_LD_HWM 0x0b
109 #define NCT6775_LD_VID 0x0d
110 #define NCT6775_LD_12 0x12
112 #define SIO_REG_LDSEL 0x07 /* Logical device select */
113 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
114 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
115 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
117 #define SIO_NCT6106_ID 0xc450
118 #define SIO_NCT6775_ID 0xb470
119 #define SIO_NCT6776_ID 0xc330
120 #define SIO_NCT6779_ID 0xc560
121 #define SIO_NCT6791_ID 0xc800
122 #define SIO_NCT6792_ID 0xc910
123 #define SIO_NCT6793_ID 0xd120
124 #define SIO_NCT6795_ID 0xd350
125 #define SIO_NCT6796_ID 0xd420
126 #define SIO_NCT6797_ID 0xd450
127 #define SIO_NCT6798_ID 0xd428
128 #define SIO_ID_MASK 0xFFF8
130 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
133 superio_outb(int ioreg, int reg, int val)
136 outb(val, ioreg + 1);
140 superio_inb(int ioreg, int reg)
143 return inb(ioreg + 1);
147 superio_select(int ioreg, int ld)
149 outb(SIO_REG_LDSEL, ioreg);
154 superio_enter(int ioreg)
157 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
159 if (!request_muxed_region(ioreg, 2, DRVNAME))
169 superio_exit(int ioreg)
173 outb(0x02, ioreg + 1);
174 release_region(ioreg, 2);
181 #define IOREGION_ALIGNMENT (~7)
182 #define IOREGION_OFFSET 5
183 #define IOREGION_LENGTH 2
184 #define ADDR_REG_OFFSET 0
185 #define DATA_REG_OFFSET 1
187 #define NCT6775_REG_BANK 0x4E
188 #define NCT6775_REG_CONFIG 0x40
191 * Not currently used:
192 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
193 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
194 * REG_MAN_ID is at port 0x4f
195 * REG_CHIP_ID is at port 0x58
198 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
199 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
201 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
202 #define NUM_REG_BEEP 5 /* Max number of beep registers */
206 /* Common and NCT6775 specific data */
208 /* Voltage min/max registers for nr=7..14 are in bank 5 */
210 static const u16 NCT6775_REG_IN_MAX[] = {
211 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
212 0x55c, 0x55e, 0x560, 0x562 };
213 static const u16 NCT6775_REG_IN_MIN[] = {
214 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
215 0x55d, 0x55f, 0x561, 0x563 };
216 static const u16 NCT6775_REG_IN[] = {
217 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
220 #define NCT6775_REG_VBAT 0x5D
221 #define NCT6775_REG_DIODE 0x5E
222 #define NCT6775_DIODE_MASK 0x02
224 #define NCT6775_REG_FANDIV1 0x506
225 #define NCT6775_REG_FANDIV2 0x507
227 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
229 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
231 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
233 static const s8 NCT6775_ALARM_BITS[] = {
234 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
235 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
237 6, 7, 11, -1, -1, /* fan1..fan5 */
238 -1, -1, -1, /* unused */
239 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
240 12, -1 }; /* intrusion0, intrusion1 */
242 #define FAN_ALARM_BASE 16
243 #define TEMP_ALARM_BASE 24
244 #define INTRUSION_ALARM_BASE 30
246 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
249 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
252 static const s8 NCT6775_BEEP_BITS[] = {
253 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
254 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
255 21, /* global beep enable */
256 6, 7, 11, 28, -1, /* fan1..fan5 */
257 -1, -1, -1, /* unused */
258 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
259 12, -1 }; /* intrusion0, intrusion1 */
261 #define BEEP_ENABLE_BASE 15
263 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
264 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
266 /* DC or PWM output fan configuration */
267 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
268 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
270 /* Advanced Fan control, some values are common for all fans */
272 static const u16 NCT6775_REG_TARGET[] = {
273 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
274 static const u16 NCT6775_REG_FAN_MODE[] = {
275 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
276 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
277 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
278 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
279 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
280 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
281 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
282 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
283 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
284 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
285 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
287 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
288 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
289 static const u16 NCT6775_REG_PWM[] = {
290 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
291 static const u16 NCT6775_REG_PWM_READ[] = {
292 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
294 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
295 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
296 static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
297 0x641, 0x642, 0x643, 0x644 };
298 static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
300 static const u16 NCT6775_REG_TEMP[] = {
301 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
303 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
305 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
306 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
307 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
308 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
309 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
310 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
312 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
313 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
315 static const u16 NCT6775_REG_TEMP_SEL[] = {
316 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
318 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
319 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
320 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
321 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
322 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
323 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
324 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
325 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
326 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
327 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
329 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
331 static const u16 NCT6775_REG_AUTO_TEMP[] = {
332 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
333 static const u16 NCT6775_REG_AUTO_PWM[] = {
334 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
336 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
337 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
339 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
341 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
342 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
343 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
344 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
346 static const char *const nct6775_temp_label[] = {
360 "PCH_CHIP_CPU_MAX_TEMP",
370 #define NCT6775_TEMP_MASK 0x001ffffe
371 #define NCT6775_VIRT_TEMP_MASK 0x00000000
373 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
379 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
390 /* NCT6776 specific data */
392 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
393 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
394 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
396 static const s8 NCT6776_ALARM_BITS[] = {
397 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
398 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
400 6, 7, 11, 10, 23, /* fan1..fan5 */
401 -1, -1, -1, /* unused */
402 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
403 12, 9 }; /* intrusion0, intrusion1 */
405 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
407 static const s8 NCT6776_BEEP_BITS[] = {
408 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
409 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
410 24, /* global beep enable */
411 25, 26, 27, 28, 29, /* fan1..fan5 */
412 -1, -1, -1, /* unused */
413 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
414 30, 31 }; /* intrusion0, intrusion1 */
416 static const u16 NCT6776_REG_TOLERANCE_H[] = {
417 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
419 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
420 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
422 static const u16 NCT6776_REG_FAN_MIN[] = {
423 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
424 static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
425 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
427 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
428 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
430 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
431 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
433 static const char *const nct6776_temp_label[] = {
448 "PCH_CHIP_CPU_MAX_TEMP",
459 #define NCT6776_TEMP_MASK 0x007ffffe
460 #define NCT6776_VIRT_TEMP_MASK 0x00000000
462 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
468 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
473 /* NCT6779 specific data */
475 static const u16 NCT6779_REG_IN[] = {
476 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
477 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
479 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
480 0x459, 0x45A, 0x45B, 0x568 };
482 static const s8 NCT6779_ALARM_BITS[] = {
483 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
484 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
486 6, 7, 11, 10, 23, /* fan1..fan5 */
487 -1, -1, -1, /* unused */
488 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
489 12, 9 }; /* intrusion0, intrusion1 */
491 static const s8 NCT6779_BEEP_BITS[] = {
492 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
493 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
494 24, /* global beep enable */
495 25, 26, 27, 28, 29, /* fan1..fan5 */
496 -1, -1, -1, /* unused */
497 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
498 30, 31 }; /* intrusion0, intrusion1 */
500 static const u16 NCT6779_REG_FAN[] = {
501 0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
502 static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
503 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0x64f };
505 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
506 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
507 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
508 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
509 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
511 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
512 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
513 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
515 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
517 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
520 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
521 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
523 static const char *const nct6779_temp_label[] = {
542 "PCH_CHIP_CPU_MAX_TEMP",
558 #define NCT6779_TEMP_MASK 0x07ffff7e
559 #define NCT6779_VIRT_TEMP_MASK 0x00000000
560 #define NCT6791_TEMP_MASK 0x87ffff7e
561 #define NCT6791_VIRT_TEMP_MASK 0x80000000
563 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
564 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
565 0, 0, 0, 0, 0, 0, 0, 0,
566 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
569 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
574 /* NCT6791 specific data */
576 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
578 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
579 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
580 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
581 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
582 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
583 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
585 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
586 0x459, 0x45A, 0x45B, 0x568, 0x45D };
588 static const s8 NCT6791_ALARM_BITS[] = {
589 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
590 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
592 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
594 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
595 12, 9 }; /* intrusion0, intrusion1 */
597 /* NCT6792/NCT6793 specific data */
599 static const u16 NCT6792_REG_TEMP_MON[] = {
600 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
601 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
602 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
604 static const char *const nct6792_temp_label[] = {
623 "PCH_CHIP_CPU_MAX_TEMP",
632 "PECI Agent 0 Calibration",
633 "PECI Agent 1 Calibration",
639 #define NCT6792_TEMP_MASK 0x9fffff7e
640 #define NCT6792_VIRT_TEMP_MASK 0x80000000
642 static const char *const nct6793_temp_label[] = {
661 "PCH_CHIP_CPU_MAX_TEMP",
671 "PECI Agent 0 Calibration",
672 "PECI Agent 1 Calibration",
677 #define NCT6793_TEMP_MASK 0xbfff037e
678 #define NCT6793_VIRT_TEMP_MASK 0x80000000
680 static const char *const nct6795_temp_label[] = {
699 "PCH_CHIP_CPU_MAX_TEMP",
709 "PECI Agent 0 Calibration",
710 "PECI Agent 1 Calibration",
715 #define NCT6795_TEMP_MASK 0xbfffff7e
716 #define NCT6795_VIRT_TEMP_MASK 0x80000000
718 static const char *const nct6796_temp_label[] = {
737 "PCH_CHIP_CPU_MAX_TEMP",
747 "PECI Agent 0 Calibration",
748 "PECI Agent 1 Calibration",
753 #define NCT6796_TEMP_MASK 0xbfff0ffe
754 #define NCT6796_VIRT_TEMP_MASK 0x80000c00
756 static const char *const nct6798_temp_label[] = {
775 "PCH_CHIP_CPU_MAX_TEMP",
791 #define NCT6798_TEMP_MASK 0x8fff0ffe
792 #define NCT6798_VIRT_TEMP_MASK 0x80000c00
794 /* NCT6102D/NCT6106D specific data */
796 #define NCT6106_REG_VBAT 0x318
797 #define NCT6106_REG_DIODE 0x319
798 #define NCT6106_DIODE_MASK 0x01
800 static const u16 NCT6106_REG_IN_MAX[] = {
801 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
802 static const u16 NCT6106_REG_IN_MIN[] = {
803 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
804 static const u16 NCT6106_REG_IN[] = {
805 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
807 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
808 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
809 static const u16 NCT6106_REG_TEMP_HYST[] = {
810 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
811 static const u16 NCT6106_REG_TEMP_OVER[] = {
812 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
813 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
814 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
815 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
816 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
817 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
818 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
819 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
821 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
822 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
823 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
824 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
826 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
827 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
828 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
829 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
830 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
831 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
832 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
833 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
835 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
836 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
837 0x11b, 0x12b, 0x13b };
839 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
840 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
841 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
843 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
844 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
845 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
846 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
847 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
848 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
850 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
852 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
853 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
854 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
855 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x18b };
856 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
857 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
859 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
860 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
862 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
863 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
865 static const s8 NCT6106_ALARM_BITS[] = {
866 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
867 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
869 32, 33, 34, -1, -1, /* fan1..fan5 */
870 -1, -1, -1, /* unused */
871 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
872 48, -1 /* intrusion0, intrusion1 */
875 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
876 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
878 static const s8 NCT6106_BEEP_BITS[] = {
879 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
880 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
881 32, /* global beep enable */
882 24, 25, 26, 27, 28, /* fan1..fan5 */
883 -1, -1, -1, /* unused */
884 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
885 34, -1 /* intrusion0, intrusion1 */
888 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
894 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
899 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
901 if (mode == 0 && pwm == 255)
906 static int pwm_enable_to_reg(enum pwm_enable mode)
917 /* 1 is DC mode, output in ms */
918 static unsigned int step_time_from_reg(u8 reg, u8 mode)
920 return mode ? 400 * reg : 100 * reg;
923 static u8 step_time_to_reg(unsigned int msec, u8 mode)
925 return clamp_val((mode ? (msec + 200) / 400 :
926 (msec + 50) / 100), 1, 255);
929 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
931 if (reg == 0 || reg == 255)
933 return 1350000U / (reg << divreg);
936 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
938 if ((reg & 0xff1f) == 0xff1f)
941 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
946 return 1350000U / reg;
949 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
951 if (reg == 0 || reg == 0xffff)
955 * Even though the registers are 16 bit wide, the fan divisor
958 return 1350000U / (reg << divreg);
961 static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
966 static u16 fan_to_reg(u32 fan, unsigned int divreg)
971 return (1350000U / fan) >> divreg;
974 static inline unsigned int
981 * Some of the voltage inputs have internal scaling, the tables below
982 * contain 8 (the ADC LSB in mV) * scaling factor * 100
984 static const u16 scale_in[15] = {
985 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
989 static inline long in_from_reg(u8 reg, u8 nr)
991 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
994 static inline u8 in_to_reg(u32 val, u8 nr)
996 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
1000 * Data structures and manipulation thereof
1003 struct nct6775_data {
1004 int addr; /* IO base of hw monitor block */
1005 int sioreg; /* SIO register address */
1009 const struct attribute_group *groups[6];
1011 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1012 * 3=temp_crit, 4=temp_lcrit
1014 u8 temp_src[NUM_TEMP];
1015 u16 reg_temp_config[NUM_TEMP];
1016 const char * const *temp_label;
1025 const s8 *ALARM_BITS;
1026 const s8 *BEEP_BITS;
1029 const u16 *REG_IN_MINMAX[2];
1031 const u16 *REG_TARGET;
1033 const u16 *REG_FAN_MODE;
1034 const u16 *REG_FAN_MIN;
1035 const u16 *REG_FAN_PULSES;
1036 const u16 *FAN_PULSE_SHIFT;
1037 const u16 *REG_FAN_TIME[3];
1039 const u16 *REG_TOLERANCE_H;
1041 const u8 *REG_PWM_MODE;
1042 const u8 *PWM_MODE_MASK;
1044 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1045 * [3]=pwm_max, [4]=pwm_step,
1046 * [5]=weight_duty_step, [6]=weight_duty_base
1048 const u16 *REG_PWM_READ;
1050 const u16 *REG_CRITICAL_PWM_ENABLE;
1051 u8 CRITICAL_PWM_ENABLE_MASK;
1052 const u16 *REG_CRITICAL_PWM;
1054 const u16 *REG_AUTO_TEMP;
1055 const u16 *REG_AUTO_PWM;
1057 const u16 *REG_CRITICAL_TEMP;
1058 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1060 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1061 const u16 *REG_TEMP_SEL;
1062 const u16 *REG_WEIGHT_TEMP_SEL;
1063 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1065 const u16 *REG_TEMP_OFFSET;
1067 const u16 *REG_ALARM;
1068 const u16 *REG_BEEP;
1070 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1071 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1073 struct mutex update_lock;
1074 bool valid; /* true if following fields are valid */
1075 unsigned long last_updated; /* In jiffies */
1077 /* Register values */
1078 u8 bank; /* current register bank */
1079 u8 in_num; /* number of in inputs we have */
1080 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1081 unsigned int rpm[NUM_FAN];
1082 u16 fan_min[NUM_FAN];
1083 u8 fan_pulses[NUM_FAN];
1084 u8 fan_div[NUM_FAN];
1086 u8 has_fan; /* some fan inputs can be disabled */
1087 u8 has_fan_min; /* some fans don't have min register */
1090 u8 num_temp_alarms; /* 2, 3, or 6 */
1091 u8 num_temp_beeps; /* 2, 3, or 6 */
1092 u8 temp_fixed_num; /* 3 or 6 */
1093 u8 temp_type[NUM_TEMP_FIXED];
1094 s8 temp_offset[NUM_TEMP_FIXED];
1095 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1096 * 3=temp_crit, 4=temp_lcrit */
1100 u8 pwm_num; /* number of pwm */
1101 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1102 * 1->PWM variable duty cycle
1104 enum pwm_enable pwm_enable[NUM_FAN];
1107 * 2->thermal cruise mode (also called SmartFan I)
1108 * 3->fan speed cruise mode
1110 * 5->enhanced variable thermal cruise (SmartFan IV)
1112 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1113 * [3]=pwm_max, [4]=pwm_step,
1114 * [5]=weight_duty_step, [6]=weight_duty_base
1117 u8 target_temp[NUM_FAN];
1118 u8 target_temp_mask;
1119 u32 target_speed[NUM_FAN];
1120 u32 target_speed_tolerance[NUM_FAN];
1121 u8 speed_tolerance_limit;
1123 u8 temp_tolerance[2][NUM_FAN];
1126 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1128 /* Automatic fan speed control registers */
1130 u8 auto_pwm[NUM_FAN][7];
1131 u8 auto_temp[NUM_FAN][7];
1132 u8 pwm_temp_sel[NUM_FAN];
1133 u8 pwm_weight_temp_sel[NUM_FAN];
1134 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1144 u16 have_temp_fixed;
1147 /* Remember extra register values over suspend/resume */
1154 struct nct6775_sio_data {
1159 struct sensor_device_template {
1160 struct device_attribute dev_attr;
1168 bool s2; /* true if both index and nr are used */
1171 struct sensor_device_attr_u {
1173 struct sensor_device_attribute a1;
1174 struct sensor_device_attribute_2 a2;
1179 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1180 .attr = {.name = _template, .mode = _mode }, \
1185 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1186 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1187 .u.index = _index, \
1190 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1192 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1193 .u.s.index = _index, \
1197 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1198 static struct sensor_device_template sensor_dev_template_##_name \
1199 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1202 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1204 static struct sensor_device_template sensor_dev_template_##_name \
1205 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1208 struct sensor_template_group {
1209 struct sensor_device_template **templates;
1210 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1214 static struct attribute_group *
1215 nct6775_create_attr_group(struct device *dev,
1216 const struct sensor_template_group *tg,
1219 struct attribute_group *group;
1220 struct sensor_device_attr_u *su;
1221 struct sensor_device_attribute *a;
1222 struct sensor_device_attribute_2 *a2;
1223 struct attribute **attrs;
1224 struct sensor_device_template **t;
1228 return ERR_PTR(-EINVAL);
1231 for (count = 0; *t; t++, count++)
1235 return ERR_PTR(-EINVAL);
1237 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1239 return ERR_PTR(-ENOMEM);
1241 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1244 return ERR_PTR(-ENOMEM);
1246 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1249 return ERR_PTR(-ENOMEM);
1251 group->attrs = attrs;
1252 group->is_visible = tg->is_visible;
1254 for (i = 0; i < repeat; i++) {
1256 while (*t != NULL) {
1257 snprintf(su->name, sizeof(su->name),
1258 (*t)->dev_attr.attr.name, tg->base + i);
1261 sysfs_attr_init(&a2->dev_attr.attr);
1262 a2->dev_attr.attr.name = su->name;
1263 a2->nr = (*t)->u.s.nr + i;
1264 a2->index = (*t)->u.s.index;
1265 a2->dev_attr.attr.mode =
1266 (*t)->dev_attr.attr.mode;
1267 a2->dev_attr.show = (*t)->dev_attr.show;
1268 a2->dev_attr.store = (*t)->dev_attr.store;
1269 *attrs = &a2->dev_attr.attr;
1272 sysfs_attr_init(&a->dev_attr.attr);
1273 a->dev_attr.attr.name = su->name;
1274 a->index = (*t)->u.index + i;
1275 a->dev_attr.attr.mode =
1276 (*t)->dev_attr.attr.mode;
1277 a->dev_attr.show = (*t)->dev_attr.show;
1278 a->dev_attr.store = (*t)->dev_attr.store;
1279 *attrs = &a->dev_attr.attr;
1290 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1292 switch (data->kind) {
1294 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1295 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1296 reg == 0x111 || reg == 0x121 || reg == 0x131;
1298 return (((reg & 0xff00) == 0x100 ||
1299 (reg & 0xff00) == 0x200) &&
1300 ((reg & 0x00ff) == 0x50 ||
1301 (reg & 0x00ff) == 0x53 ||
1302 (reg & 0x00ff) == 0x55)) ||
1303 (reg & 0xfff0) == 0x630 ||
1304 reg == 0x640 || reg == 0x642 ||
1306 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1307 reg == 0x73 || reg == 0x75 || reg == 0x77;
1309 return (((reg & 0xff00) == 0x100 ||
1310 (reg & 0xff00) == 0x200) &&
1311 ((reg & 0x00ff) == 0x50 ||
1312 (reg & 0x00ff) == 0x53 ||
1313 (reg & 0x00ff) == 0x55)) ||
1314 (reg & 0xfff0) == 0x630 ||
1316 reg == 0x640 || reg == 0x642 ||
1317 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1318 reg == 0x73 || reg == 0x75 || reg == 0x77;
1327 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1328 (reg & 0xfff0) == 0x4c0 ||
1330 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1331 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1333 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1334 reg == 0x7b || reg == 0x7d;
1340 * On older chips, only registers 0x50-0x5f are banked.
1341 * On more recent chips, all registers are banked.
1342 * Assume that is the case and set the bank number for each access.
1343 * Cache the bank number so it only needs to be set if it changes.
1345 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1349 if (data->bank != bank) {
1350 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1351 outb_p(bank, data->addr + DATA_REG_OFFSET);
1356 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1358 int res, word_sized = is_word_sized(data, reg);
1360 nct6775_set_bank(data, reg);
1361 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1362 res = inb_p(data->addr + DATA_REG_OFFSET);
1364 outb_p((reg & 0xff) + 1,
1365 data->addr + ADDR_REG_OFFSET);
1366 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1371 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1373 int word_sized = is_word_sized(data, reg);
1375 nct6775_set_bank(data, reg);
1376 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1378 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1379 outb_p((reg & 0xff) + 1,
1380 data->addr + ADDR_REG_OFFSET);
1382 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1386 /* We left-align 8-bit temperature values to make the code simpler */
1387 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1391 res = nct6775_read_value(data, reg);
1392 if (!is_word_sized(data, reg))
1398 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1400 if (!is_word_sized(data, reg))
1402 return nct6775_write_value(data, reg, value);
1405 /* This function assumes that the caller holds data->update_lock */
1406 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1412 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1413 | (data->fan_div[0] & 0x7);
1414 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1417 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1418 | ((data->fan_div[1] << 4) & 0x70);
1419 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1422 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1423 | (data->fan_div[2] & 0x7);
1424 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1427 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1428 | ((data->fan_div[3] << 4) & 0x70);
1429 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1434 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1436 if (data->kind == nct6775)
1437 nct6775_write_fan_div(data, nr);
1440 static void nct6775_update_fan_div(struct nct6775_data *data)
1444 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1445 data->fan_div[0] = i & 0x7;
1446 data->fan_div[1] = (i & 0x70) >> 4;
1447 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1448 data->fan_div[2] = i & 0x7;
1449 if (data->has_fan & BIT(3))
1450 data->fan_div[3] = (i & 0x70) >> 4;
1453 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1455 if (data->kind == nct6775)
1456 nct6775_update_fan_div(data);
1459 static void nct6775_init_fan_div(struct nct6775_data *data)
1463 nct6775_update_fan_div_common(data);
1465 * For all fans, start with highest divider value if the divider
1466 * register is not initialized. This ensures that we get a
1467 * reading from the fan count register, even if it is not optimal.
1468 * We'll compute a better divider later on.
1470 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1471 if (!(data->has_fan & BIT(i)))
1473 if (data->fan_div[i] == 0) {
1474 data->fan_div[i] = 7;
1475 nct6775_write_fan_div_common(data, i);
1480 static void nct6775_init_fan_common(struct device *dev,
1481 struct nct6775_data *data)
1486 if (data->has_fan_div)
1487 nct6775_init_fan_div(data);
1490 * If fan_min is not set (0), set it to 0xff to disable it. This
1491 * prevents the unnecessary warning when fanX_min is reported as 0.
1493 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1494 if (data->has_fan_min & BIT(i)) {
1495 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1497 nct6775_write_value(data, data->REG_FAN_MIN[i],
1498 data->has_fan_div ? 0xff
1504 static void nct6775_select_fan_div(struct device *dev,
1505 struct nct6775_data *data, int nr, u16 reg)
1507 u8 fan_div = data->fan_div[nr];
1510 if (!data->has_fan_div)
1514 * If we failed to measure the fan speed, or the reported value is not
1515 * in the optimal range, and the clock divider can be modified,
1516 * let's try that for next time.
1518 if (reg == 0x00 && fan_div < 0x07)
1520 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1523 if (fan_div != data->fan_div[nr]) {
1524 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1525 nr + 1, div_from_reg(data->fan_div[nr]),
1526 div_from_reg(fan_div));
1528 /* Preserve min limit if possible */
1529 if (data->has_fan_min & BIT(nr)) {
1530 fan_min = data->fan_min[nr];
1531 if (fan_div > data->fan_div[nr]) {
1532 if (fan_min != 255 && fan_min > 1)
1535 if (fan_min != 255) {
1541 if (fan_min != data->fan_min[nr]) {
1542 data->fan_min[nr] = fan_min;
1543 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1547 data->fan_div[nr] = fan_div;
1548 nct6775_write_fan_div_common(data, nr);
1552 static void nct6775_update_pwm(struct device *dev)
1554 struct nct6775_data *data = dev_get_drvdata(dev);
1556 int fanmodecfg, reg;
1559 for (i = 0; i < data->pwm_num; i++) {
1560 if (!(data->has_pwm & BIT(i)))
1563 duty_is_dc = data->REG_PWM_MODE[i] &&
1564 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1565 & data->PWM_MODE_MASK[i]);
1566 data->pwm_mode[i] = !duty_is_dc;
1568 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1569 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1570 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1572 = nct6775_read_value(data,
1573 data->REG_PWM[j][i]);
1577 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1578 (fanmodecfg >> 4) & 7);
1580 if (!data->temp_tolerance[0][i] ||
1581 data->pwm_enable[i] != speed_cruise)
1582 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1583 if (!data->target_speed_tolerance[i] ||
1584 data->pwm_enable[i] == speed_cruise) {
1585 u8 t = fanmodecfg & 0x0f;
1587 if (data->REG_TOLERANCE_H) {
1588 t |= (nct6775_read_value(data,
1589 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1591 data->target_speed_tolerance[i] = t;
1594 data->temp_tolerance[1][i] =
1595 nct6775_read_value(data,
1596 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1598 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1599 data->pwm_temp_sel[i] = reg & 0x1f;
1600 /* If fan can stop, report floor as 0 */
1602 data->pwm[2][i] = 0;
1604 if (!data->REG_WEIGHT_TEMP_SEL[i])
1607 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1608 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1609 /* If weight is disabled, report weight source as 0 */
1611 data->pwm_weight_temp_sel[i] = 0;
1613 /* Weight temp data */
1614 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1615 data->weight_temp[j][i]
1616 = nct6775_read_value(data,
1617 data->REG_WEIGHT_TEMP[j][i]);
1622 static void nct6775_update_pwm_limits(struct device *dev)
1624 struct nct6775_data *data = dev_get_drvdata(dev);
1629 for (i = 0; i < data->pwm_num; i++) {
1630 if (!(data->has_pwm & BIT(i)))
1633 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1634 data->fan_time[j][i] =
1635 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1638 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1639 /* Update only in matching mode or if never updated */
1640 if (!data->target_temp[i] ||
1641 data->pwm_enable[i] == thermal_cruise)
1642 data->target_temp[i] = reg_t & data->target_temp_mask;
1643 if (!data->target_speed[i] ||
1644 data->pwm_enable[i] == speed_cruise) {
1645 if (data->REG_TOLERANCE_H) {
1646 reg_t |= (nct6775_read_value(data,
1647 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1649 data->target_speed[i] = reg_t;
1652 for (j = 0; j < data->auto_pwm_num; j++) {
1653 data->auto_pwm[i][j] =
1654 nct6775_read_value(data,
1655 NCT6775_AUTO_PWM(data, i, j));
1656 data->auto_temp[i][j] =
1657 nct6775_read_value(data,
1658 NCT6775_AUTO_TEMP(data, i, j));
1661 /* critical auto_pwm temperature data */
1662 data->auto_temp[i][data->auto_pwm_num] =
1663 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1665 switch (data->kind) {
1667 reg = nct6775_read_value(data,
1668 NCT6775_REG_CRITICAL_ENAB[i]);
1669 data->auto_pwm[i][data->auto_pwm_num] =
1670 (reg & 0x02) ? 0xff : 0x00;
1673 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1684 reg = nct6775_read_value(data,
1685 data->REG_CRITICAL_PWM_ENABLE[i]);
1686 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1687 reg = nct6775_read_value(data,
1688 data->REG_CRITICAL_PWM[i]);
1691 data->auto_pwm[i][data->auto_pwm_num] = reg;
1697 static struct nct6775_data *nct6775_update_device(struct device *dev)
1699 struct nct6775_data *data = dev_get_drvdata(dev);
1702 mutex_lock(&data->update_lock);
1704 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1706 /* Fan clock dividers */
1707 nct6775_update_fan_div_common(data);
1709 /* Measured voltages and limits */
1710 for (i = 0; i < data->in_num; i++) {
1711 if (!(data->have_in & BIT(i)))
1714 data->in[i][0] = nct6775_read_value(data,
1716 data->in[i][1] = nct6775_read_value(data,
1717 data->REG_IN_MINMAX[0][i]);
1718 data->in[i][2] = nct6775_read_value(data,
1719 data->REG_IN_MINMAX[1][i]);
1722 /* Measured fan speeds and limits */
1723 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1726 if (!(data->has_fan & BIT(i)))
1729 reg = nct6775_read_value(data, data->REG_FAN[i]);
1730 data->rpm[i] = data->fan_from_reg(reg,
1733 if (data->has_fan_min & BIT(i))
1734 data->fan_min[i] = nct6775_read_value(data,
1735 data->REG_FAN_MIN[i]);
1737 if (data->REG_FAN_PULSES[i]) {
1738 data->fan_pulses[i] =
1739 (nct6775_read_value(data,
1740 data->REG_FAN_PULSES[i])
1741 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1744 nct6775_select_fan_div(dev, data, i, reg);
1747 nct6775_update_pwm(dev);
1748 nct6775_update_pwm_limits(dev);
1750 /* Measured temperatures and limits */
1751 for (i = 0; i < NUM_TEMP; i++) {
1752 if (!(data->have_temp & BIT(i)))
1754 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1755 if (data->reg_temp[j][i])
1757 = nct6775_read_temp(data,
1758 data->reg_temp[j][i]);
1760 if (i >= NUM_TEMP_FIXED ||
1761 !(data->have_temp_fixed & BIT(i)))
1763 data->temp_offset[i]
1764 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1768 for (i = 0; i < NUM_REG_ALARM; i++) {
1771 if (!data->REG_ALARM[i])
1773 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1774 data->alarms |= ((u64)alarm) << (i << 3);
1778 for (i = 0; i < NUM_REG_BEEP; i++) {
1781 if (!data->REG_BEEP[i])
1783 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1784 data->beeps |= ((u64)beep) << (i << 3);
1787 data->last_updated = jiffies;
1791 mutex_unlock(&data->update_lock);
1796 * Sysfs callback functions
1799 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1801 struct nct6775_data *data = nct6775_update_device(dev);
1802 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1803 int index = sattr->index;
1806 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1810 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1813 struct nct6775_data *data = dev_get_drvdata(dev);
1814 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1815 int index = sattr->index;
1820 err = kstrtoul(buf, 10, &val);
1823 mutex_lock(&data->update_lock);
1824 data->in[nr][index] = in_to_reg(val, nr);
1825 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1826 data->in[nr][index]);
1827 mutex_unlock(&data->update_lock);
1832 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1834 struct nct6775_data *data = nct6775_update_device(dev);
1835 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1836 int nr = data->ALARM_BITS[sattr->index];
1838 return sprintf(buf, "%u\n",
1839 (unsigned int)((data->alarms >> nr) & 0x01));
1842 static int find_temp_source(struct nct6775_data *data, int index, int count)
1844 int source = data->temp_src[index];
1847 for (nr = 0; nr < count; nr++) {
1850 src = nct6775_read_value(data,
1851 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1859 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1861 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1862 struct nct6775_data *data = nct6775_update_device(dev);
1863 unsigned int alarm = 0;
1867 * For temperatures, there is no fixed mapping from registers to alarm
1868 * bits. Alarm bits are determined by the temperature source mapping.
1870 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1872 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1874 alarm = (data->alarms >> bit) & 0x01;
1876 return sprintf(buf, "%u\n", alarm);
1880 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1882 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1883 struct nct6775_data *data = nct6775_update_device(dev);
1884 int nr = data->BEEP_BITS[sattr->index];
1886 return sprintf(buf, "%u\n",
1887 (unsigned int)((data->beeps >> nr) & 0x01));
1891 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1894 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1895 struct nct6775_data *data = dev_get_drvdata(dev);
1896 int nr = data->BEEP_BITS[sattr->index];
1897 int regindex = nr >> 3;
1901 err = kstrtoul(buf, 10, &val);
1907 mutex_lock(&data->update_lock);
1909 data->beeps |= (1ULL << nr);
1911 data->beeps &= ~(1ULL << nr);
1912 nct6775_write_value(data, data->REG_BEEP[regindex],
1913 (data->beeps >> (regindex << 3)) & 0xff);
1914 mutex_unlock(&data->update_lock);
1919 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1921 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1922 struct nct6775_data *data = nct6775_update_device(dev);
1923 unsigned int beep = 0;
1927 * For temperatures, there is no fixed mapping from registers to beep
1928 * enable bits. Beep enable bits are determined by the temperature
1931 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1933 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1935 beep = (data->beeps >> bit) & 0x01;
1937 return sprintf(buf, "%u\n", beep);
1941 store_temp_beep(struct device *dev, struct device_attribute *attr,
1942 const char *buf, size_t count)
1944 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1945 struct nct6775_data *data = dev_get_drvdata(dev);
1946 int nr, bit, regindex;
1950 err = kstrtoul(buf, 10, &val);
1956 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1960 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1961 regindex = bit >> 3;
1963 mutex_lock(&data->update_lock);
1965 data->beeps |= (1ULL << bit);
1967 data->beeps &= ~(1ULL << bit);
1968 nct6775_write_value(data, data->REG_BEEP[regindex],
1969 (data->beeps >> (regindex << 3)) & 0xff);
1970 mutex_unlock(&data->update_lock);
1975 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1976 struct attribute *attr, int index)
1978 struct device *dev = container_of(kobj, struct device, kobj);
1979 struct nct6775_data *data = dev_get_drvdata(dev);
1980 int in = index / 5; /* voltage index */
1982 if (!(data->have_in & BIT(in)))
1988 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1989 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1990 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1992 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1993 store_in_reg, 0, 1);
1994 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1995 store_in_reg, 0, 2);
1998 * nct6775_in_is_visible uses the index into the following array
1999 * to determine if attributes should be created or not.
2000 * Any change in order or content must be matched.
2002 static struct sensor_device_template *nct6775_attributes_in_template[] = {
2003 &sensor_dev_template_in_input,
2004 &sensor_dev_template_in_alarm,
2005 &sensor_dev_template_in_beep,
2006 &sensor_dev_template_in_min,
2007 &sensor_dev_template_in_max,
2011 static const struct sensor_template_group nct6775_in_template_group = {
2012 .templates = nct6775_attributes_in_template,
2013 .is_visible = nct6775_in_is_visible,
2017 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
2019 struct nct6775_data *data = nct6775_update_device(dev);
2020 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2021 int nr = sattr->index;
2023 return sprintf(buf, "%d\n", data->rpm[nr]);
2027 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
2029 struct nct6775_data *data = nct6775_update_device(dev);
2030 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2031 int nr = sattr->index;
2033 return sprintf(buf, "%d\n",
2034 data->fan_from_reg_min(data->fan_min[nr],
2035 data->fan_div[nr]));
2039 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2041 struct nct6775_data *data = nct6775_update_device(dev);
2042 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2043 int nr = sattr->index;
2045 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2049 store_fan_min(struct device *dev, struct device_attribute *attr,
2050 const char *buf, size_t count)
2052 struct nct6775_data *data = dev_get_drvdata(dev);
2053 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2054 int nr = sattr->index;
2060 err = kstrtoul(buf, 10, &val);
2064 mutex_lock(&data->update_lock);
2065 if (!data->has_fan_div) {
2066 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2072 val = 1350000U / val;
2073 val = (val & 0x1f) | ((val << 3) & 0xff00);
2075 data->fan_min[nr] = val;
2076 goto write_min; /* Leave fan divider alone */
2079 /* No min limit, alarm disabled */
2080 data->fan_min[nr] = 255;
2081 new_div = data->fan_div[nr]; /* No change */
2082 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2085 reg = 1350000U / val;
2086 if (reg >= 128 * 255) {
2088 * Speed below this value cannot possibly be represented,
2089 * even with the highest divider (128)
2091 data->fan_min[nr] = 254;
2092 new_div = 7; /* 128 == BIT(7) */
2094 "fan%u low limit %lu below minimum %u, set to minimum\n",
2095 nr + 1, val, data->fan_from_reg_min(254, 7));
2098 * Speed above this value cannot possibly be represented,
2099 * even with the lowest divider (1)
2101 data->fan_min[nr] = 1;
2102 new_div = 0; /* 1 == BIT(0) */
2104 "fan%u low limit %lu above maximum %u, set to maximum\n",
2105 nr + 1, val, data->fan_from_reg_min(1, 0));
2108 * Automatically pick the best divider, i.e. the one such
2109 * that the min limit will correspond to a register value
2110 * in the 96..192 range
2113 while (reg > 192 && new_div < 7) {
2117 data->fan_min[nr] = reg;
2122 * Write both the fan clock divider (if it changed) and the new
2123 * fan min (unconditionally)
2125 if (new_div != data->fan_div[nr]) {
2126 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2127 nr + 1, div_from_reg(data->fan_div[nr]),
2128 div_from_reg(new_div));
2129 data->fan_div[nr] = new_div;
2130 nct6775_write_fan_div_common(data, nr);
2131 /* Give the chip time to sample a new speed value */
2132 data->last_updated = jiffies;
2136 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2137 mutex_unlock(&data->update_lock);
2143 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2145 struct nct6775_data *data = nct6775_update_device(dev);
2146 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2147 int p = data->fan_pulses[sattr->index];
2149 return sprintf(buf, "%d\n", p ? : 4);
2153 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2154 const char *buf, size_t count)
2156 struct nct6775_data *data = dev_get_drvdata(dev);
2157 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2158 int nr = sattr->index;
2163 err = kstrtoul(buf, 10, &val);
2170 mutex_lock(&data->update_lock);
2171 data->fan_pulses[nr] = val & 3;
2172 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2173 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2174 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2175 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2176 mutex_unlock(&data->update_lock);
2181 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2182 struct attribute *attr, int index)
2184 struct device *dev = container_of(kobj, struct device, kobj);
2185 struct nct6775_data *data = dev_get_drvdata(dev);
2186 int fan = index / 6; /* fan index */
2187 int nr = index % 6; /* attribute index */
2189 if (!(data->has_fan & BIT(fan)))
2192 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2194 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2196 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2198 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2200 if (nr == 5 && data->kind != nct6775)
2206 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2207 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2209 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2210 store_beep, FAN_ALARM_BASE);
2211 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2212 store_fan_pulses, 0);
2213 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2215 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2218 * nct6775_fan_is_visible uses the index into the following array
2219 * to determine if attributes should be created or not.
2220 * Any change in order or content must be matched.
2222 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2223 &sensor_dev_template_fan_input,
2224 &sensor_dev_template_fan_alarm, /* 1 */
2225 &sensor_dev_template_fan_beep, /* 2 */
2226 &sensor_dev_template_fan_pulses,
2227 &sensor_dev_template_fan_min, /* 4 */
2228 &sensor_dev_template_fan_div, /* 5 */
2232 static const struct sensor_template_group nct6775_fan_template_group = {
2233 .templates = nct6775_attributes_fan_template,
2234 .is_visible = nct6775_fan_is_visible,
2239 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2241 struct nct6775_data *data = nct6775_update_device(dev);
2242 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2243 int nr = sattr->index;
2245 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2249 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2251 struct nct6775_data *data = nct6775_update_device(dev);
2252 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2254 int index = sattr->index;
2256 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2260 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2263 struct nct6775_data *data = dev_get_drvdata(dev);
2264 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2266 int index = sattr->index;
2270 err = kstrtol(buf, 10, &val);
2274 mutex_lock(&data->update_lock);
2275 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2276 nct6775_write_temp(data, data->reg_temp[index][nr],
2277 data->temp[index][nr]);
2278 mutex_unlock(&data->update_lock);
2283 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2285 struct nct6775_data *data = nct6775_update_device(dev);
2286 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2288 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2292 store_temp_offset(struct device *dev, struct device_attribute *attr,
2293 const char *buf, size_t count)
2295 struct nct6775_data *data = dev_get_drvdata(dev);
2296 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2297 int nr = sattr->index;
2301 err = kstrtol(buf, 10, &val);
2305 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2307 mutex_lock(&data->update_lock);
2308 data->temp_offset[nr] = val;
2309 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2310 mutex_unlock(&data->update_lock);
2316 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2318 struct nct6775_data *data = nct6775_update_device(dev);
2319 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2320 int nr = sattr->index;
2322 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2326 store_temp_type(struct device *dev, struct device_attribute *attr,
2327 const char *buf, size_t count)
2329 struct nct6775_data *data = nct6775_update_device(dev);
2330 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2331 int nr = sattr->index;
2334 u8 vbat, diode, vbit, dbit;
2336 err = kstrtoul(buf, 10, &val);
2340 if (val != 1 && val != 3 && val != 4)
2343 mutex_lock(&data->update_lock);
2345 data->temp_type[nr] = val;
2347 dbit = data->DIODE_MASK << nr;
2348 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2349 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2351 case 1: /* CPU diode (diode, current mode) */
2355 case 3: /* diode, voltage mode */
2358 case 4: /* thermistor */
2361 nct6775_write_value(data, data->REG_VBAT, vbat);
2362 nct6775_write_value(data, data->REG_DIODE, diode);
2364 mutex_unlock(&data->update_lock);
2368 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2369 struct attribute *attr, int index)
2371 struct device *dev = container_of(kobj, struct device, kobj);
2372 struct nct6775_data *data = dev_get_drvdata(dev);
2373 int temp = index / 10; /* temp index */
2374 int nr = index % 10; /* attribute index */
2376 if (!(data->have_temp & BIT(temp)))
2379 if (nr == 1 && !data->temp_label)
2382 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2383 return 0; /* alarm */
2385 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2386 return 0; /* beep */
2388 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2391 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2394 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2397 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2400 /* offset and type only apply to fixed sensors */
2401 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2407 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2408 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2409 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2411 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2412 show_temp, store_temp, 0, 2);
2413 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2415 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2417 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2418 show_temp_offset, store_temp_offset, 0);
2419 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2420 store_temp_type, 0);
2421 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2422 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2423 store_temp_beep, 0);
2426 * nct6775_temp_is_visible uses the index into the following array
2427 * to determine if attributes should be created or not.
2428 * Any change in order or content must be matched.
2430 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2431 &sensor_dev_template_temp_input,
2432 &sensor_dev_template_temp_label,
2433 &sensor_dev_template_temp_alarm, /* 2 */
2434 &sensor_dev_template_temp_beep, /* 3 */
2435 &sensor_dev_template_temp_max, /* 4 */
2436 &sensor_dev_template_temp_max_hyst, /* 5 */
2437 &sensor_dev_template_temp_crit, /* 6 */
2438 &sensor_dev_template_temp_lcrit, /* 7 */
2439 &sensor_dev_template_temp_offset, /* 8 */
2440 &sensor_dev_template_temp_type, /* 9 */
2444 static const struct sensor_template_group nct6775_temp_template_group = {
2445 .templates = nct6775_attributes_temp_template,
2446 .is_visible = nct6775_temp_is_visible,
2451 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2453 struct nct6775_data *data = nct6775_update_device(dev);
2454 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2456 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2460 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2461 const char *buf, size_t count)
2463 struct nct6775_data *data = dev_get_drvdata(dev);
2464 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2465 int nr = sattr->index;
2470 err = kstrtoul(buf, 10, &val);
2477 /* Setting DC mode (0) is not supported for all chips/channels */
2478 if (data->REG_PWM_MODE[nr] == 0) {
2484 mutex_lock(&data->update_lock);
2485 data->pwm_mode[nr] = val;
2486 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2487 reg &= ~data->PWM_MODE_MASK[nr];
2489 reg |= data->PWM_MODE_MASK[nr];
2490 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2491 mutex_unlock(&data->update_lock);
2496 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2498 struct nct6775_data *data = nct6775_update_device(dev);
2499 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2501 int index = sattr->index;
2505 * For automatic fan control modes, show current pwm readings.
2506 * Otherwise, show the configured value.
2508 if (index == 0 && data->pwm_enable[nr] > manual)
2509 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2511 pwm = data->pwm[index][nr];
2513 return sprintf(buf, "%d\n", pwm);
2517 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2520 struct nct6775_data *data = dev_get_drvdata(dev);
2521 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2523 int index = sattr->index;
2525 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2527 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2531 err = kstrtoul(buf, 10, &val);
2534 val = clamp_val(val, minval[index], maxval[index]);
2536 mutex_lock(&data->update_lock);
2537 data->pwm[index][nr] = val;
2538 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2539 if (index == 2) { /* floor: disable if val == 0 */
2540 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2544 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2546 mutex_unlock(&data->update_lock);
2550 /* Returns 0 if OK, -EINVAL otherwise */
2551 static int check_trip_points(struct nct6775_data *data, int nr)
2555 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2556 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2559 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2560 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2563 /* validate critical temperature and pwm if enabled (pwm > 0) */
2564 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2565 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2566 data->auto_temp[nr][data->auto_pwm_num] ||
2567 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2568 data->auto_pwm[nr][data->auto_pwm_num])
2574 static void pwm_update_registers(struct nct6775_data *data, int nr)
2578 switch (data->pwm_enable[nr]) {
2583 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2584 reg = (reg & ~data->tolerance_mask) |
2585 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2586 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2587 nct6775_write_value(data, data->REG_TARGET[nr],
2588 data->target_speed[nr] & 0xff);
2589 if (data->REG_TOLERANCE_H) {
2590 reg = (data->target_speed[nr] >> 8) & 0x0f;
2591 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2592 nct6775_write_value(data,
2593 data->REG_TOLERANCE_H[nr],
2597 case thermal_cruise:
2598 nct6775_write_value(data, data->REG_TARGET[nr],
2599 data->target_temp[nr]);
2602 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2603 reg = (reg & ~data->tolerance_mask) |
2604 data->temp_tolerance[0][nr];
2605 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2611 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2613 struct nct6775_data *data = nct6775_update_device(dev);
2614 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2616 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2620 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2621 const char *buf, size_t count)
2623 struct nct6775_data *data = dev_get_drvdata(dev);
2624 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2625 int nr = sattr->index;
2630 err = kstrtoul(buf, 10, &val);
2637 if (val == sf3 && data->kind != nct6775)
2640 if (val == sf4 && check_trip_points(data, nr)) {
2641 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2642 dev_err(dev, "Adjust trip points and try again\n");
2646 mutex_lock(&data->update_lock);
2647 data->pwm_enable[nr] = val;
2650 * turn off pwm control: select manual mode, set pwm to maximum
2652 data->pwm[0][nr] = 255;
2653 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2655 pwm_update_registers(data, nr);
2656 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2658 reg |= pwm_enable_to_reg(val) << 4;
2659 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2660 mutex_unlock(&data->update_lock);
2665 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2669 for (i = 0; i < NUM_TEMP; i++) {
2670 if (!(data->have_temp & BIT(i)))
2672 if (src == data->temp_src[i]) {
2678 return sprintf(buf, "%d\n", sel);
2682 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2684 struct nct6775_data *data = nct6775_update_device(dev);
2685 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2686 int index = sattr->index;
2688 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2692 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2693 const char *buf, size_t count)
2695 struct nct6775_data *data = nct6775_update_device(dev);
2696 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2697 int nr = sattr->index;
2701 err = kstrtoul(buf, 10, &val);
2704 if (val == 0 || val > NUM_TEMP)
2706 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2709 mutex_lock(&data->update_lock);
2710 src = data->temp_src[val - 1];
2711 data->pwm_temp_sel[nr] = src;
2712 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2715 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2716 mutex_unlock(&data->update_lock);
2722 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2725 struct nct6775_data *data = nct6775_update_device(dev);
2726 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2727 int index = sattr->index;
2729 return show_pwm_temp_sel_common(data, buf,
2730 data->pwm_weight_temp_sel[index]);
2734 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2735 const char *buf, size_t count)
2737 struct nct6775_data *data = nct6775_update_device(dev);
2738 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2739 int nr = sattr->index;
2743 err = kstrtoul(buf, 10, &val);
2748 val = array_index_nospec(val, NUM_TEMP + 1);
2749 if (val && (!(data->have_temp & BIT(val - 1)) ||
2750 !data->temp_src[val - 1]))
2753 mutex_lock(&data->update_lock);
2755 src = data->temp_src[val - 1];
2756 data->pwm_weight_temp_sel[nr] = src;
2757 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2759 reg |= (src | 0x80);
2760 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2762 data->pwm_weight_temp_sel[nr] = 0;
2763 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2765 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2767 mutex_unlock(&data->update_lock);
2773 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2775 struct nct6775_data *data = nct6775_update_device(dev);
2776 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2778 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2782 store_target_temp(struct device *dev, struct device_attribute *attr,
2783 const char *buf, size_t count)
2785 struct nct6775_data *data = dev_get_drvdata(dev);
2786 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2787 int nr = sattr->index;
2791 err = kstrtoul(buf, 10, &val);
2795 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2796 data->target_temp_mask);
2798 mutex_lock(&data->update_lock);
2799 data->target_temp[nr] = val;
2800 pwm_update_registers(data, nr);
2801 mutex_unlock(&data->update_lock);
2806 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2808 struct nct6775_data *data = nct6775_update_device(dev);
2809 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2810 int nr = sattr->index;
2812 return sprintf(buf, "%d\n",
2813 fan_from_reg16(data->target_speed[nr],
2814 data->fan_div[nr]));
2818 store_target_speed(struct device *dev, struct device_attribute *attr,
2819 const char *buf, size_t count)
2821 struct nct6775_data *data = dev_get_drvdata(dev);
2822 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2823 int nr = sattr->index;
2828 err = kstrtoul(buf, 10, &val);
2832 val = clamp_val(val, 0, 1350000U);
2833 speed = fan_to_reg(val, data->fan_div[nr]);
2835 mutex_lock(&data->update_lock);
2836 data->target_speed[nr] = speed;
2837 pwm_update_registers(data, nr);
2838 mutex_unlock(&data->update_lock);
2843 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2846 struct nct6775_data *data = nct6775_update_device(dev);
2847 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2849 int index = sattr->index;
2851 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2855 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2856 const char *buf, size_t count)
2858 struct nct6775_data *data = dev_get_drvdata(dev);
2859 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2861 int index = sattr->index;
2865 err = kstrtoul(buf, 10, &val);
2869 /* Limit tolerance as needed */
2870 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2872 mutex_lock(&data->update_lock);
2873 data->temp_tolerance[index][nr] = val;
2875 pwm_update_registers(data, nr);
2877 nct6775_write_value(data,
2878 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2880 mutex_unlock(&data->update_lock);
2885 * Fan speed tolerance is a tricky beast, since the associated register is
2886 * a tick counter, but the value is reported and configured as rpm.
2887 * Compute resulting low and high rpm values and report the difference.
2888 * A fan speed tolerance only makes sense if a fan target speed has been
2889 * configured, so only display values other than 0 if that is the case.
2892 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2895 struct nct6775_data *data = nct6775_update_device(dev);
2896 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2897 int nr = sattr->index;
2898 int target = data->target_speed[nr];
2902 int low = target - data->target_speed_tolerance[nr];
2903 int high = target + data->target_speed_tolerance[nr];
2912 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2913 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2916 return sprintf(buf, "%d\n", tolerance);
2920 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2921 const char *buf, size_t count)
2923 struct nct6775_data *data = dev_get_drvdata(dev);
2924 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2925 int nr = sattr->index;
2930 err = kstrtoul(buf, 10, &val);
2934 high = fan_from_reg16(data->target_speed[nr],
2935 data->fan_div[nr]) + val;
2936 low = fan_from_reg16(data->target_speed[nr],
2937 data->fan_div[nr]) - val;
2943 val = (fan_to_reg(low, data->fan_div[nr]) -
2944 fan_to_reg(high, data->fan_div[nr])) / 2;
2946 /* Limit tolerance as needed */
2947 val = clamp_val(val, 0, data->speed_tolerance_limit);
2949 mutex_lock(&data->update_lock);
2950 data->target_speed_tolerance[nr] = val;
2951 pwm_update_registers(data, nr);
2952 mutex_unlock(&data->update_lock);
2956 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2957 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2959 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2960 store_pwm_enable, 0);
2961 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2962 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2963 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2964 show_target_temp, store_target_temp, 0);
2965 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2966 show_target_speed, store_target_speed, 0);
2967 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2968 show_speed_tolerance, store_speed_tolerance, 0);
2970 /* Smart Fan registers */
2973 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2975 struct nct6775_data *data = nct6775_update_device(dev);
2976 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2978 int index = sattr->index;
2980 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2984 store_weight_temp(struct device *dev, struct device_attribute *attr,
2985 const char *buf, size_t count)
2987 struct nct6775_data *data = dev_get_drvdata(dev);
2988 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2990 int index = sattr->index;
2994 err = kstrtoul(buf, 10, &val);
2998 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
3000 mutex_lock(&data->update_lock);
3001 data->weight_temp[index][nr] = val;
3002 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
3003 mutex_unlock(&data->update_lock);
3007 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
3008 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
3009 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
3010 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
3011 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
3012 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
3013 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
3014 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
3015 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
3016 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
3017 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
3018 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
3021 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
3023 struct nct6775_data *data = nct6775_update_device(dev);
3024 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3026 int index = sattr->index;
3028 return sprintf(buf, "%d\n",
3029 step_time_from_reg(data->fan_time[index][nr],
3030 data->pwm_mode[nr]));
3034 store_fan_time(struct device *dev, struct device_attribute *attr,
3035 const char *buf, size_t count)
3037 struct nct6775_data *data = dev_get_drvdata(dev);
3038 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3040 int index = sattr->index;
3044 err = kstrtoul(buf, 10, &val);
3048 val = step_time_to_reg(val, data->pwm_mode[nr]);
3049 mutex_lock(&data->update_lock);
3050 data->fan_time[index][nr] = val;
3051 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3052 mutex_unlock(&data->update_lock);
3057 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3059 struct nct6775_data *data = nct6775_update_device(dev);
3060 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3062 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3066 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3067 const char *buf, size_t count)
3069 struct nct6775_data *data = dev_get_drvdata(dev);
3070 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3072 int point = sattr->index;
3077 err = kstrtoul(buf, 10, &val);
3083 if (point == data->auto_pwm_num) {
3084 if (data->kind != nct6775 && !val)
3086 if (data->kind != nct6779 && val)
3090 mutex_lock(&data->update_lock);
3091 data->auto_pwm[nr][point] = val;
3092 if (point < data->auto_pwm_num) {
3093 nct6775_write_value(data,
3094 NCT6775_AUTO_PWM(data, nr, point),
3095 data->auto_pwm[nr][point]);
3097 switch (data->kind) {
3099 /* disable if needed (pwm == 0) */
3100 reg = nct6775_read_value(data,
3101 NCT6775_REG_CRITICAL_ENAB[nr]);
3106 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3110 break; /* always enabled, nothing to do */
3120 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3122 reg = nct6775_read_value(data,
3123 data->REG_CRITICAL_PWM_ENABLE[nr]);
3125 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3127 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3128 nct6775_write_value(data,
3129 data->REG_CRITICAL_PWM_ENABLE[nr],
3134 mutex_unlock(&data->update_lock);
3139 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3141 struct nct6775_data *data = nct6775_update_device(dev);
3142 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3144 int point = sattr->index;
3147 * We don't know for sure if the temperature is signed or unsigned.
3148 * Assume it is unsigned.
3150 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3154 store_auto_temp(struct device *dev, struct device_attribute *attr,
3155 const char *buf, size_t count)
3157 struct nct6775_data *data = dev_get_drvdata(dev);
3158 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3160 int point = sattr->index;
3164 err = kstrtoul(buf, 10, &val);
3170 mutex_lock(&data->update_lock);
3171 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3172 if (point < data->auto_pwm_num) {
3173 nct6775_write_value(data,
3174 NCT6775_AUTO_TEMP(data, nr, point),
3175 data->auto_temp[nr][point]);
3177 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3178 data->auto_temp[nr][point]);
3180 mutex_unlock(&data->update_lock);
3184 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3185 struct attribute *attr, int index)
3187 struct device *dev = container_of(kobj, struct device, kobj);
3188 struct nct6775_data *data = dev_get_drvdata(dev);
3189 int pwm = index / 36; /* pwm index */
3190 int nr = index % 36; /* attribute index */
3192 if (!(data->has_pwm & BIT(pwm)))
3195 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3196 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3198 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3200 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3202 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3205 if (nr >= 22 && nr <= 35) { /* auto point */
3206 int api = (nr - 22) / 2; /* auto point index */
3208 if (api > data->auto_pwm_num)
3214 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3215 show_fan_time, store_fan_time, 0, 0);
3216 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3217 show_fan_time, store_fan_time, 0, 1);
3218 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3219 show_fan_time, store_fan_time, 0, 2);
3220 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3222 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3224 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3225 show_temp_tolerance, store_temp_tolerance, 0, 0);
3226 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3227 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3230 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3233 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3236 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3237 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3238 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3239 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3241 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3242 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3243 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3244 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3246 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3247 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3248 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3249 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3251 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3252 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3253 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3254 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3256 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3257 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3258 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3259 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3261 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3262 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3263 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3264 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3266 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3267 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3268 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3269 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3272 * nct6775_pwm_is_visible uses the index into the following array
3273 * to determine if attributes should be created or not.
3274 * Any change in order or content must be matched.
3276 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3277 &sensor_dev_template_pwm,
3278 &sensor_dev_template_pwm_mode,
3279 &sensor_dev_template_pwm_enable,
3280 &sensor_dev_template_pwm_temp_sel,
3281 &sensor_dev_template_pwm_temp_tolerance,
3282 &sensor_dev_template_pwm_crit_temp_tolerance,
3283 &sensor_dev_template_pwm_target_temp,
3284 &sensor_dev_template_fan_target,
3285 &sensor_dev_template_fan_tolerance,
3286 &sensor_dev_template_pwm_stop_time,
3287 &sensor_dev_template_pwm_step_up_time,
3288 &sensor_dev_template_pwm_step_down_time,
3289 &sensor_dev_template_pwm_start,
3290 &sensor_dev_template_pwm_floor,
3291 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3292 &sensor_dev_template_pwm_weight_temp_step,
3293 &sensor_dev_template_pwm_weight_temp_step_tol,
3294 &sensor_dev_template_pwm_weight_temp_step_base,
3295 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3296 &sensor_dev_template_pwm_max, /* 19 */
3297 &sensor_dev_template_pwm_step, /* 20 */
3298 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3299 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3300 &sensor_dev_template_pwm_auto_point1_temp,
3301 &sensor_dev_template_pwm_auto_point2_pwm,
3302 &sensor_dev_template_pwm_auto_point2_temp,
3303 &sensor_dev_template_pwm_auto_point3_pwm,
3304 &sensor_dev_template_pwm_auto_point3_temp,
3305 &sensor_dev_template_pwm_auto_point4_pwm,
3306 &sensor_dev_template_pwm_auto_point4_temp,
3307 &sensor_dev_template_pwm_auto_point5_pwm,
3308 &sensor_dev_template_pwm_auto_point5_temp,
3309 &sensor_dev_template_pwm_auto_point6_pwm,
3310 &sensor_dev_template_pwm_auto_point6_temp,
3311 &sensor_dev_template_pwm_auto_point7_pwm,
3312 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3317 static const struct sensor_template_group nct6775_pwm_template_group = {
3318 .templates = nct6775_attributes_pwm_template,
3319 .is_visible = nct6775_pwm_is_visible,
3324 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3326 struct nct6775_data *data = dev_get_drvdata(dev);
3328 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3331 static DEVICE_ATTR_RO(cpu0_vid);
3333 /* Case open detection */
3336 clear_caseopen(struct device *dev, struct device_attribute *attr,
3337 const char *buf, size_t count)
3339 struct nct6775_data *data = dev_get_drvdata(dev);
3340 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3345 if (kstrtoul(buf, 10, &val) || val != 0)
3348 mutex_lock(&data->update_lock);
3351 * Use CR registers to clear caseopen status.
3352 * The CR registers are the same for all chips, and not all chips
3353 * support clearing the caseopen status through "regular" registers.
3355 ret = superio_enter(data->sioreg);
3361 superio_select(data->sioreg, NCT6775_LD_ACPI);
3362 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3363 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3364 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3365 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3366 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3367 superio_exit(data->sioreg);
3369 data->valid = false; /* Force cache refresh */
3371 mutex_unlock(&data->update_lock);
3375 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3376 clear_caseopen, INTRUSION_ALARM_BASE);
3377 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3378 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3379 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3380 store_beep, INTRUSION_ALARM_BASE);
3381 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3382 store_beep, INTRUSION_ALARM_BASE + 1);
3383 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3384 store_beep, BEEP_ENABLE_BASE);
3386 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3387 struct attribute *attr, int index)
3389 struct device *dev = container_of(kobj, struct device, kobj);
3390 struct nct6775_data *data = dev_get_drvdata(dev);
3392 if (index == 0 && !data->have_vid)
3395 if (index == 1 || index == 2) {
3396 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3400 if (index == 3 || index == 4) {
3401 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3409 * nct6775_other_is_visible uses the index into the following array
3410 * to determine if attributes should be created or not.
3411 * Any change in order or content must be matched.
3413 static struct attribute *nct6775_attributes_other[] = {
3414 &dev_attr_cpu0_vid.attr, /* 0 */
3415 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3416 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3417 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3418 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3419 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3424 static const struct attribute_group nct6775_group_other = {
3425 .attrs = nct6775_attributes_other,
3426 .is_visible = nct6775_other_is_visible,
3429 static inline void nct6775_init_device(struct nct6775_data *data)
3434 /* Start monitoring if needed */
3435 if (data->REG_CONFIG) {
3436 tmp = nct6775_read_value(data, data->REG_CONFIG);
3438 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3441 /* Enable temperature sensors if needed */
3442 for (i = 0; i < NUM_TEMP; i++) {
3443 if (!(data->have_temp & BIT(i)))
3445 if (!data->reg_temp_config[i])
3447 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3449 nct6775_write_value(data, data->reg_temp_config[i],
3453 /* Enable VBAT monitoring if needed */
3454 tmp = nct6775_read_value(data, data->REG_VBAT);
3456 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3458 diode = nct6775_read_value(data, data->REG_DIODE);
3460 for (i = 0; i < data->temp_fixed_num; i++) {
3461 if (!(data->have_temp_fixed & BIT(i)))
3463 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3465 = 3 - ((diode >> i) & data->DIODE_MASK);
3466 else /* thermistor */
3467 data->temp_type[i] = 4;
3472 nct6775_check_fan_inputs(struct nct6775_data *data)
3474 bool fan3pin = false, fan4pin = false, fan4min = false;
3475 bool fan5pin = false, fan6pin = false, fan7pin = false;
3476 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3477 bool pwm6pin = false, pwm7pin = false;
3478 int sioreg = data->sioreg;
3480 /* Store SIO_REG_ENABLE for use during resume */
3481 superio_select(sioreg, NCT6775_LD_HWM);
3482 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3484 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3485 if (data->kind == nct6775) {
3486 int cr2c = superio_inb(sioreg, 0x2c);
3488 fan3pin = cr2c & BIT(6);
3489 pwm3pin = cr2c & BIT(7);
3491 /* On NCT6775, fan4 shares pins with the fdc interface */
3492 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3493 } else if (data->kind == nct6776) {
3494 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3495 const char *board_vendor, *board_name;
3497 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3498 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3500 if (board_name && board_vendor &&
3501 !strcmp(board_vendor, "ASRock")) {
3503 * Auxiliary fan monitoring is not enabled on ASRock
3504 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3505 * Observed with BIOS version 2.00.
3507 if (!strcmp(board_name, "Z77 Pro4-M")) {
3508 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3509 data->sio_reg_enable |= 0xe0;
3510 superio_outb(sioreg, SIO_REG_ENABLE,
3511 data->sio_reg_enable);
3516 if (data->sio_reg_enable & 0x80)
3519 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3521 if (data->sio_reg_enable & 0x40)
3524 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3526 if (data->sio_reg_enable & 0x20)
3529 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3533 } else if (data->kind == nct6106) {
3534 int cr24 = superio_inb(sioreg, 0x24);
3536 fan3pin = !(cr24 & 0x80);
3537 pwm3pin = cr24 & 0x08;
3540 * NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D,
3541 * NCT6797D, NCT6798D
3543 int cr1a = superio_inb(sioreg, 0x1a);
3544 int cr1b = superio_inb(sioreg, 0x1b);
3545 int cr1c = superio_inb(sioreg, 0x1c);
3546 int cr1d = superio_inb(sioreg, 0x1d);
3547 int cr2a = superio_inb(sioreg, 0x2a);
3548 int cr2b = superio_inb(sioreg, 0x2b);
3549 int cr2d = superio_inb(sioreg, 0x2d);
3550 int cr2f = superio_inb(sioreg, 0x2f);
3551 bool dsw_en = cr2f & BIT(3);
3552 bool ddr4_en = cr2f & BIT(4);
3557 superio_select(sioreg, NCT6775_LD_12);
3558 cre0 = superio_inb(sioreg, 0xe0);
3559 creb = superio_inb(sioreg, 0xeb);
3560 cred = superio_inb(sioreg, 0xed);
3562 fan3pin = !(cr1c & BIT(5));
3563 fan4pin = !(cr1c & BIT(6));
3564 fan5pin = !(cr1c & BIT(7));
3566 pwm3pin = !(cr1c & BIT(0));
3567 pwm4pin = !(cr1c & BIT(1));
3568 pwm5pin = !(cr1c & BIT(2));
3570 switch (data->kind) {
3572 fan6pin = cr2d & BIT(1);
3573 pwm6pin = cr2d & BIT(0);
3576 fan6pin = !dsw_en && (cr2d & BIT(1));
3577 pwm6pin = !dsw_en && (cr2d & BIT(0));
3580 fan5pin |= cr1b & BIT(5);
3581 fan5pin |= creb & BIT(5);
3583 fan6pin = !dsw_en && (cr2d & BIT(1));
3584 fan6pin |= creb & BIT(3);
3586 pwm5pin |= cr2d & BIT(7);
3587 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3589 pwm6pin = !dsw_en && (cr2d & BIT(0));
3590 pwm6pin |= creb & BIT(2);
3593 fan5pin |= cr1b & BIT(5);
3594 fan5pin |= creb & BIT(5);
3596 fan6pin = (cr2a & BIT(4)) &&
3597 (!dsw_en || (cred & BIT(4)));
3598 fan6pin |= creb & BIT(3);
3600 pwm5pin |= cr2d & BIT(7);
3601 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3603 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3604 pwm6pin |= creb & BIT(2);
3607 fan5pin |= cr1b & BIT(5);
3608 fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0));
3609 fan5pin |= creb & BIT(5);
3611 fan6pin = (cr2a & BIT(4)) &&
3612 (!dsw_en || (cred & BIT(4)));
3613 fan6pin |= creb & BIT(3);
3615 fan7pin = !(cr2b & BIT(2));
3617 pwm5pin |= cr2d & BIT(7);
3618 pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0));
3619 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3621 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3622 pwm6pin |= creb & BIT(2);
3624 pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3627 fan5pin |= !ddr4_en && (cr1b & BIT(5));
3628 fan5pin |= creb & BIT(5);
3630 fan6pin = cr2a & BIT(4);
3631 fan6pin |= creb & BIT(3);
3633 fan7pin = cr1a & BIT(1);
3635 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3636 pwm5pin |= !ddr4_en && (cr2d & BIT(7));
3638 pwm6pin = creb & BIT(2);
3639 pwm6pin |= cred & BIT(2);
3641 pwm7pin = cr1d & BIT(4);
3644 fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3));
3645 fan6pin |= cr2a & BIT(4);
3646 fan6pin |= creb & BIT(5);
3648 fan7pin = cr1b & BIT(5);
3649 fan7pin |= !(cr2b & BIT(2));
3650 fan7pin |= creb & BIT(3);
3652 pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4));
3653 pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3));
3654 pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3656 pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3657 pwm7pin |= cr2d & BIT(7);
3658 pwm7pin |= creb & BIT(2);
3660 default: /* NCT6779D */
3667 /* fan 1 and 2 (0x03) are always present */
3668 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3669 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3670 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3671 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3672 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3673 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3676 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3677 int *available, int *mask)
3682 for (i = 0; i < data->pwm_num && *available; i++) {
3687 src = nct6775_read_value(data, regp[i]);
3689 if (!src || (*mask & BIT(src)))
3691 if (!(data->temp_mask & BIT(src)))
3694 index = __ffs(*available);
3695 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3696 *available &= ~BIT(index);
3701 static int nct6775_probe(struct platform_device *pdev)
3703 struct device *dev = &pdev->dev;
3704 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3705 struct nct6775_data *data;
3706 struct resource *res;
3708 int src, mask, available;
3709 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3710 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3711 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3712 int num_reg_temp, num_reg_temp_mon;
3714 struct attribute_group *group;
3715 struct device *hwmon_dev;
3716 int num_attr_groups = 0;
3718 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3719 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3723 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3728 data->kind = sio_data->kind;
3729 data->sioreg = sio_data->sioreg;
3730 data->addr = res->start;
3731 mutex_init(&data->update_lock);
3732 data->name = nct6775_device_names[data->kind];
3733 data->bank = 0xff; /* Force initial bank selection */
3734 platform_set_drvdata(pdev, data);
3736 switch (data->kind) {
3740 data->auto_pwm_num = 4;
3741 data->temp_fixed_num = 3;
3742 data->num_temp_alarms = 6;
3743 data->num_temp_beeps = 6;
3745 data->fan_from_reg = fan_from_reg13;
3746 data->fan_from_reg_min = fan_from_reg13;
3748 data->temp_label = nct6776_temp_label;
3749 data->temp_mask = NCT6776_TEMP_MASK;
3750 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3752 data->REG_VBAT = NCT6106_REG_VBAT;
3753 data->REG_DIODE = NCT6106_REG_DIODE;
3754 data->DIODE_MASK = NCT6106_DIODE_MASK;
3755 data->REG_VIN = NCT6106_REG_IN;
3756 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3757 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3758 data->REG_TARGET = NCT6106_REG_TARGET;
3759 data->REG_FAN = NCT6106_REG_FAN;
3760 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3761 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3762 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3763 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3764 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3765 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3766 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3767 data->REG_TOLERANCE_H = NCT6106_REG_TOLERANCE_H;
3768 data->REG_PWM[0] = NCT6106_REG_PWM;
3769 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3770 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3771 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3772 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3773 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3774 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3775 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3776 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3777 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3778 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3779 data->REG_CRITICAL_TEMP_TOLERANCE
3780 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3781 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3782 data->CRITICAL_PWM_ENABLE_MASK
3783 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3784 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3785 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3786 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3787 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3788 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3789 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3790 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3791 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3792 data->REG_ALARM = NCT6106_REG_ALARM;
3793 data->ALARM_BITS = NCT6106_ALARM_BITS;
3794 data->REG_BEEP = NCT6106_REG_BEEP;
3795 data->BEEP_BITS = NCT6106_BEEP_BITS;
3797 reg_temp = NCT6106_REG_TEMP;
3798 reg_temp_mon = NCT6106_REG_TEMP_MON;
3799 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3800 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3801 reg_temp_over = NCT6106_REG_TEMP_OVER;
3802 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3803 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3804 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3805 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3806 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3807 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3813 data->auto_pwm_num = 6;
3814 data->has_fan_div = true;
3815 data->temp_fixed_num = 3;
3816 data->num_temp_alarms = 3;
3817 data->num_temp_beeps = 3;
3819 data->ALARM_BITS = NCT6775_ALARM_BITS;
3820 data->BEEP_BITS = NCT6775_BEEP_BITS;
3822 data->fan_from_reg = fan_from_reg16;
3823 data->fan_from_reg_min = fan_from_reg8;
3824 data->target_temp_mask = 0x7f;
3825 data->tolerance_mask = 0x0f;
3826 data->speed_tolerance_limit = 15;
3828 data->temp_label = nct6775_temp_label;
3829 data->temp_mask = NCT6775_TEMP_MASK;
3830 data->virt_temp_mask = NCT6775_VIRT_TEMP_MASK;
3832 data->REG_CONFIG = NCT6775_REG_CONFIG;
3833 data->REG_VBAT = NCT6775_REG_VBAT;
3834 data->REG_DIODE = NCT6775_REG_DIODE;
3835 data->DIODE_MASK = NCT6775_DIODE_MASK;
3836 data->REG_VIN = NCT6775_REG_IN;
3837 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3838 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3839 data->REG_TARGET = NCT6775_REG_TARGET;
3840 data->REG_FAN = NCT6775_REG_FAN;
3841 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3842 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3843 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3844 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3845 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3846 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3847 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3848 data->REG_PWM[0] = NCT6775_REG_PWM;
3849 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3850 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3851 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3852 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3853 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3854 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3855 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3856 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3857 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3858 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3859 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3860 data->REG_CRITICAL_TEMP_TOLERANCE
3861 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3862 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3863 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3864 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3865 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3866 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3867 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3868 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3869 data->REG_ALARM = NCT6775_REG_ALARM;
3870 data->REG_BEEP = NCT6775_REG_BEEP;
3872 reg_temp = NCT6775_REG_TEMP;
3873 reg_temp_mon = NCT6775_REG_TEMP_MON;
3874 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3875 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3876 reg_temp_over = NCT6775_REG_TEMP_OVER;
3877 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3878 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3879 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3880 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3886 data->auto_pwm_num = 4;
3887 data->has_fan_div = false;
3888 data->temp_fixed_num = 3;
3889 data->num_temp_alarms = 3;
3890 data->num_temp_beeps = 6;
3892 data->ALARM_BITS = NCT6776_ALARM_BITS;
3893 data->BEEP_BITS = NCT6776_BEEP_BITS;
3895 data->fan_from_reg = fan_from_reg13;
3896 data->fan_from_reg_min = fan_from_reg13;
3897 data->target_temp_mask = 0xff;
3898 data->tolerance_mask = 0x07;
3899 data->speed_tolerance_limit = 63;
3901 data->temp_label = nct6776_temp_label;
3902 data->temp_mask = NCT6776_TEMP_MASK;
3903 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3905 data->REG_CONFIG = NCT6775_REG_CONFIG;
3906 data->REG_VBAT = NCT6775_REG_VBAT;
3907 data->REG_DIODE = NCT6775_REG_DIODE;
3908 data->DIODE_MASK = NCT6775_DIODE_MASK;
3909 data->REG_VIN = NCT6775_REG_IN;
3910 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3911 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3912 data->REG_TARGET = NCT6775_REG_TARGET;
3913 data->REG_FAN = NCT6775_REG_FAN;
3914 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3915 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3916 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3917 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3918 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3919 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3920 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3921 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3922 data->REG_PWM[0] = NCT6775_REG_PWM;
3923 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3924 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3925 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3926 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3927 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3928 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3929 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3930 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3931 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3932 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3933 data->REG_CRITICAL_TEMP_TOLERANCE
3934 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3935 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3936 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3937 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3938 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3939 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3940 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3941 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3942 data->REG_ALARM = NCT6775_REG_ALARM;
3943 data->REG_BEEP = NCT6776_REG_BEEP;
3945 reg_temp = NCT6775_REG_TEMP;
3946 reg_temp_mon = NCT6775_REG_TEMP_MON;
3947 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3948 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3949 reg_temp_over = NCT6775_REG_TEMP_OVER;
3950 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3951 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3952 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3953 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3959 data->auto_pwm_num = 4;
3960 data->has_fan_div = false;
3961 data->temp_fixed_num = 6;
3962 data->num_temp_alarms = 2;
3963 data->num_temp_beeps = 2;
3965 data->ALARM_BITS = NCT6779_ALARM_BITS;
3966 data->BEEP_BITS = NCT6779_BEEP_BITS;
3968 data->fan_from_reg = fan_from_reg_rpm;
3969 data->fan_from_reg_min = fan_from_reg13;
3970 data->target_temp_mask = 0xff;
3971 data->tolerance_mask = 0x07;
3972 data->speed_tolerance_limit = 63;
3974 data->temp_label = nct6779_temp_label;
3975 data->temp_mask = NCT6779_TEMP_MASK;
3976 data->virt_temp_mask = NCT6779_VIRT_TEMP_MASK;
3978 data->REG_CONFIG = NCT6775_REG_CONFIG;
3979 data->REG_VBAT = NCT6775_REG_VBAT;
3980 data->REG_DIODE = NCT6775_REG_DIODE;
3981 data->DIODE_MASK = NCT6775_DIODE_MASK;
3982 data->REG_VIN = NCT6779_REG_IN;
3983 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3984 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3985 data->REG_TARGET = NCT6775_REG_TARGET;
3986 data->REG_FAN = NCT6779_REG_FAN;
3987 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3988 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3989 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3990 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3991 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3992 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3993 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3994 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3995 data->REG_PWM[0] = NCT6775_REG_PWM;
3996 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3997 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3998 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3999 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
4000 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4001 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4002 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4003 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4004 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4005 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4006 data->REG_CRITICAL_TEMP_TOLERANCE
4007 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4008 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4009 data->CRITICAL_PWM_ENABLE_MASK
4010 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4011 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4012 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4013 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4014 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4015 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
4016 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
4017 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
4018 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
4019 data->REG_ALARM = NCT6779_REG_ALARM;
4020 data->REG_BEEP = NCT6776_REG_BEEP;
4022 reg_temp = NCT6779_REG_TEMP;
4023 reg_temp_mon = NCT6779_REG_TEMP_MON;
4024 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4025 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4026 reg_temp_over = NCT6779_REG_TEMP_OVER;
4027 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4028 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4029 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4030 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4041 data->pwm_num = (data->kind == nct6796 ||
4042 data->kind == nct6797 ||
4043 data->kind == nct6798) ? 7 : 6;
4044 data->auto_pwm_num = 4;
4045 data->has_fan_div = false;
4046 data->temp_fixed_num = 6;
4047 data->num_temp_alarms = 2;
4048 data->num_temp_beeps = 2;
4050 data->ALARM_BITS = NCT6791_ALARM_BITS;
4051 data->BEEP_BITS = NCT6779_BEEP_BITS;
4053 data->fan_from_reg = fan_from_reg_rpm;
4054 data->fan_from_reg_min = fan_from_reg13;
4055 data->target_temp_mask = 0xff;
4056 data->tolerance_mask = 0x07;
4057 data->speed_tolerance_limit = 63;
4059 switch (data->kind) {
4062 data->temp_label = nct6779_temp_label;
4063 data->temp_mask = NCT6791_TEMP_MASK;
4064 data->virt_temp_mask = NCT6791_VIRT_TEMP_MASK;
4067 data->temp_label = nct6792_temp_label;
4068 data->temp_mask = NCT6792_TEMP_MASK;
4069 data->virt_temp_mask = NCT6792_VIRT_TEMP_MASK;
4072 data->temp_label = nct6793_temp_label;
4073 data->temp_mask = NCT6793_TEMP_MASK;
4074 data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
4078 data->temp_label = nct6795_temp_label;
4079 data->temp_mask = NCT6795_TEMP_MASK;
4080 data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
4083 data->temp_label = nct6796_temp_label;
4084 data->temp_mask = NCT6796_TEMP_MASK;
4085 data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
4088 data->temp_label = nct6798_temp_label;
4089 data->temp_mask = NCT6798_TEMP_MASK;
4090 data->virt_temp_mask = NCT6798_VIRT_TEMP_MASK;
4094 data->REG_CONFIG = NCT6775_REG_CONFIG;
4095 data->REG_VBAT = NCT6775_REG_VBAT;
4096 data->REG_DIODE = NCT6775_REG_DIODE;
4097 data->DIODE_MASK = NCT6775_DIODE_MASK;
4098 data->REG_VIN = NCT6779_REG_IN;
4099 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
4100 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4101 data->REG_TARGET = NCT6775_REG_TARGET;
4102 data->REG_FAN = NCT6779_REG_FAN;
4103 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4104 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4105 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4106 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4107 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4108 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4109 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4110 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4111 data->REG_PWM[0] = NCT6775_REG_PWM;
4112 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4113 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4114 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4115 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4116 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4117 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4118 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4119 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4120 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4121 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4122 data->REG_CRITICAL_TEMP_TOLERANCE
4123 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4124 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4125 data->CRITICAL_PWM_ENABLE_MASK
4126 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4127 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4128 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4129 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4130 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4131 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4132 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4133 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4134 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4135 data->REG_ALARM = NCT6791_REG_ALARM;
4136 if (data->kind == nct6791)
4137 data->REG_BEEP = NCT6776_REG_BEEP;
4139 data->REG_BEEP = NCT6792_REG_BEEP;
4141 reg_temp = NCT6779_REG_TEMP;
4142 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4143 if (data->kind == nct6791) {
4144 reg_temp_mon = NCT6779_REG_TEMP_MON;
4145 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4147 reg_temp_mon = NCT6792_REG_TEMP_MON;
4148 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4150 reg_temp_over = NCT6779_REG_TEMP_OVER;
4151 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4152 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4153 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4154 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4160 data->have_in = BIT(data->in_num) - 1;
4161 data->have_temp = 0;
4164 * On some boards, not all available temperature sources are monitored,
4165 * even though some of the monitoring registers are unused.
4166 * Get list of unused monitoring registers, then detect if any fan
4167 * controls are configured to use unmonitored temperature sources.
4168 * If so, assign the unmonitored temperature sources to available
4169 * monitoring registers.
4173 for (i = 0; i < num_reg_temp; i++) {
4174 if (reg_temp[i] == 0)
4177 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4178 if (!src || (mask & BIT(src)))
4179 available |= BIT(i);
4185 * Now find unmonitored temperature registers and enable monitoring
4186 * if additional monitoring registers are available.
4188 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4189 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4192 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4193 for (i = 0; i < num_reg_temp; i++) {
4194 if (reg_temp[i] == 0)
4197 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4198 if (!src || (mask & BIT(src)))
4201 if (!(data->temp_mask & BIT(src))) {
4203 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4204 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4210 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4211 if (src <= data->temp_fixed_num) {
4212 data->have_temp |= BIT(src - 1);
4213 data->have_temp_fixed |= BIT(src - 1);
4214 data->reg_temp[0][src - 1] = reg_temp[i];
4215 data->reg_temp[1][src - 1] = reg_temp_over[i];
4216 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4217 if (reg_temp_crit_h && reg_temp_crit_h[i])
4218 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4219 else if (reg_temp_crit[src - 1])
4220 data->reg_temp[3][src - 1]
4221 = reg_temp_crit[src - 1];
4222 if (reg_temp_crit_l && reg_temp_crit_l[i])
4223 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4224 data->reg_temp_config[src - 1] = reg_temp_config[i];
4225 data->temp_src[src - 1] = src;
4232 /* Use dynamic index for other sources */
4233 data->have_temp |= BIT(s);
4234 data->reg_temp[0][s] = reg_temp[i];
4235 data->reg_temp[1][s] = reg_temp_over[i];
4236 data->reg_temp[2][s] = reg_temp_hyst[i];
4237 data->reg_temp_config[s] = reg_temp_config[i];
4238 if (reg_temp_crit_h && reg_temp_crit_h[i])
4239 data->reg_temp[3][s] = reg_temp_crit_h[i];
4240 else if (reg_temp_crit[src - 1])
4241 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4242 if (reg_temp_crit_l && reg_temp_crit_l[i])
4243 data->reg_temp[4][s] = reg_temp_crit_l[i];
4245 data->temp_src[s] = src;
4250 * Repeat with temperatures used for fan control.
4251 * This set of registers does not support limits.
4253 for (i = 0; i < num_reg_temp_mon; i++) {
4254 if (reg_temp_mon[i] == 0)
4257 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4261 if (!(data->temp_mask & BIT(src))) {
4263 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4264 src, i, data->REG_TEMP_SEL[i],
4270 * For virtual temperature sources, the 'virtual' temperature
4271 * for each fan reflects a different temperature, and there
4272 * are no duplicates.
4274 if (!(data->virt_temp_mask & BIT(src))) {
4275 if (mask & BIT(src))
4280 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4281 if (src <= data->temp_fixed_num) {
4282 if (data->have_temp & BIT(src - 1))
4284 data->have_temp |= BIT(src - 1);
4285 data->have_temp_fixed |= BIT(src - 1);
4286 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4287 data->temp_src[src - 1] = src;
4294 /* Use dynamic index for other sources */
4295 data->have_temp |= BIT(s);
4296 data->reg_temp[0][s] = reg_temp_mon[i];
4297 data->temp_src[s] = src;
4301 #ifdef USE_ALTERNATE
4303 * Go through the list of alternate temp registers and enable
4305 * The temperature is already monitored if the respective bit in <mask>
4308 for (i = 0; i < 31; i++) {
4309 if (!(data->temp_mask & BIT(i + 1)))
4311 if (!reg_temp_alternate[i])
4313 if (mask & BIT(i + 1))
4315 if (i < data->temp_fixed_num) {
4316 if (data->have_temp & BIT(i))
4318 data->have_temp |= BIT(i);
4319 data->have_temp_fixed |= BIT(i);
4320 data->reg_temp[0][i] = reg_temp_alternate[i];
4321 if (i < num_reg_temp) {
4322 data->reg_temp[1][i] = reg_temp_over[i];
4323 data->reg_temp[2][i] = reg_temp_hyst[i];
4325 data->temp_src[i] = i + 1;
4329 if (s >= NUM_TEMP) /* Abort if no more space */
4332 data->have_temp |= BIT(s);
4333 data->reg_temp[0][s] = reg_temp_alternate[i];
4334 data->temp_src[s] = i + 1;
4337 #endif /* USE_ALTERNATE */
4339 /* Initialize the chip */
4340 nct6775_init_device(data);
4342 err = superio_enter(sio_data->sioreg);
4346 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4347 switch (data->kind) {
4349 data->have_vid = (cr2a & 0x40);
4352 data->have_vid = (cr2a & 0x60) == 0x40;
4368 * We can get the VID input values directly at logical device D 0xe3.
4370 if (data->have_vid) {
4371 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4372 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4373 data->vrm = vid_which_vrm();
4379 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4380 tmp = superio_inb(sio_data->sioreg,
4381 NCT6775_REG_CR_FAN_DEBOUNCE);
4382 switch (data->kind) {
4403 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4405 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4409 nct6775_check_fan_inputs(data);
4411 superio_exit(sio_data->sioreg);
4413 /* Read fan clock dividers immediately */
4414 nct6775_init_fan_common(dev, data);
4416 /* Register sysfs hooks */
4417 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4420 return PTR_ERR(group);
4422 data->groups[num_attr_groups++] = group;
4424 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4425 fls(data->have_in));
4427 return PTR_ERR(group);
4429 data->groups[num_attr_groups++] = group;
4431 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4432 fls(data->has_fan));
4434 return PTR_ERR(group);
4436 data->groups[num_attr_groups++] = group;
4438 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4439 fls(data->have_temp));
4441 return PTR_ERR(group);
4443 data->groups[num_attr_groups++] = group;
4444 data->groups[num_attr_groups++] = &nct6775_group_other;
4446 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4447 data, data->groups);
4448 return PTR_ERR_OR_ZERO(hwmon_dev);
4451 static void nct6791_enable_io_mapping(int sioaddr)
4455 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4457 pr_info("Enabling hardware monitor logical device mappings.\n");
4458 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4463 static int __maybe_unused nct6775_suspend(struct device *dev)
4465 struct nct6775_data *data = nct6775_update_device(dev);
4467 mutex_lock(&data->update_lock);
4468 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4469 if (data->kind == nct6775) {
4470 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4471 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4473 mutex_unlock(&data->update_lock);
4478 static int __maybe_unused nct6775_resume(struct device *dev)
4480 struct nct6775_data *data = dev_get_drvdata(dev);
4481 int sioreg = data->sioreg;
4485 mutex_lock(&data->update_lock);
4486 data->bank = 0xff; /* Force initial bank selection */
4488 err = superio_enter(sioreg);
4492 superio_select(sioreg, NCT6775_LD_HWM);
4493 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4494 if (reg != data->sio_reg_enable)
4495 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4497 if (data->kind == nct6791 || data->kind == nct6792 ||
4498 data->kind == nct6793 || data->kind == nct6795 ||
4499 data->kind == nct6796 || data->kind == nct6797 ||
4500 data->kind == nct6798)
4501 nct6791_enable_io_mapping(sioreg);
4503 superio_exit(sioreg);
4505 /* Restore limits */
4506 for (i = 0; i < data->in_num; i++) {
4507 if (!(data->have_in & BIT(i)))
4510 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4512 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4516 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4517 if (!(data->has_fan_min & BIT(i)))
4520 nct6775_write_value(data, data->REG_FAN_MIN[i],
4524 for (i = 0; i < NUM_TEMP; i++) {
4525 if (!(data->have_temp & BIT(i)))
4528 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4529 if (data->reg_temp[j][i])
4530 nct6775_write_temp(data, data->reg_temp[j][i],
4534 /* Restore other settings */
4535 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4536 if (data->kind == nct6775) {
4537 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4538 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4542 /* Force re-reading all values */
4543 data->valid = false;
4544 mutex_unlock(&data->update_lock);
4549 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4551 static struct platform_driver nct6775_driver = {
4554 .pm = &nct6775_dev_pm_ops,
4556 .probe = nct6775_probe,
4559 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4560 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4566 err = superio_enter(sioaddr);
4570 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4571 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4572 if (force_id && val != 0xffff)
4575 switch (val & SIO_ID_MASK) {
4576 case SIO_NCT6106_ID:
4577 sio_data->kind = nct6106;
4579 case SIO_NCT6775_ID:
4580 sio_data->kind = nct6775;
4582 case SIO_NCT6776_ID:
4583 sio_data->kind = nct6776;
4585 case SIO_NCT6779_ID:
4586 sio_data->kind = nct6779;
4588 case SIO_NCT6791_ID:
4589 sio_data->kind = nct6791;
4591 case SIO_NCT6792_ID:
4592 sio_data->kind = nct6792;
4594 case SIO_NCT6793_ID:
4595 sio_data->kind = nct6793;
4597 case SIO_NCT6795_ID:
4598 sio_data->kind = nct6795;
4600 case SIO_NCT6796_ID:
4601 sio_data->kind = nct6796;
4603 case SIO_NCT6797_ID:
4604 sio_data->kind = nct6797;
4606 case SIO_NCT6798_ID:
4607 sio_data->kind = nct6798;
4611 pr_debug("unsupported chip ID: 0x%04x\n", val);
4612 superio_exit(sioaddr);
4616 /* We have a known chip, find the HWM I/O address */
4617 superio_select(sioaddr, NCT6775_LD_HWM);
4618 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4619 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4620 addr = val & IOREGION_ALIGNMENT;
4622 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4623 superio_exit(sioaddr);
4627 /* Activate logical device if needed */
4628 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4629 if (!(val & 0x01)) {
4630 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4631 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4634 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4635 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4636 sio_data->kind == nct6796 || sio_data->kind == nct6797 ||
4637 sio_data->kind == nct6798)
4638 nct6791_enable_io_mapping(sioaddr);
4640 superio_exit(sioaddr);
4641 pr_info("Found %s or compatible chip at %#x:%#x\n",
4642 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4643 sio_data->sioreg = sioaddr;
4649 * when Super-I/O functions move to a separate file, the Super-I/O
4650 * bus will manage the lifetime of the device and this module will only keep
4651 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4652 * must keep track of the device
4654 static struct platform_device *pdev[2];
4656 static int __init sensors_nct6775_init(void)
4661 struct resource res;
4662 struct nct6775_sio_data sio_data;
4663 int sioaddr[2] = { 0x2e, 0x4e };
4665 err = platform_driver_register(&nct6775_driver);
4670 * initialize sio_data->kind and sio_data->sioreg.
4672 * when Super-I/O functions move to a separate file, the Super-I/O
4673 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4674 * nct6775 hardware monitor, and call probe()
4676 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4677 address = nct6775_find(sioaddr[i], &sio_data);
4683 pdev[i] = platform_device_alloc(DRVNAME, address);
4686 goto exit_device_unregister;
4689 err = platform_device_add_data(pdev[i], &sio_data,
4690 sizeof(struct nct6775_sio_data));
4692 goto exit_device_put;
4694 memset(&res, 0, sizeof(res));
4696 res.start = address + IOREGION_OFFSET;
4697 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4698 res.flags = IORESOURCE_IO;
4700 err = acpi_check_resource_conflict(&res);
4702 platform_device_put(pdev[i]);
4707 err = platform_device_add_resources(pdev[i], &res, 1);
4709 goto exit_device_put;
4711 /* platform_device_add calls probe() */
4712 err = platform_device_add(pdev[i]);
4714 goto exit_device_put;
4718 goto exit_unregister;
4724 platform_device_put(pdev[i]);
4725 exit_device_unregister:
4728 platform_device_unregister(pdev[i]);
4731 platform_driver_unregister(&nct6775_driver);
4735 static void __exit sensors_nct6775_exit(void)
4739 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4741 platform_device_unregister(pdev[i]);
4743 platform_driver_unregister(&nct6775_driver);
4746 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4747 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4748 MODULE_LICENSE("GPL");
4750 module_init(sensors_nct6775_init);
4751 module_exit(sensors_nct6775_exit);