2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Supports the following chips:
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
66 #include <linux/nospec.h>
71 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
74 /* used to set data->name = nct6775_device_names[data->sio_kind] */
75 static const char * const nct6775_device_names[] = {
87 static const char * const nct6775_sio_names[] __initconst = {
99 static unsigned short force_id;
100 module_param(force_id, ushort, 0);
101 MODULE_PARM_DESC(force_id, "Override the detected device ID");
103 static unsigned short fan_debounce;
104 module_param(fan_debounce, ushort, 0);
105 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
107 #define DRVNAME "nct6775"
110 * Super-I/O constants and functions
113 #define NCT6775_LD_ACPI 0x0a
114 #define NCT6775_LD_HWM 0x0b
115 #define NCT6775_LD_VID 0x0d
116 #define NCT6775_LD_12 0x12
118 #define SIO_REG_LDSEL 0x07 /* Logical device select */
119 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
120 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
121 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
123 #define SIO_NCT6106_ID 0xc450
124 #define SIO_NCT6775_ID 0xb470
125 #define SIO_NCT6776_ID 0xc330
126 #define SIO_NCT6779_ID 0xc560
127 #define SIO_NCT6791_ID 0xc800
128 #define SIO_NCT6792_ID 0xc910
129 #define SIO_NCT6793_ID 0xd120
130 #define SIO_NCT6795_ID 0xd350
131 #define SIO_NCT6796_ID 0xd420
132 #define SIO_ID_MASK 0xFFF0
134 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
137 superio_outb(int ioreg, int reg, int val)
140 outb(val, ioreg + 1);
144 superio_inb(int ioreg, int reg)
147 return inb(ioreg + 1);
151 superio_select(int ioreg, int ld)
153 outb(SIO_REG_LDSEL, ioreg);
158 superio_enter(int ioreg)
161 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
163 if (!request_muxed_region(ioreg, 2, DRVNAME))
173 superio_exit(int ioreg)
177 outb(0x02, ioreg + 1);
178 release_region(ioreg, 2);
185 #define IOREGION_ALIGNMENT (~7)
186 #define IOREGION_OFFSET 5
187 #define IOREGION_LENGTH 2
188 #define ADDR_REG_OFFSET 0
189 #define DATA_REG_OFFSET 1
191 #define NCT6775_REG_BANK 0x4E
192 #define NCT6775_REG_CONFIG 0x40
195 * Not currently used:
196 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
197 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
198 * REG_MAN_ID is at port 0x4f
199 * REG_CHIP_ID is at port 0x58
202 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
203 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
205 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
206 #define NUM_REG_BEEP 5 /* Max number of beep registers */
210 /* Common and NCT6775 specific data */
212 /* Voltage min/max registers for nr=7..14 are in bank 5 */
214 static const u16 NCT6775_REG_IN_MAX[] = {
215 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
216 0x55c, 0x55e, 0x560, 0x562 };
217 static const u16 NCT6775_REG_IN_MIN[] = {
218 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
219 0x55d, 0x55f, 0x561, 0x563 };
220 static const u16 NCT6775_REG_IN[] = {
221 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
224 #define NCT6775_REG_VBAT 0x5D
225 #define NCT6775_REG_DIODE 0x5E
226 #define NCT6775_DIODE_MASK 0x02
228 #define NCT6775_REG_FANDIV1 0x506
229 #define NCT6775_REG_FANDIV2 0x507
231 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
233 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
235 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
237 static const s8 NCT6775_ALARM_BITS[] = {
238 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
239 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
241 6, 7, 11, -1, -1, /* fan1..fan5 */
242 -1, -1, -1, /* unused */
243 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
244 12, -1 }; /* intrusion0, intrusion1 */
246 #define FAN_ALARM_BASE 16
247 #define TEMP_ALARM_BASE 24
248 #define INTRUSION_ALARM_BASE 30
250 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
253 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
256 static const s8 NCT6775_BEEP_BITS[] = {
257 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
258 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
259 21, /* global beep enable */
260 6, 7, 11, 28, -1, /* fan1..fan5 */
261 -1, -1, -1, /* unused */
262 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
263 12, -1 }; /* intrusion0, intrusion1 */
265 #define BEEP_ENABLE_BASE 15
267 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
268 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
270 /* DC or PWM output fan configuration */
271 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
272 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
274 /* Advanced Fan control, some values are common for all fans */
276 static const u16 NCT6775_REG_TARGET[] = {
277 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
278 static const u16 NCT6775_REG_FAN_MODE[] = {
279 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
280 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
281 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
282 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
283 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
284 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
285 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
286 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
287 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
288 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
289 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
291 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
292 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
293 static const u16 NCT6775_REG_PWM[] = {
294 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
295 static const u16 NCT6775_REG_PWM_READ[] = {
296 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
298 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
299 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
300 static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
301 0x641, 0x642, 0x643, 0x644 };
302 static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
304 static const u16 NCT6775_REG_TEMP[] = {
305 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
307 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
309 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
310 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
311 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
312 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
313 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
314 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
316 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
317 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
319 static const u16 NCT6775_REG_TEMP_SEL[] = {
320 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
322 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
323 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
324 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
325 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
326 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
327 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
328 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
329 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
330 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
331 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
333 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
335 static const u16 NCT6775_REG_AUTO_TEMP[] = {
336 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
337 static const u16 NCT6775_REG_AUTO_PWM[] = {
338 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
340 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
341 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
343 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
345 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
346 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
347 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
348 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
350 static const char *const nct6775_temp_label[] = {
364 "PCH_CHIP_CPU_MAX_TEMP",
374 #define NCT6775_TEMP_MASK 0x001ffffe
375 #define NCT6775_VIRT_TEMP_MASK 0x00000000
377 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
383 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
394 /* NCT6776 specific data */
396 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
397 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
398 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
400 static const s8 NCT6776_ALARM_BITS[] = {
401 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
402 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
404 6, 7, 11, 10, 23, /* fan1..fan5 */
405 -1, -1, -1, /* unused */
406 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
407 12, 9 }; /* intrusion0, intrusion1 */
409 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
411 static const s8 NCT6776_BEEP_BITS[] = {
412 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
413 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
414 24, /* global beep enable */
415 25, 26, 27, 28, 29, /* fan1..fan5 */
416 -1, -1, -1, /* unused */
417 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
418 30, 31 }; /* intrusion0, intrusion1 */
420 static const u16 NCT6776_REG_TOLERANCE_H[] = {
421 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
423 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
424 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
426 static const u16 NCT6776_REG_FAN_MIN[] = {
427 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
428 static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
429 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
431 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
432 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
434 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
435 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
437 static const char *const nct6776_temp_label[] = {
452 "PCH_CHIP_CPU_MAX_TEMP",
463 #define NCT6776_TEMP_MASK 0x007ffffe
464 #define NCT6776_VIRT_TEMP_MASK 0x00000000
466 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
472 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
477 /* NCT6779 specific data */
479 static const u16 NCT6779_REG_IN[] = {
480 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
481 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
483 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
484 0x459, 0x45A, 0x45B, 0x568 };
486 static const s8 NCT6779_ALARM_BITS[] = {
487 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
488 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
490 6, 7, 11, 10, 23, /* fan1..fan5 */
491 -1, -1, -1, /* unused */
492 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
493 12, 9 }; /* intrusion0, intrusion1 */
495 static const s8 NCT6779_BEEP_BITS[] = {
496 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
497 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
498 24, /* global beep enable */
499 25, 26, 27, 28, 29, /* fan1..fan5 */
500 -1, -1, -1, /* unused */
501 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
502 30, 31 }; /* intrusion0, intrusion1 */
504 static const u16 NCT6779_REG_FAN[] = {
505 0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
506 static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
507 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
509 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
510 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
511 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
512 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
513 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
515 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
516 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
517 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
519 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
521 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
524 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
525 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
527 static const char *const nct6779_temp_label[] = {
546 "PCH_CHIP_CPU_MAX_TEMP",
562 #define NCT6779_TEMP_MASK 0x07ffff7e
563 #define NCT6779_VIRT_TEMP_MASK 0x00000000
564 #define NCT6791_TEMP_MASK 0x87ffff7e
565 #define NCT6791_VIRT_TEMP_MASK 0x80000000
567 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
568 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
569 0, 0, 0, 0, 0, 0, 0, 0,
570 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
573 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
578 /* NCT6791 specific data */
580 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
582 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
583 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
584 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
585 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
586 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
587 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
589 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
590 0x459, 0x45A, 0x45B, 0x568, 0x45D };
592 static const s8 NCT6791_ALARM_BITS[] = {
593 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
594 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
596 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
598 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
599 12, 9 }; /* intrusion0, intrusion1 */
601 /* NCT6792/NCT6793 specific data */
603 static const u16 NCT6792_REG_TEMP_MON[] = {
604 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
605 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
606 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
608 static const char *const nct6792_temp_label[] = {
627 "PCH_CHIP_CPU_MAX_TEMP",
636 "PECI Agent 0 Calibration",
637 "PECI Agent 1 Calibration",
643 #define NCT6792_TEMP_MASK 0x9fffff7e
644 #define NCT6792_VIRT_TEMP_MASK 0x80000000
646 static const char *const nct6793_temp_label[] = {
665 "PCH_CHIP_CPU_MAX_TEMP",
675 "PECI Agent 0 Calibration",
676 "PECI Agent 1 Calibration",
681 #define NCT6793_TEMP_MASK 0xbfff037e
682 #define NCT6793_VIRT_TEMP_MASK 0x80000000
684 static const char *const nct6795_temp_label[] = {
703 "PCH_CHIP_CPU_MAX_TEMP",
713 "PECI Agent 0 Calibration",
714 "PECI Agent 1 Calibration",
719 #define NCT6795_TEMP_MASK 0xbfffff7e
720 #define NCT6795_VIRT_TEMP_MASK 0x80000000
722 static const char *const nct6796_temp_label[] = {
741 "PCH_CHIP_CPU_MAX_TEMP",
751 "PECI Agent 0 Calibration",
752 "PECI Agent 1 Calibration",
757 #define NCT6796_TEMP_MASK 0xbfff0ffe
758 #define NCT6796_VIRT_TEMP_MASK 0x80000c00
760 /* NCT6102D/NCT6106D specific data */
762 #define NCT6106_REG_VBAT 0x318
763 #define NCT6106_REG_DIODE 0x319
764 #define NCT6106_DIODE_MASK 0x01
766 static const u16 NCT6106_REG_IN_MAX[] = {
767 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
768 static const u16 NCT6106_REG_IN_MIN[] = {
769 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
770 static const u16 NCT6106_REG_IN[] = {
771 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
773 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
774 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
775 static const u16 NCT6106_REG_TEMP_HYST[] = {
776 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
777 static const u16 NCT6106_REG_TEMP_OVER[] = {
778 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
779 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
780 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
781 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
782 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
783 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
784 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
785 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
787 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
788 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
789 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
790 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
792 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
793 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
794 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
795 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
796 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
797 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
798 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
799 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
801 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
802 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
803 0x11b, 0x12b, 0x13b };
805 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
806 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
807 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
809 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
810 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
811 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
812 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
813 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
814 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
816 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
818 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
819 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
820 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
821 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
822 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
823 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
825 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
826 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
828 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
829 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
831 static const s8 NCT6106_ALARM_BITS[] = {
832 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
833 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
835 32, 33, 34, -1, -1, /* fan1..fan5 */
836 -1, -1, -1, /* unused */
837 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
838 48, -1 /* intrusion0, intrusion1 */
841 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
842 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
844 static const s8 NCT6106_BEEP_BITS[] = {
845 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
846 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
847 32, /* global beep enable */
848 24, 25, 26, 27, 28, /* fan1..fan5 */
849 -1, -1, -1, /* unused */
850 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
851 34, -1 /* intrusion0, intrusion1 */
854 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
860 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
865 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
867 if (mode == 0 && pwm == 255)
872 static int pwm_enable_to_reg(enum pwm_enable mode)
883 /* 1 is DC mode, output in ms */
884 static unsigned int step_time_from_reg(u8 reg, u8 mode)
886 return mode ? 400 * reg : 100 * reg;
889 static u8 step_time_to_reg(unsigned int msec, u8 mode)
891 return clamp_val((mode ? (msec + 200) / 400 :
892 (msec + 50) / 100), 1, 255);
895 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
897 if (reg == 0 || reg == 255)
899 return 1350000U / (reg << divreg);
902 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
904 if ((reg & 0xff1f) == 0xff1f)
907 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
912 return 1350000U / reg;
915 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
917 if (reg == 0 || reg == 0xffff)
921 * Even though the registers are 16 bit wide, the fan divisor
924 return 1350000U / (reg << divreg);
927 static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
932 static u16 fan_to_reg(u32 fan, unsigned int divreg)
937 return (1350000U / fan) >> divreg;
940 static inline unsigned int
947 * Some of the voltage inputs have internal scaling, the tables below
948 * contain 8 (the ADC LSB in mV) * scaling factor * 100
950 static const u16 scale_in[15] = {
951 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
955 static inline long in_from_reg(u8 reg, u8 nr)
957 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
960 static inline u8 in_to_reg(u32 val, u8 nr)
962 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
966 * Data structures and manipulation thereof
969 struct nct6775_data {
970 int addr; /* IO base of hw monitor block */
971 int sioreg; /* SIO register address */
975 const struct attribute_group *groups[6];
977 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
978 * 3=temp_crit, 4=temp_lcrit
980 u8 temp_src[NUM_TEMP];
981 u16 reg_temp_config[NUM_TEMP];
982 const char * const *temp_label;
991 const s8 *ALARM_BITS;
995 const u16 *REG_IN_MINMAX[2];
997 const u16 *REG_TARGET;
999 const u16 *REG_FAN_MODE;
1000 const u16 *REG_FAN_MIN;
1001 const u16 *REG_FAN_PULSES;
1002 const u16 *FAN_PULSE_SHIFT;
1003 const u16 *REG_FAN_TIME[3];
1005 const u16 *REG_TOLERANCE_H;
1007 const u8 *REG_PWM_MODE;
1008 const u8 *PWM_MODE_MASK;
1010 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1011 * [3]=pwm_max, [4]=pwm_step,
1012 * [5]=weight_duty_step, [6]=weight_duty_base
1014 const u16 *REG_PWM_READ;
1016 const u16 *REG_CRITICAL_PWM_ENABLE;
1017 u8 CRITICAL_PWM_ENABLE_MASK;
1018 const u16 *REG_CRITICAL_PWM;
1020 const u16 *REG_AUTO_TEMP;
1021 const u16 *REG_AUTO_PWM;
1023 const u16 *REG_CRITICAL_TEMP;
1024 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1026 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1027 const u16 *REG_TEMP_SEL;
1028 const u16 *REG_WEIGHT_TEMP_SEL;
1029 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1031 const u16 *REG_TEMP_OFFSET;
1033 const u16 *REG_ALARM;
1034 const u16 *REG_BEEP;
1036 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1037 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1039 struct mutex update_lock;
1040 bool valid; /* true if following fields are valid */
1041 unsigned long last_updated; /* In jiffies */
1043 /* Register values */
1044 u8 bank; /* current register bank */
1045 u8 in_num; /* number of in inputs we have */
1046 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1047 unsigned int rpm[NUM_FAN];
1048 u16 fan_min[NUM_FAN];
1049 u8 fan_pulses[NUM_FAN];
1050 u8 fan_div[NUM_FAN];
1052 u8 has_fan; /* some fan inputs can be disabled */
1053 u8 has_fan_min; /* some fans don't have min register */
1056 u8 num_temp_alarms; /* 2, 3, or 6 */
1057 u8 num_temp_beeps; /* 2, 3, or 6 */
1058 u8 temp_fixed_num; /* 3 or 6 */
1059 u8 temp_type[NUM_TEMP_FIXED];
1060 s8 temp_offset[NUM_TEMP_FIXED];
1061 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1062 * 3=temp_crit, 4=temp_lcrit */
1066 u8 pwm_num; /* number of pwm */
1067 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1068 * 1->PWM variable duty cycle
1070 enum pwm_enable pwm_enable[NUM_FAN];
1073 * 2->thermal cruise mode (also called SmartFan I)
1074 * 3->fan speed cruise mode
1076 * 5->enhanced variable thermal cruise (SmartFan IV)
1078 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1079 * [3]=pwm_max, [4]=pwm_step,
1080 * [5]=weight_duty_step, [6]=weight_duty_base
1083 u8 target_temp[NUM_FAN];
1084 u8 target_temp_mask;
1085 u32 target_speed[NUM_FAN];
1086 u32 target_speed_tolerance[NUM_FAN];
1087 u8 speed_tolerance_limit;
1089 u8 temp_tolerance[2][NUM_FAN];
1092 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1094 /* Automatic fan speed control registers */
1096 u8 auto_pwm[NUM_FAN][7];
1097 u8 auto_temp[NUM_FAN][7];
1098 u8 pwm_temp_sel[NUM_FAN];
1099 u8 pwm_weight_temp_sel[NUM_FAN];
1100 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1110 u16 have_temp_fixed;
1113 /* Remember extra register values over suspend/resume */
1120 struct nct6775_sio_data {
1125 struct sensor_device_template {
1126 struct device_attribute dev_attr;
1134 bool s2; /* true if both index and nr are used */
1137 struct sensor_device_attr_u {
1139 struct sensor_device_attribute a1;
1140 struct sensor_device_attribute_2 a2;
1145 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1146 .attr = {.name = _template, .mode = _mode }, \
1151 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1152 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1153 .u.index = _index, \
1156 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1158 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1159 .u.s.index = _index, \
1163 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1164 static struct sensor_device_template sensor_dev_template_##_name \
1165 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1168 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1170 static struct sensor_device_template sensor_dev_template_##_name \
1171 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1174 struct sensor_template_group {
1175 struct sensor_device_template **templates;
1176 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1180 static struct attribute_group *
1181 nct6775_create_attr_group(struct device *dev,
1182 const struct sensor_template_group *tg,
1185 struct attribute_group *group;
1186 struct sensor_device_attr_u *su;
1187 struct sensor_device_attribute *a;
1188 struct sensor_device_attribute_2 *a2;
1189 struct attribute **attrs;
1190 struct sensor_device_template **t;
1194 return ERR_PTR(-EINVAL);
1197 for (count = 0; *t; t++, count++)
1201 return ERR_PTR(-EINVAL);
1203 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1205 return ERR_PTR(-ENOMEM);
1207 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1210 return ERR_PTR(-ENOMEM);
1212 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1215 return ERR_PTR(-ENOMEM);
1217 group->attrs = attrs;
1218 group->is_visible = tg->is_visible;
1220 for (i = 0; i < repeat; i++) {
1222 while (*t != NULL) {
1223 snprintf(su->name, sizeof(su->name),
1224 (*t)->dev_attr.attr.name, tg->base + i);
1227 sysfs_attr_init(&a2->dev_attr.attr);
1228 a2->dev_attr.attr.name = su->name;
1229 a2->nr = (*t)->u.s.nr + i;
1230 a2->index = (*t)->u.s.index;
1231 a2->dev_attr.attr.mode =
1232 (*t)->dev_attr.attr.mode;
1233 a2->dev_attr.show = (*t)->dev_attr.show;
1234 a2->dev_attr.store = (*t)->dev_attr.store;
1235 *attrs = &a2->dev_attr.attr;
1238 sysfs_attr_init(&a->dev_attr.attr);
1239 a->dev_attr.attr.name = su->name;
1240 a->index = (*t)->u.index + i;
1241 a->dev_attr.attr.mode =
1242 (*t)->dev_attr.attr.mode;
1243 a->dev_attr.show = (*t)->dev_attr.show;
1244 a->dev_attr.store = (*t)->dev_attr.store;
1245 *attrs = &a->dev_attr.attr;
1256 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1258 switch (data->kind) {
1260 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1261 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1262 reg == 0x111 || reg == 0x121 || reg == 0x131;
1264 return (((reg & 0xff00) == 0x100 ||
1265 (reg & 0xff00) == 0x200) &&
1266 ((reg & 0x00ff) == 0x50 ||
1267 (reg & 0x00ff) == 0x53 ||
1268 (reg & 0x00ff) == 0x55)) ||
1269 (reg & 0xfff0) == 0x630 ||
1270 reg == 0x640 || reg == 0x642 ||
1272 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1273 reg == 0x73 || reg == 0x75 || reg == 0x77;
1275 return (((reg & 0xff00) == 0x100 ||
1276 (reg & 0xff00) == 0x200) &&
1277 ((reg & 0x00ff) == 0x50 ||
1278 (reg & 0x00ff) == 0x53 ||
1279 (reg & 0x00ff) == 0x55)) ||
1280 (reg & 0xfff0) == 0x630 ||
1282 reg == 0x640 || reg == 0x642 ||
1283 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1284 reg == 0x73 || reg == 0x75 || reg == 0x77;
1291 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1292 (reg & 0xfff0) == 0x4c0 ||
1294 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1295 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1297 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1298 reg == 0x7b || reg == 0x7d;
1304 * On older chips, only registers 0x50-0x5f are banked.
1305 * On more recent chips, all registers are banked.
1306 * Assume that is the case and set the bank number for each access.
1307 * Cache the bank number so it only needs to be set if it changes.
1309 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1313 if (data->bank != bank) {
1314 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1315 outb_p(bank, data->addr + DATA_REG_OFFSET);
1320 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1322 int res, word_sized = is_word_sized(data, reg);
1324 nct6775_set_bank(data, reg);
1325 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1326 res = inb_p(data->addr + DATA_REG_OFFSET);
1328 outb_p((reg & 0xff) + 1,
1329 data->addr + ADDR_REG_OFFSET);
1330 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1335 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1337 int word_sized = is_word_sized(data, reg);
1339 nct6775_set_bank(data, reg);
1340 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1342 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1343 outb_p((reg & 0xff) + 1,
1344 data->addr + ADDR_REG_OFFSET);
1346 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1350 /* We left-align 8-bit temperature values to make the code simpler */
1351 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1355 res = nct6775_read_value(data, reg);
1356 if (!is_word_sized(data, reg))
1362 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1364 if (!is_word_sized(data, reg))
1366 return nct6775_write_value(data, reg, value);
1369 /* This function assumes that the caller holds data->update_lock */
1370 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1376 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1377 | (data->fan_div[0] & 0x7);
1378 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1381 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1382 | ((data->fan_div[1] << 4) & 0x70);
1383 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1386 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1387 | (data->fan_div[2] & 0x7);
1388 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1391 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1392 | ((data->fan_div[3] << 4) & 0x70);
1393 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1398 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1400 if (data->kind == nct6775)
1401 nct6775_write_fan_div(data, nr);
1404 static void nct6775_update_fan_div(struct nct6775_data *data)
1408 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1409 data->fan_div[0] = i & 0x7;
1410 data->fan_div[1] = (i & 0x70) >> 4;
1411 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1412 data->fan_div[2] = i & 0x7;
1413 if (data->has_fan & BIT(3))
1414 data->fan_div[3] = (i & 0x70) >> 4;
1417 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1419 if (data->kind == nct6775)
1420 nct6775_update_fan_div(data);
1423 static void nct6775_init_fan_div(struct nct6775_data *data)
1427 nct6775_update_fan_div_common(data);
1429 * For all fans, start with highest divider value if the divider
1430 * register is not initialized. This ensures that we get a
1431 * reading from the fan count register, even if it is not optimal.
1432 * We'll compute a better divider later on.
1434 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1435 if (!(data->has_fan & BIT(i)))
1437 if (data->fan_div[i] == 0) {
1438 data->fan_div[i] = 7;
1439 nct6775_write_fan_div_common(data, i);
1444 static void nct6775_init_fan_common(struct device *dev,
1445 struct nct6775_data *data)
1450 if (data->has_fan_div)
1451 nct6775_init_fan_div(data);
1454 * If fan_min is not set (0), set it to 0xff to disable it. This
1455 * prevents the unnecessary warning when fanX_min is reported as 0.
1457 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1458 if (data->has_fan_min & BIT(i)) {
1459 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1461 nct6775_write_value(data, data->REG_FAN_MIN[i],
1462 data->has_fan_div ? 0xff
1468 static void nct6775_select_fan_div(struct device *dev,
1469 struct nct6775_data *data, int nr, u16 reg)
1471 u8 fan_div = data->fan_div[nr];
1474 if (!data->has_fan_div)
1478 * If we failed to measure the fan speed, or the reported value is not
1479 * in the optimal range, and the clock divider can be modified,
1480 * let's try that for next time.
1482 if (reg == 0x00 && fan_div < 0x07)
1484 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1487 if (fan_div != data->fan_div[nr]) {
1488 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1489 nr + 1, div_from_reg(data->fan_div[nr]),
1490 div_from_reg(fan_div));
1492 /* Preserve min limit if possible */
1493 if (data->has_fan_min & BIT(nr)) {
1494 fan_min = data->fan_min[nr];
1495 if (fan_div > data->fan_div[nr]) {
1496 if (fan_min != 255 && fan_min > 1)
1499 if (fan_min != 255) {
1505 if (fan_min != data->fan_min[nr]) {
1506 data->fan_min[nr] = fan_min;
1507 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1511 data->fan_div[nr] = fan_div;
1512 nct6775_write_fan_div_common(data, nr);
1516 static void nct6775_update_pwm(struct device *dev)
1518 struct nct6775_data *data = dev_get_drvdata(dev);
1520 int fanmodecfg, reg;
1523 for (i = 0; i < data->pwm_num; i++) {
1524 if (!(data->has_pwm & BIT(i)))
1527 duty_is_dc = data->REG_PWM_MODE[i] &&
1528 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1529 & data->PWM_MODE_MASK[i]);
1530 data->pwm_mode[i] = !duty_is_dc;
1532 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1533 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1534 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1536 = nct6775_read_value(data,
1537 data->REG_PWM[j][i]);
1541 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1542 (fanmodecfg >> 4) & 7);
1544 if (!data->temp_tolerance[0][i] ||
1545 data->pwm_enable[i] != speed_cruise)
1546 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1547 if (!data->target_speed_tolerance[i] ||
1548 data->pwm_enable[i] == speed_cruise) {
1549 u8 t = fanmodecfg & 0x0f;
1551 if (data->REG_TOLERANCE_H) {
1552 t |= (nct6775_read_value(data,
1553 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1555 data->target_speed_tolerance[i] = t;
1558 data->temp_tolerance[1][i] =
1559 nct6775_read_value(data,
1560 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1562 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1563 data->pwm_temp_sel[i] = reg & 0x1f;
1564 /* If fan can stop, report floor as 0 */
1566 data->pwm[2][i] = 0;
1568 if (!data->REG_WEIGHT_TEMP_SEL[i])
1571 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1572 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1573 /* If weight is disabled, report weight source as 0 */
1575 data->pwm_weight_temp_sel[i] = 0;
1577 /* Weight temp data */
1578 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1579 data->weight_temp[j][i]
1580 = nct6775_read_value(data,
1581 data->REG_WEIGHT_TEMP[j][i]);
1586 static void nct6775_update_pwm_limits(struct device *dev)
1588 struct nct6775_data *data = dev_get_drvdata(dev);
1593 for (i = 0; i < data->pwm_num; i++) {
1594 if (!(data->has_pwm & BIT(i)))
1597 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1598 data->fan_time[j][i] =
1599 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1602 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1603 /* Update only in matching mode or if never updated */
1604 if (!data->target_temp[i] ||
1605 data->pwm_enable[i] == thermal_cruise)
1606 data->target_temp[i] = reg_t & data->target_temp_mask;
1607 if (!data->target_speed[i] ||
1608 data->pwm_enable[i] == speed_cruise) {
1609 if (data->REG_TOLERANCE_H) {
1610 reg_t |= (nct6775_read_value(data,
1611 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1613 data->target_speed[i] = reg_t;
1616 for (j = 0; j < data->auto_pwm_num; j++) {
1617 data->auto_pwm[i][j] =
1618 nct6775_read_value(data,
1619 NCT6775_AUTO_PWM(data, i, j));
1620 data->auto_temp[i][j] =
1621 nct6775_read_value(data,
1622 NCT6775_AUTO_TEMP(data, i, j));
1625 /* critical auto_pwm temperature data */
1626 data->auto_temp[i][data->auto_pwm_num] =
1627 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1629 switch (data->kind) {
1631 reg = nct6775_read_value(data,
1632 NCT6775_REG_CRITICAL_ENAB[i]);
1633 data->auto_pwm[i][data->auto_pwm_num] =
1634 (reg & 0x02) ? 0xff : 0x00;
1637 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1646 reg = nct6775_read_value(data,
1647 data->REG_CRITICAL_PWM_ENABLE[i]);
1648 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1649 reg = nct6775_read_value(data,
1650 data->REG_CRITICAL_PWM[i]);
1653 data->auto_pwm[i][data->auto_pwm_num] = reg;
1659 static struct nct6775_data *nct6775_update_device(struct device *dev)
1661 struct nct6775_data *data = dev_get_drvdata(dev);
1664 mutex_lock(&data->update_lock);
1666 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1668 /* Fan clock dividers */
1669 nct6775_update_fan_div_common(data);
1671 /* Measured voltages and limits */
1672 for (i = 0; i < data->in_num; i++) {
1673 if (!(data->have_in & BIT(i)))
1676 data->in[i][0] = nct6775_read_value(data,
1678 data->in[i][1] = nct6775_read_value(data,
1679 data->REG_IN_MINMAX[0][i]);
1680 data->in[i][2] = nct6775_read_value(data,
1681 data->REG_IN_MINMAX[1][i]);
1684 /* Measured fan speeds and limits */
1685 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1688 if (!(data->has_fan & BIT(i)))
1691 reg = nct6775_read_value(data, data->REG_FAN[i]);
1692 data->rpm[i] = data->fan_from_reg(reg,
1695 if (data->has_fan_min & BIT(i))
1696 data->fan_min[i] = nct6775_read_value(data,
1697 data->REG_FAN_MIN[i]);
1699 if (data->REG_FAN_PULSES[i]) {
1700 data->fan_pulses[i] =
1701 (nct6775_read_value(data,
1702 data->REG_FAN_PULSES[i])
1703 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1706 nct6775_select_fan_div(dev, data, i, reg);
1709 nct6775_update_pwm(dev);
1710 nct6775_update_pwm_limits(dev);
1712 /* Measured temperatures and limits */
1713 for (i = 0; i < NUM_TEMP; i++) {
1714 if (!(data->have_temp & BIT(i)))
1716 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1717 if (data->reg_temp[j][i])
1719 = nct6775_read_temp(data,
1720 data->reg_temp[j][i]);
1722 if (i >= NUM_TEMP_FIXED ||
1723 !(data->have_temp_fixed & BIT(i)))
1725 data->temp_offset[i]
1726 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1730 for (i = 0; i < NUM_REG_ALARM; i++) {
1733 if (!data->REG_ALARM[i])
1735 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1736 data->alarms |= ((u64)alarm) << (i << 3);
1740 for (i = 0; i < NUM_REG_BEEP; i++) {
1743 if (!data->REG_BEEP[i])
1745 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1746 data->beeps |= ((u64)beep) << (i << 3);
1749 data->last_updated = jiffies;
1753 mutex_unlock(&data->update_lock);
1758 * Sysfs callback functions
1761 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1763 struct nct6775_data *data = nct6775_update_device(dev);
1764 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1765 int index = sattr->index;
1768 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1772 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1775 struct nct6775_data *data = dev_get_drvdata(dev);
1776 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1777 int index = sattr->index;
1782 err = kstrtoul(buf, 10, &val);
1785 mutex_lock(&data->update_lock);
1786 data->in[nr][index] = in_to_reg(val, nr);
1787 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1788 data->in[nr][index]);
1789 mutex_unlock(&data->update_lock);
1794 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1796 struct nct6775_data *data = nct6775_update_device(dev);
1797 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1798 int nr = data->ALARM_BITS[sattr->index];
1800 return sprintf(buf, "%u\n",
1801 (unsigned int)((data->alarms >> nr) & 0x01));
1804 static int find_temp_source(struct nct6775_data *data, int index, int count)
1806 int source = data->temp_src[index];
1809 for (nr = 0; nr < count; nr++) {
1812 src = nct6775_read_value(data,
1813 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1821 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1823 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1824 struct nct6775_data *data = nct6775_update_device(dev);
1825 unsigned int alarm = 0;
1829 * For temperatures, there is no fixed mapping from registers to alarm
1830 * bits. Alarm bits are determined by the temperature source mapping.
1832 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1834 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1836 alarm = (data->alarms >> bit) & 0x01;
1838 return sprintf(buf, "%u\n", alarm);
1842 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1844 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1845 struct nct6775_data *data = nct6775_update_device(dev);
1846 int nr = data->BEEP_BITS[sattr->index];
1848 return sprintf(buf, "%u\n",
1849 (unsigned int)((data->beeps >> nr) & 0x01));
1853 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1856 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1857 struct nct6775_data *data = dev_get_drvdata(dev);
1858 int nr = data->BEEP_BITS[sattr->index];
1859 int regindex = nr >> 3;
1863 err = kstrtoul(buf, 10, &val);
1869 mutex_lock(&data->update_lock);
1871 data->beeps |= (1ULL << nr);
1873 data->beeps &= ~(1ULL << nr);
1874 nct6775_write_value(data, data->REG_BEEP[regindex],
1875 (data->beeps >> (regindex << 3)) & 0xff);
1876 mutex_unlock(&data->update_lock);
1881 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1883 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1884 struct nct6775_data *data = nct6775_update_device(dev);
1885 unsigned int beep = 0;
1889 * For temperatures, there is no fixed mapping from registers to beep
1890 * enable bits. Beep enable bits are determined by the temperature
1893 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1895 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1897 beep = (data->beeps >> bit) & 0x01;
1899 return sprintf(buf, "%u\n", beep);
1903 store_temp_beep(struct device *dev, struct device_attribute *attr,
1904 const char *buf, size_t count)
1906 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1907 struct nct6775_data *data = dev_get_drvdata(dev);
1908 int nr, bit, regindex;
1912 err = kstrtoul(buf, 10, &val);
1918 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1922 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1923 regindex = bit >> 3;
1925 mutex_lock(&data->update_lock);
1927 data->beeps |= (1ULL << bit);
1929 data->beeps &= ~(1ULL << bit);
1930 nct6775_write_value(data, data->REG_BEEP[regindex],
1931 (data->beeps >> (regindex << 3)) & 0xff);
1932 mutex_unlock(&data->update_lock);
1937 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1938 struct attribute *attr, int index)
1940 struct device *dev = container_of(kobj, struct device, kobj);
1941 struct nct6775_data *data = dev_get_drvdata(dev);
1942 int in = index / 5; /* voltage index */
1944 if (!(data->have_in & BIT(in)))
1950 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1951 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1952 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1954 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1955 store_in_reg, 0, 1);
1956 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1957 store_in_reg, 0, 2);
1960 * nct6775_in_is_visible uses the index into the following array
1961 * to determine if attributes should be created or not.
1962 * Any change in order or content must be matched.
1964 static struct sensor_device_template *nct6775_attributes_in_template[] = {
1965 &sensor_dev_template_in_input,
1966 &sensor_dev_template_in_alarm,
1967 &sensor_dev_template_in_beep,
1968 &sensor_dev_template_in_min,
1969 &sensor_dev_template_in_max,
1973 static const struct sensor_template_group nct6775_in_template_group = {
1974 .templates = nct6775_attributes_in_template,
1975 .is_visible = nct6775_in_is_visible,
1979 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1981 struct nct6775_data *data = nct6775_update_device(dev);
1982 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1983 int nr = sattr->index;
1985 return sprintf(buf, "%d\n", data->rpm[nr]);
1989 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1991 struct nct6775_data *data = nct6775_update_device(dev);
1992 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1993 int nr = sattr->index;
1995 return sprintf(buf, "%d\n",
1996 data->fan_from_reg_min(data->fan_min[nr],
1997 data->fan_div[nr]));
2001 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2003 struct nct6775_data *data = nct6775_update_device(dev);
2004 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2005 int nr = sattr->index;
2007 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2011 store_fan_min(struct device *dev, struct device_attribute *attr,
2012 const char *buf, size_t count)
2014 struct nct6775_data *data = dev_get_drvdata(dev);
2015 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2016 int nr = sattr->index;
2022 err = kstrtoul(buf, 10, &val);
2026 mutex_lock(&data->update_lock);
2027 if (!data->has_fan_div) {
2028 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2034 val = 1350000U / val;
2035 val = (val & 0x1f) | ((val << 3) & 0xff00);
2037 data->fan_min[nr] = val;
2038 goto write_min; /* Leave fan divider alone */
2041 /* No min limit, alarm disabled */
2042 data->fan_min[nr] = 255;
2043 new_div = data->fan_div[nr]; /* No change */
2044 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2047 reg = 1350000U / val;
2048 if (reg >= 128 * 255) {
2050 * Speed below this value cannot possibly be represented,
2051 * even with the highest divider (128)
2053 data->fan_min[nr] = 254;
2054 new_div = 7; /* 128 == BIT(7) */
2056 "fan%u low limit %lu below minimum %u, set to minimum\n",
2057 nr + 1, val, data->fan_from_reg_min(254, 7));
2060 * Speed above this value cannot possibly be represented,
2061 * even with the lowest divider (1)
2063 data->fan_min[nr] = 1;
2064 new_div = 0; /* 1 == BIT(0) */
2066 "fan%u low limit %lu above maximum %u, set to maximum\n",
2067 nr + 1, val, data->fan_from_reg_min(1, 0));
2070 * Automatically pick the best divider, i.e. the one such
2071 * that the min limit will correspond to a register value
2072 * in the 96..192 range
2075 while (reg > 192 && new_div < 7) {
2079 data->fan_min[nr] = reg;
2084 * Write both the fan clock divider (if it changed) and the new
2085 * fan min (unconditionally)
2087 if (new_div != data->fan_div[nr]) {
2088 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2089 nr + 1, div_from_reg(data->fan_div[nr]),
2090 div_from_reg(new_div));
2091 data->fan_div[nr] = new_div;
2092 nct6775_write_fan_div_common(data, nr);
2093 /* Give the chip time to sample a new speed value */
2094 data->last_updated = jiffies;
2098 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2099 mutex_unlock(&data->update_lock);
2105 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2107 struct nct6775_data *data = nct6775_update_device(dev);
2108 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2109 int p = data->fan_pulses[sattr->index];
2111 return sprintf(buf, "%d\n", p ? : 4);
2115 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2116 const char *buf, size_t count)
2118 struct nct6775_data *data = dev_get_drvdata(dev);
2119 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2120 int nr = sattr->index;
2125 err = kstrtoul(buf, 10, &val);
2132 mutex_lock(&data->update_lock);
2133 data->fan_pulses[nr] = val & 3;
2134 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2135 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2136 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2137 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2138 mutex_unlock(&data->update_lock);
2143 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2144 struct attribute *attr, int index)
2146 struct device *dev = container_of(kobj, struct device, kobj);
2147 struct nct6775_data *data = dev_get_drvdata(dev);
2148 int fan = index / 6; /* fan index */
2149 int nr = index % 6; /* attribute index */
2151 if (!(data->has_fan & BIT(fan)))
2154 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2156 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2158 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2160 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2162 if (nr == 5 && data->kind != nct6775)
2168 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2169 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2171 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2172 store_beep, FAN_ALARM_BASE);
2173 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2174 store_fan_pulses, 0);
2175 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2177 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2180 * nct6775_fan_is_visible uses the index into the following array
2181 * to determine if attributes should be created or not.
2182 * Any change in order or content must be matched.
2184 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2185 &sensor_dev_template_fan_input,
2186 &sensor_dev_template_fan_alarm, /* 1 */
2187 &sensor_dev_template_fan_beep, /* 2 */
2188 &sensor_dev_template_fan_pulses,
2189 &sensor_dev_template_fan_min, /* 4 */
2190 &sensor_dev_template_fan_div, /* 5 */
2194 static const struct sensor_template_group nct6775_fan_template_group = {
2195 .templates = nct6775_attributes_fan_template,
2196 .is_visible = nct6775_fan_is_visible,
2201 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2203 struct nct6775_data *data = nct6775_update_device(dev);
2204 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2205 int nr = sattr->index;
2207 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2211 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2213 struct nct6775_data *data = nct6775_update_device(dev);
2214 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2216 int index = sattr->index;
2218 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2222 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2225 struct nct6775_data *data = dev_get_drvdata(dev);
2226 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2228 int index = sattr->index;
2232 err = kstrtol(buf, 10, &val);
2236 mutex_lock(&data->update_lock);
2237 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2238 nct6775_write_temp(data, data->reg_temp[index][nr],
2239 data->temp[index][nr]);
2240 mutex_unlock(&data->update_lock);
2245 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2247 struct nct6775_data *data = nct6775_update_device(dev);
2248 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2250 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2254 store_temp_offset(struct device *dev, struct device_attribute *attr,
2255 const char *buf, size_t count)
2257 struct nct6775_data *data = dev_get_drvdata(dev);
2258 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2259 int nr = sattr->index;
2263 err = kstrtol(buf, 10, &val);
2267 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2269 mutex_lock(&data->update_lock);
2270 data->temp_offset[nr] = val;
2271 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2272 mutex_unlock(&data->update_lock);
2278 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2280 struct nct6775_data *data = nct6775_update_device(dev);
2281 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2282 int nr = sattr->index;
2284 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2288 store_temp_type(struct device *dev, struct device_attribute *attr,
2289 const char *buf, size_t count)
2291 struct nct6775_data *data = nct6775_update_device(dev);
2292 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2293 int nr = sattr->index;
2296 u8 vbat, diode, vbit, dbit;
2298 err = kstrtoul(buf, 10, &val);
2302 if (val != 1 && val != 3 && val != 4)
2305 mutex_lock(&data->update_lock);
2307 data->temp_type[nr] = val;
2309 dbit = data->DIODE_MASK << nr;
2310 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2311 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2313 case 1: /* CPU diode (diode, current mode) */
2317 case 3: /* diode, voltage mode */
2320 case 4: /* thermistor */
2323 nct6775_write_value(data, data->REG_VBAT, vbat);
2324 nct6775_write_value(data, data->REG_DIODE, diode);
2326 mutex_unlock(&data->update_lock);
2330 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2331 struct attribute *attr, int index)
2333 struct device *dev = container_of(kobj, struct device, kobj);
2334 struct nct6775_data *data = dev_get_drvdata(dev);
2335 int temp = index / 10; /* temp index */
2336 int nr = index % 10; /* attribute index */
2338 if (!(data->have_temp & BIT(temp)))
2341 if (nr == 1 && !data->temp_label)
2344 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2345 return 0; /* alarm */
2347 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2348 return 0; /* beep */
2350 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2353 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2356 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2359 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2362 /* offset and type only apply to fixed sensors */
2363 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2369 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2370 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2371 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2373 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2374 show_temp, store_temp, 0, 2);
2375 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2377 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2379 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2380 show_temp_offset, store_temp_offset, 0);
2381 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2382 store_temp_type, 0);
2383 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2384 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2385 store_temp_beep, 0);
2388 * nct6775_temp_is_visible uses the index into the following array
2389 * to determine if attributes should be created or not.
2390 * Any change in order or content must be matched.
2392 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2393 &sensor_dev_template_temp_input,
2394 &sensor_dev_template_temp_label,
2395 &sensor_dev_template_temp_alarm, /* 2 */
2396 &sensor_dev_template_temp_beep, /* 3 */
2397 &sensor_dev_template_temp_max, /* 4 */
2398 &sensor_dev_template_temp_max_hyst, /* 5 */
2399 &sensor_dev_template_temp_crit, /* 6 */
2400 &sensor_dev_template_temp_lcrit, /* 7 */
2401 &sensor_dev_template_temp_offset, /* 8 */
2402 &sensor_dev_template_temp_type, /* 9 */
2406 static const struct sensor_template_group nct6775_temp_template_group = {
2407 .templates = nct6775_attributes_temp_template,
2408 .is_visible = nct6775_temp_is_visible,
2413 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2415 struct nct6775_data *data = nct6775_update_device(dev);
2416 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2418 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2422 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2423 const char *buf, size_t count)
2425 struct nct6775_data *data = dev_get_drvdata(dev);
2426 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2427 int nr = sattr->index;
2432 err = kstrtoul(buf, 10, &val);
2439 /* Setting DC mode (0) is not supported for all chips/channels */
2440 if (data->REG_PWM_MODE[nr] == 0) {
2446 mutex_lock(&data->update_lock);
2447 data->pwm_mode[nr] = val;
2448 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2449 reg &= ~data->PWM_MODE_MASK[nr];
2451 reg |= data->PWM_MODE_MASK[nr];
2452 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2453 mutex_unlock(&data->update_lock);
2458 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2460 struct nct6775_data *data = nct6775_update_device(dev);
2461 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2463 int index = sattr->index;
2467 * For automatic fan control modes, show current pwm readings.
2468 * Otherwise, show the configured value.
2470 if (index == 0 && data->pwm_enable[nr] > manual)
2471 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2473 pwm = data->pwm[index][nr];
2475 return sprintf(buf, "%d\n", pwm);
2479 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2482 struct nct6775_data *data = dev_get_drvdata(dev);
2483 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2485 int index = sattr->index;
2487 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2489 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2493 err = kstrtoul(buf, 10, &val);
2496 val = clamp_val(val, minval[index], maxval[index]);
2498 mutex_lock(&data->update_lock);
2499 data->pwm[index][nr] = val;
2500 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2501 if (index == 2) { /* floor: disable if val == 0 */
2502 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2506 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2508 mutex_unlock(&data->update_lock);
2512 /* Returns 0 if OK, -EINVAL otherwise */
2513 static int check_trip_points(struct nct6775_data *data, int nr)
2517 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2518 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2521 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2522 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2525 /* validate critical temperature and pwm if enabled (pwm > 0) */
2526 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2527 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2528 data->auto_temp[nr][data->auto_pwm_num] ||
2529 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2530 data->auto_pwm[nr][data->auto_pwm_num])
2536 static void pwm_update_registers(struct nct6775_data *data, int nr)
2540 switch (data->pwm_enable[nr]) {
2545 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2546 reg = (reg & ~data->tolerance_mask) |
2547 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2548 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2549 nct6775_write_value(data, data->REG_TARGET[nr],
2550 data->target_speed[nr] & 0xff);
2551 if (data->REG_TOLERANCE_H) {
2552 reg = (data->target_speed[nr] >> 8) & 0x0f;
2553 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2554 nct6775_write_value(data,
2555 data->REG_TOLERANCE_H[nr],
2559 case thermal_cruise:
2560 nct6775_write_value(data, data->REG_TARGET[nr],
2561 data->target_temp[nr]);
2564 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2565 reg = (reg & ~data->tolerance_mask) |
2566 data->temp_tolerance[0][nr];
2567 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2573 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2575 struct nct6775_data *data = nct6775_update_device(dev);
2576 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2578 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2582 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2583 const char *buf, size_t count)
2585 struct nct6775_data *data = dev_get_drvdata(dev);
2586 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2587 int nr = sattr->index;
2592 err = kstrtoul(buf, 10, &val);
2599 if (val == sf3 && data->kind != nct6775)
2602 if (val == sf4 && check_trip_points(data, nr)) {
2603 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2604 dev_err(dev, "Adjust trip points and try again\n");
2608 mutex_lock(&data->update_lock);
2609 data->pwm_enable[nr] = val;
2612 * turn off pwm control: select manual mode, set pwm to maximum
2614 data->pwm[0][nr] = 255;
2615 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2617 pwm_update_registers(data, nr);
2618 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2620 reg |= pwm_enable_to_reg(val) << 4;
2621 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2622 mutex_unlock(&data->update_lock);
2627 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2631 for (i = 0; i < NUM_TEMP; i++) {
2632 if (!(data->have_temp & BIT(i)))
2634 if (src == data->temp_src[i]) {
2640 return sprintf(buf, "%d\n", sel);
2644 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2646 struct nct6775_data *data = nct6775_update_device(dev);
2647 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2648 int index = sattr->index;
2650 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2654 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2655 const char *buf, size_t count)
2657 struct nct6775_data *data = nct6775_update_device(dev);
2658 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2659 int nr = sattr->index;
2663 err = kstrtoul(buf, 10, &val);
2666 if (val == 0 || val > NUM_TEMP)
2668 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2671 mutex_lock(&data->update_lock);
2672 src = data->temp_src[val - 1];
2673 data->pwm_temp_sel[nr] = src;
2674 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2677 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2678 mutex_unlock(&data->update_lock);
2684 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2687 struct nct6775_data *data = nct6775_update_device(dev);
2688 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2689 int index = sattr->index;
2691 return show_pwm_temp_sel_common(data, buf,
2692 data->pwm_weight_temp_sel[index]);
2696 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2697 const char *buf, size_t count)
2699 struct nct6775_data *data = nct6775_update_device(dev);
2700 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2701 int nr = sattr->index;
2705 err = kstrtoul(buf, 10, &val);
2710 val = array_index_nospec(val, NUM_TEMP + 1);
2711 if (val && (!(data->have_temp & BIT(val - 1)) ||
2712 !data->temp_src[val - 1]))
2715 mutex_lock(&data->update_lock);
2717 src = data->temp_src[val - 1];
2718 data->pwm_weight_temp_sel[nr] = src;
2719 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2721 reg |= (src | 0x80);
2722 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2724 data->pwm_weight_temp_sel[nr] = 0;
2725 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2727 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2729 mutex_unlock(&data->update_lock);
2735 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2737 struct nct6775_data *data = nct6775_update_device(dev);
2738 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2740 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2744 store_target_temp(struct device *dev, struct device_attribute *attr,
2745 const char *buf, size_t count)
2747 struct nct6775_data *data = dev_get_drvdata(dev);
2748 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2749 int nr = sattr->index;
2753 err = kstrtoul(buf, 10, &val);
2757 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2758 data->target_temp_mask);
2760 mutex_lock(&data->update_lock);
2761 data->target_temp[nr] = val;
2762 pwm_update_registers(data, nr);
2763 mutex_unlock(&data->update_lock);
2768 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2770 struct nct6775_data *data = nct6775_update_device(dev);
2771 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2772 int nr = sattr->index;
2774 return sprintf(buf, "%d\n",
2775 fan_from_reg16(data->target_speed[nr],
2776 data->fan_div[nr]));
2780 store_target_speed(struct device *dev, struct device_attribute *attr,
2781 const char *buf, size_t count)
2783 struct nct6775_data *data = dev_get_drvdata(dev);
2784 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2785 int nr = sattr->index;
2790 err = kstrtoul(buf, 10, &val);
2794 val = clamp_val(val, 0, 1350000U);
2795 speed = fan_to_reg(val, data->fan_div[nr]);
2797 mutex_lock(&data->update_lock);
2798 data->target_speed[nr] = speed;
2799 pwm_update_registers(data, nr);
2800 mutex_unlock(&data->update_lock);
2805 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2808 struct nct6775_data *data = nct6775_update_device(dev);
2809 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2811 int index = sattr->index;
2813 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2817 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2818 const char *buf, size_t count)
2820 struct nct6775_data *data = dev_get_drvdata(dev);
2821 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2823 int index = sattr->index;
2827 err = kstrtoul(buf, 10, &val);
2831 /* Limit tolerance as needed */
2832 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2834 mutex_lock(&data->update_lock);
2835 data->temp_tolerance[index][nr] = val;
2837 pwm_update_registers(data, nr);
2839 nct6775_write_value(data,
2840 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2842 mutex_unlock(&data->update_lock);
2847 * Fan speed tolerance is a tricky beast, since the associated register is
2848 * a tick counter, but the value is reported and configured as rpm.
2849 * Compute resulting low and high rpm values and report the difference.
2850 * A fan speed tolerance only makes sense if a fan target speed has been
2851 * configured, so only display values other than 0 if that is the case.
2854 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2857 struct nct6775_data *data = nct6775_update_device(dev);
2858 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2859 int nr = sattr->index;
2860 int target = data->target_speed[nr];
2864 int low = target - data->target_speed_tolerance[nr];
2865 int high = target + data->target_speed_tolerance[nr];
2874 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2875 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2878 return sprintf(buf, "%d\n", tolerance);
2882 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2883 const char *buf, size_t count)
2885 struct nct6775_data *data = dev_get_drvdata(dev);
2886 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2887 int nr = sattr->index;
2892 err = kstrtoul(buf, 10, &val);
2896 high = fan_from_reg16(data->target_speed[nr],
2897 data->fan_div[nr]) + val;
2898 low = fan_from_reg16(data->target_speed[nr],
2899 data->fan_div[nr]) - val;
2905 val = (fan_to_reg(low, data->fan_div[nr]) -
2906 fan_to_reg(high, data->fan_div[nr])) / 2;
2908 /* Limit tolerance as needed */
2909 val = clamp_val(val, 0, data->speed_tolerance_limit);
2911 mutex_lock(&data->update_lock);
2912 data->target_speed_tolerance[nr] = val;
2913 pwm_update_registers(data, nr);
2914 mutex_unlock(&data->update_lock);
2918 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2919 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2921 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2922 store_pwm_enable, 0);
2923 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2924 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2925 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2926 show_target_temp, store_target_temp, 0);
2927 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2928 show_target_speed, store_target_speed, 0);
2929 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2930 show_speed_tolerance, store_speed_tolerance, 0);
2932 /* Smart Fan registers */
2935 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2937 struct nct6775_data *data = nct6775_update_device(dev);
2938 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2940 int index = sattr->index;
2942 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2946 store_weight_temp(struct device *dev, struct device_attribute *attr,
2947 const char *buf, size_t count)
2949 struct nct6775_data *data = dev_get_drvdata(dev);
2950 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2952 int index = sattr->index;
2956 err = kstrtoul(buf, 10, &val);
2960 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2962 mutex_lock(&data->update_lock);
2963 data->weight_temp[index][nr] = val;
2964 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2965 mutex_unlock(&data->update_lock);
2969 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2970 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2971 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2972 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2973 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2974 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2975 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2976 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2977 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2978 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2979 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2980 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2983 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2985 struct nct6775_data *data = nct6775_update_device(dev);
2986 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2988 int index = sattr->index;
2990 return sprintf(buf, "%d\n",
2991 step_time_from_reg(data->fan_time[index][nr],
2992 data->pwm_mode[nr]));
2996 store_fan_time(struct device *dev, struct device_attribute *attr,
2997 const char *buf, size_t count)
2999 struct nct6775_data *data = dev_get_drvdata(dev);
3000 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3002 int index = sattr->index;
3006 err = kstrtoul(buf, 10, &val);
3010 val = step_time_to_reg(val, data->pwm_mode[nr]);
3011 mutex_lock(&data->update_lock);
3012 data->fan_time[index][nr] = val;
3013 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3014 mutex_unlock(&data->update_lock);
3019 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3021 struct nct6775_data *data = nct6775_update_device(dev);
3022 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3024 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3028 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3029 const char *buf, size_t count)
3031 struct nct6775_data *data = dev_get_drvdata(dev);
3032 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3034 int point = sattr->index;
3039 err = kstrtoul(buf, 10, &val);
3045 if (point == data->auto_pwm_num) {
3046 if (data->kind != nct6775 && !val)
3048 if (data->kind != nct6779 && val)
3052 mutex_lock(&data->update_lock);
3053 data->auto_pwm[nr][point] = val;
3054 if (point < data->auto_pwm_num) {
3055 nct6775_write_value(data,
3056 NCT6775_AUTO_PWM(data, nr, point),
3057 data->auto_pwm[nr][point]);
3059 switch (data->kind) {
3061 /* disable if needed (pwm == 0) */
3062 reg = nct6775_read_value(data,
3063 NCT6775_REG_CRITICAL_ENAB[nr]);
3068 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3072 break; /* always enabled, nothing to do */
3080 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3082 reg = nct6775_read_value(data,
3083 data->REG_CRITICAL_PWM_ENABLE[nr]);
3085 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3087 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3088 nct6775_write_value(data,
3089 data->REG_CRITICAL_PWM_ENABLE[nr],
3094 mutex_unlock(&data->update_lock);
3099 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3101 struct nct6775_data *data = nct6775_update_device(dev);
3102 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3104 int point = sattr->index;
3107 * We don't know for sure if the temperature is signed or unsigned.
3108 * Assume it is unsigned.
3110 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3114 store_auto_temp(struct device *dev, struct device_attribute *attr,
3115 const char *buf, size_t count)
3117 struct nct6775_data *data = dev_get_drvdata(dev);
3118 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3120 int point = sattr->index;
3124 err = kstrtoul(buf, 10, &val);
3130 mutex_lock(&data->update_lock);
3131 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3132 if (point < data->auto_pwm_num) {
3133 nct6775_write_value(data,
3134 NCT6775_AUTO_TEMP(data, nr, point),
3135 data->auto_temp[nr][point]);
3137 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3138 data->auto_temp[nr][point]);
3140 mutex_unlock(&data->update_lock);
3144 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3145 struct attribute *attr, int index)
3147 struct device *dev = container_of(kobj, struct device, kobj);
3148 struct nct6775_data *data = dev_get_drvdata(dev);
3149 int pwm = index / 36; /* pwm index */
3150 int nr = index % 36; /* attribute index */
3152 if (!(data->has_pwm & BIT(pwm)))
3155 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3156 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3158 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3160 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3162 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3165 if (nr >= 22 && nr <= 35) { /* auto point */
3166 int api = (nr - 22) / 2; /* auto point index */
3168 if (api > data->auto_pwm_num)
3174 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3175 show_fan_time, store_fan_time, 0, 0);
3176 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3177 show_fan_time, store_fan_time, 0, 1);
3178 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3179 show_fan_time, store_fan_time, 0, 2);
3180 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3182 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3184 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3185 show_temp_tolerance, store_temp_tolerance, 0, 0);
3186 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3187 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3190 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3193 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3196 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3197 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3198 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3199 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3201 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3202 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3203 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3204 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3206 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3207 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3208 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3209 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3211 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3212 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3213 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3214 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3216 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3217 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3218 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3219 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3221 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3222 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3223 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3224 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3226 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3227 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3228 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3229 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3232 * nct6775_pwm_is_visible uses the index into the following array
3233 * to determine if attributes should be created or not.
3234 * Any change in order or content must be matched.
3236 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3237 &sensor_dev_template_pwm,
3238 &sensor_dev_template_pwm_mode,
3239 &sensor_dev_template_pwm_enable,
3240 &sensor_dev_template_pwm_temp_sel,
3241 &sensor_dev_template_pwm_temp_tolerance,
3242 &sensor_dev_template_pwm_crit_temp_tolerance,
3243 &sensor_dev_template_pwm_target_temp,
3244 &sensor_dev_template_fan_target,
3245 &sensor_dev_template_fan_tolerance,
3246 &sensor_dev_template_pwm_stop_time,
3247 &sensor_dev_template_pwm_step_up_time,
3248 &sensor_dev_template_pwm_step_down_time,
3249 &sensor_dev_template_pwm_start,
3250 &sensor_dev_template_pwm_floor,
3251 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3252 &sensor_dev_template_pwm_weight_temp_step,
3253 &sensor_dev_template_pwm_weight_temp_step_tol,
3254 &sensor_dev_template_pwm_weight_temp_step_base,
3255 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3256 &sensor_dev_template_pwm_max, /* 19 */
3257 &sensor_dev_template_pwm_step, /* 20 */
3258 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3259 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3260 &sensor_dev_template_pwm_auto_point1_temp,
3261 &sensor_dev_template_pwm_auto_point2_pwm,
3262 &sensor_dev_template_pwm_auto_point2_temp,
3263 &sensor_dev_template_pwm_auto_point3_pwm,
3264 &sensor_dev_template_pwm_auto_point3_temp,
3265 &sensor_dev_template_pwm_auto_point4_pwm,
3266 &sensor_dev_template_pwm_auto_point4_temp,
3267 &sensor_dev_template_pwm_auto_point5_pwm,
3268 &sensor_dev_template_pwm_auto_point5_temp,
3269 &sensor_dev_template_pwm_auto_point6_pwm,
3270 &sensor_dev_template_pwm_auto_point6_temp,
3271 &sensor_dev_template_pwm_auto_point7_pwm,
3272 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3277 static const struct sensor_template_group nct6775_pwm_template_group = {
3278 .templates = nct6775_attributes_pwm_template,
3279 .is_visible = nct6775_pwm_is_visible,
3284 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3286 struct nct6775_data *data = dev_get_drvdata(dev);
3288 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3291 static DEVICE_ATTR_RO(cpu0_vid);
3293 /* Case open detection */
3296 clear_caseopen(struct device *dev, struct device_attribute *attr,
3297 const char *buf, size_t count)
3299 struct nct6775_data *data = dev_get_drvdata(dev);
3300 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3305 if (kstrtoul(buf, 10, &val) || val != 0)
3308 mutex_lock(&data->update_lock);
3311 * Use CR registers to clear caseopen status.
3312 * The CR registers are the same for all chips, and not all chips
3313 * support clearing the caseopen status through "regular" registers.
3315 ret = superio_enter(data->sioreg);
3321 superio_select(data->sioreg, NCT6775_LD_ACPI);
3322 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3323 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3324 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3325 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3326 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3327 superio_exit(data->sioreg);
3329 data->valid = false; /* Force cache refresh */
3331 mutex_unlock(&data->update_lock);
3335 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3336 clear_caseopen, INTRUSION_ALARM_BASE);
3337 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3338 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3339 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3340 store_beep, INTRUSION_ALARM_BASE);
3341 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3342 store_beep, INTRUSION_ALARM_BASE + 1);
3343 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3344 store_beep, BEEP_ENABLE_BASE);
3346 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3347 struct attribute *attr, int index)
3349 struct device *dev = container_of(kobj, struct device, kobj);
3350 struct nct6775_data *data = dev_get_drvdata(dev);
3352 if (index == 0 && !data->have_vid)
3355 if (index == 1 || index == 2) {
3356 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3360 if (index == 3 || index == 4) {
3361 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3369 * nct6775_other_is_visible uses the index into the following array
3370 * to determine if attributes should be created or not.
3371 * Any change in order or content must be matched.
3373 static struct attribute *nct6775_attributes_other[] = {
3374 &dev_attr_cpu0_vid.attr, /* 0 */
3375 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3376 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3377 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3378 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3379 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3384 static const struct attribute_group nct6775_group_other = {
3385 .attrs = nct6775_attributes_other,
3386 .is_visible = nct6775_other_is_visible,
3389 static inline void nct6775_init_device(struct nct6775_data *data)
3394 /* Start monitoring if needed */
3395 if (data->REG_CONFIG) {
3396 tmp = nct6775_read_value(data, data->REG_CONFIG);
3398 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3401 /* Enable temperature sensors if needed */
3402 for (i = 0; i < NUM_TEMP; i++) {
3403 if (!(data->have_temp & BIT(i)))
3405 if (!data->reg_temp_config[i])
3407 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3409 nct6775_write_value(data, data->reg_temp_config[i],
3413 /* Enable VBAT monitoring if needed */
3414 tmp = nct6775_read_value(data, data->REG_VBAT);
3416 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3418 diode = nct6775_read_value(data, data->REG_DIODE);
3420 for (i = 0; i < data->temp_fixed_num; i++) {
3421 if (!(data->have_temp_fixed & BIT(i)))
3423 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3425 = 3 - ((diode >> i) & data->DIODE_MASK);
3426 else /* thermistor */
3427 data->temp_type[i] = 4;
3432 nct6775_check_fan_inputs(struct nct6775_data *data)
3434 bool fan3pin = false, fan4pin = false, fan4min = false;
3435 bool fan5pin = false, fan6pin = false, fan7pin = false;
3436 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3437 bool pwm6pin = false, pwm7pin = false;
3438 int sioreg = data->sioreg;
3442 /* Store SIO_REG_ENABLE for use during resume */
3443 superio_select(sioreg, NCT6775_LD_HWM);
3444 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3446 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3447 if (data->kind == nct6775) {
3448 cr2c = superio_inb(sioreg, 0x2c);
3450 fan3pin = cr2c & BIT(6);
3451 pwm3pin = cr2c & BIT(7);
3453 /* On NCT6775, fan4 shares pins with the fdc interface */
3454 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3455 } else if (data->kind == nct6776) {
3456 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3457 const char *board_vendor, *board_name;
3459 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3460 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3462 if (board_name && board_vendor &&
3463 !strcmp(board_vendor, "ASRock")) {
3465 * Auxiliary fan monitoring is not enabled on ASRock
3466 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3467 * Observed with BIOS version 2.00.
3469 if (!strcmp(board_name, "Z77 Pro4-M")) {
3470 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3471 data->sio_reg_enable |= 0xe0;
3472 superio_outb(sioreg, SIO_REG_ENABLE,
3473 data->sio_reg_enable);
3478 if (data->sio_reg_enable & 0x80)
3481 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3483 if (data->sio_reg_enable & 0x40)
3486 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3488 if (data->sio_reg_enable & 0x20)
3491 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3495 } else if (data->kind == nct6106) {
3496 cr24 = superio_inb(sioreg, 0x24);
3497 fan3pin = !(cr24 & 0x80);
3498 pwm3pin = cr24 & 0x08;
3500 /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
3501 int cr1b, cr2a, cr2f;
3506 cr1c = superio_inb(sioreg, 0x1c);
3508 fan3pin = !(cr1c & BIT(5));
3509 fan4pin = !(cr1c & BIT(6));
3510 fan5pin = !(cr1c & BIT(7));
3512 pwm3pin = !(cr1c & BIT(0));
3513 pwm4pin = !(cr1c & BIT(1));
3514 pwm5pin = !(cr1c & BIT(2));
3516 cr2d = superio_inb(sioreg, 0x2d);
3517 switch (data->kind) {
3520 fan6pin = cr2d & BIT(1);
3521 pwm6pin = cr2d & BIT(0);
3526 cr1b = superio_inb(sioreg, 0x1b);
3527 cr2a = superio_inb(sioreg, 0x2a);
3528 cr2f = superio_inb(sioreg, 0x2f);
3529 dsw_en = cr2f & BIT(3);
3532 pwm5pin = cr2d & BIT(7);
3535 fan5pin = cr1b & BIT(5);
3537 superio_select(sioreg, NCT6775_LD_12);
3538 if (data->kind != nct6796) {
3539 int creb = superio_inb(sioreg, 0xeb);
3542 fan6pin = cr2d & BIT(1);
3543 pwm6pin = cr2d & BIT(0);
3547 fan5pin = creb & BIT(5);
3549 pwm5pin = (creb & BIT(4)) &&
3552 fan6pin = creb & BIT(3);
3554 pwm6pin = creb & BIT(2);
3557 if (data->kind == nct6795 || data->kind == nct6796) {
3558 int cred = superio_inb(sioreg, 0xed);
3561 fan6pin = (cr2a & BIT(4)) &&
3562 (!dsw_en || (cred & BIT(4)));
3564 pwm6pin = (cr2a & BIT(3)) &&
3568 if (data->kind == nct6796) {
3569 int cr1d = superio_inb(sioreg, 0x1d);
3570 int cr2b = superio_inb(sioreg, 0x2b);
3572 fan7pin = !(cr2b & BIT(2));
3573 pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3577 default: /* NCT6779D */
3584 /* fan 1 and 2 (0x03) are always present */
3585 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3586 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3587 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3588 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3589 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3590 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3593 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3594 int *available, int *mask)
3599 for (i = 0; i < data->pwm_num && *available; i++) {
3604 src = nct6775_read_value(data, regp[i]);
3606 if (!src || (*mask & BIT(src)))
3608 if (!(data->temp_mask & BIT(src)))
3611 index = __ffs(*available);
3612 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3613 *available &= ~BIT(index);
3618 static int nct6775_probe(struct platform_device *pdev)
3620 struct device *dev = &pdev->dev;
3621 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3622 struct nct6775_data *data;
3623 struct resource *res;
3625 int src, mask, available;
3626 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3627 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3628 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3629 int num_reg_temp, num_reg_temp_mon;
3631 struct attribute_group *group;
3632 struct device *hwmon_dev;
3633 int num_attr_groups = 0;
3635 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3636 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3640 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3645 data->kind = sio_data->kind;
3646 data->sioreg = sio_data->sioreg;
3647 data->addr = res->start;
3648 mutex_init(&data->update_lock);
3649 data->name = nct6775_device_names[data->kind];
3650 data->bank = 0xff; /* Force initial bank selection */
3651 platform_set_drvdata(pdev, data);
3653 switch (data->kind) {
3657 data->auto_pwm_num = 4;
3658 data->temp_fixed_num = 3;
3659 data->num_temp_alarms = 6;
3660 data->num_temp_beeps = 6;
3662 data->fan_from_reg = fan_from_reg13;
3663 data->fan_from_reg_min = fan_from_reg13;
3665 data->temp_label = nct6776_temp_label;
3666 data->temp_mask = NCT6776_TEMP_MASK;
3667 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3669 data->REG_VBAT = NCT6106_REG_VBAT;
3670 data->REG_DIODE = NCT6106_REG_DIODE;
3671 data->DIODE_MASK = NCT6106_DIODE_MASK;
3672 data->REG_VIN = NCT6106_REG_IN;
3673 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3674 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3675 data->REG_TARGET = NCT6106_REG_TARGET;
3676 data->REG_FAN = NCT6106_REG_FAN;
3677 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3678 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3679 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3680 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3681 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3682 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3683 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3684 data->REG_PWM[0] = NCT6106_REG_PWM;
3685 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3686 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3687 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3688 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3689 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3690 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3691 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3692 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3693 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3694 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3695 data->REG_CRITICAL_TEMP_TOLERANCE
3696 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3697 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3698 data->CRITICAL_PWM_ENABLE_MASK
3699 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3700 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3701 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3702 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3703 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3704 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3705 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3706 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3707 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3708 data->REG_ALARM = NCT6106_REG_ALARM;
3709 data->ALARM_BITS = NCT6106_ALARM_BITS;
3710 data->REG_BEEP = NCT6106_REG_BEEP;
3711 data->BEEP_BITS = NCT6106_BEEP_BITS;
3713 reg_temp = NCT6106_REG_TEMP;
3714 reg_temp_mon = NCT6106_REG_TEMP_MON;
3715 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3716 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3717 reg_temp_over = NCT6106_REG_TEMP_OVER;
3718 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3719 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3720 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3721 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3722 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3723 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3729 data->auto_pwm_num = 6;
3730 data->has_fan_div = true;
3731 data->temp_fixed_num = 3;
3732 data->num_temp_alarms = 3;
3733 data->num_temp_beeps = 3;
3735 data->ALARM_BITS = NCT6775_ALARM_BITS;
3736 data->BEEP_BITS = NCT6775_BEEP_BITS;
3738 data->fan_from_reg = fan_from_reg16;
3739 data->fan_from_reg_min = fan_from_reg8;
3740 data->target_temp_mask = 0x7f;
3741 data->tolerance_mask = 0x0f;
3742 data->speed_tolerance_limit = 15;
3744 data->temp_label = nct6775_temp_label;
3745 data->temp_mask = NCT6775_TEMP_MASK;
3746 data->virt_temp_mask = NCT6775_VIRT_TEMP_MASK;
3748 data->REG_CONFIG = NCT6775_REG_CONFIG;
3749 data->REG_VBAT = NCT6775_REG_VBAT;
3750 data->REG_DIODE = NCT6775_REG_DIODE;
3751 data->DIODE_MASK = NCT6775_DIODE_MASK;
3752 data->REG_VIN = NCT6775_REG_IN;
3753 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3754 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3755 data->REG_TARGET = NCT6775_REG_TARGET;
3756 data->REG_FAN = NCT6775_REG_FAN;
3757 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3758 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3759 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3760 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3761 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3762 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3763 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3764 data->REG_PWM[0] = NCT6775_REG_PWM;
3765 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3766 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3767 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3768 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3769 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3770 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3771 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3772 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3773 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3774 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3775 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3776 data->REG_CRITICAL_TEMP_TOLERANCE
3777 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3778 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3779 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3780 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3781 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3782 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3783 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3784 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3785 data->REG_ALARM = NCT6775_REG_ALARM;
3786 data->REG_BEEP = NCT6775_REG_BEEP;
3788 reg_temp = NCT6775_REG_TEMP;
3789 reg_temp_mon = NCT6775_REG_TEMP_MON;
3790 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3791 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3792 reg_temp_over = NCT6775_REG_TEMP_OVER;
3793 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3794 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3795 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3796 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3802 data->auto_pwm_num = 4;
3803 data->has_fan_div = false;
3804 data->temp_fixed_num = 3;
3805 data->num_temp_alarms = 3;
3806 data->num_temp_beeps = 6;
3808 data->ALARM_BITS = NCT6776_ALARM_BITS;
3809 data->BEEP_BITS = NCT6776_BEEP_BITS;
3811 data->fan_from_reg = fan_from_reg13;
3812 data->fan_from_reg_min = fan_from_reg13;
3813 data->target_temp_mask = 0xff;
3814 data->tolerance_mask = 0x07;
3815 data->speed_tolerance_limit = 63;
3817 data->temp_label = nct6776_temp_label;
3818 data->temp_mask = NCT6776_TEMP_MASK;
3819 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3821 data->REG_CONFIG = NCT6775_REG_CONFIG;
3822 data->REG_VBAT = NCT6775_REG_VBAT;
3823 data->REG_DIODE = NCT6775_REG_DIODE;
3824 data->DIODE_MASK = NCT6775_DIODE_MASK;
3825 data->REG_VIN = NCT6775_REG_IN;
3826 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3827 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3828 data->REG_TARGET = NCT6775_REG_TARGET;
3829 data->REG_FAN = NCT6775_REG_FAN;
3830 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3831 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3832 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3833 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3834 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3835 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3836 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3837 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3838 data->REG_PWM[0] = NCT6775_REG_PWM;
3839 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3840 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3841 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3842 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3843 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3844 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3845 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3846 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3847 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3848 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3849 data->REG_CRITICAL_TEMP_TOLERANCE
3850 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3851 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3852 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3853 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3854 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3855 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3856 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3857 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3858 data->REG_ALARM = NCT6775_REG_ALARM;
3859 data->REG_BEEP = NCT6776_REG_BEEP;
3861 reg_temp = NCT6775_REG_TEMP;
3862 reg_temp_mon = NCT6775_REG_TEMP_MON;
3863 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3864 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3865 reg_temp_over = NCT6775_REG_TEMP_OVER;
3866 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3867 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3868 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3869 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3875 data->auto_pwm_num = 4;
3876 data->has_fan_div = false;
3877 data->temp_fixed_num = 6;
3878 data->num_temp_alarms = 2;
3879 data->num_temp_beeps = 2;
3881 data->ALARM_BITS = NCT6779_ALARM_BITS;
3882 data->BEEP_BITS = NCT6779_BEEP_BITS;
3884 data->fan_from_reg = fan_from_reg_rpm;
3885 data->fan_from_reg_min = fan_from_reg13;
3886 data->target_temp_mask = 0xff;
3887 data->tolerance_mask = 0x07;
3888 data->speed_tolerance_limit = 63;
3890 data->temp_label = nct6779_temp_label;
3891 data->temp_mask = NCT6779_TEMP_MASK;
3892 data->virt_temp_mask = NCT6779_VIRT_TEMP_MASK;
3894 data->REG_CONFIG = NCT6775_REG_CONFIG;
3895 data->REG_VBAT = NCT6775_REG_VBAT;
3896 data->REG_DIODE = NCT6775_REG_DIODE;
3897 data->DIODE_MASK = NCT6775_DIODE_MASK;
3898 data->REG_VIN = NCT6779_REG_IN;
3899 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3900 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3901 data->REG_TARGET = NCT6775_REG_TARGET;
3902 data->REG_FAN = NCT6779_REG_FAN;
3903 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3904 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3905 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3906 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3907 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3908 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3909 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3910 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3911 data->REG_PWM[0] = NCT6775_REG_PWM;
3912 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3913 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3914 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3915 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3916 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3917 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3918 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3919 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3920 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3921 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3922 data->REG_CRITICAL_TEMP_TOLERANCE
3923 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3924 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3925 data->CRITICAL_PWM_ENABLE_MASK
3926 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3927 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3928 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3929 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3930 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3931 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3932 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3933 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3934 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3935 data->REG_ALARM = NCT6779_REG_ALARM;
3936 data->REG_BEEP = NCT6776_REG_BEEP;
3938 reg_temp = NCT6779_REG_TEMP;
3939 reg_temp_mon = NCT6779_REG_TEMP_MON;
3940 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3941 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3942 reg_temp_over = NCT6779_REG_TEMP_OVER;
3943 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3944 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3945 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3946 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3955 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
3956 data->auto_pwm_num = 4;
3957 data->has_fan_div = false;
3958 data->temp_fixed_num = 6;
3959 data->num_temp_alarms = 2;
3960 data->num_temp_beeps = 2;
3962 data->ALARM_BITS = NCT6791_ALARM_BITS;
3963 data->BEEP_BITS = NCT6779_BEEP_BITS;
3965 data->fan_from_reg = fan_from_reg_rpm;
3966 data->fan_from_reg_min = fan_from_reg13;
3967 data->target_temp_mask = 0xff;
3968 data->tolerance_mask = 0x07;
3969 data->speed_tolerance_limit = 63;
3971 switch (data->kind) {
3974 data->temp_label = nct6779_temp_label;
3975 data->temp_mask = NCT6791_TEMP_MASK;
3976 data->virt_temp_mask = NCT6791_VIRT_TEMP_MASK;
3979 data->temp_label = nct6792_temp_label;
3980 data->temp_mask = NCT6792_TEMP_MASK;
3981 data->virt_temp_mask = NCT6792_VIRT_TEMP_MASK;
3984 data->temp_label = nct6793_temp_label;
3985 data->temp_mask = NCT6793_TEMP_MASK;
3986 data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
3989 data->temp_label = nct6795_temp_label;
3990 data->temp_mask = NCT6795_TEMP_MASK;
3991 data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
3994 data->temp_label = nct6796_temp_label;
3995 data->temp_mask = NCT6796_TEMP_MASK;
3996 data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
4000 data->REG_CONFIG = NCT6775_REG_CONFIG;
4001 data->REG_VBAT = NCT6775_REG_VBAT;
4002 data->REG_DIODE = NCT6775_REG_DIODE;
4003 data->DIODE_MASK = NCT6775_DIODE_MASK;
4004 data->REG_VIN = NCT6779_REG_IN;
4005 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
4006 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4007 data->REG_TARGET = NCT6775_REG_TARGET;
4008 data->REG_FAN = NCT6779_REG_FAN;
4009 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4010 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4011 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4012 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4013 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4014 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4015 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4016 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4017 data->REG_PWM[0] = NCT6775_REG_PWM;
4018 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4019 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4020 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4021 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4022 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4023 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4024 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4025 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4026 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4027 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4028 data->REG_CRITICAL_TEMP_TOLERANCE
4029 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4030 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4031 data->CRITICAL_PWM_ENABLE_MASK
4032 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4033 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4034 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4035 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4036 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4037 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4038 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4039 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4040 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4041 data->REG_ALARM = NCT6791_REG_ALARM;
4042 if (data->kind == nct6791)
4043 data->REG_BEEP = NCT6776_REG_BEEP;
4045 data->REG_BEEP = NCT6792_REG_BEEP;
4047 reg_temp = NCT6779_REG_TEMP;
4048 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4049 if (data->kind == nct6791) {
4050 reg_temp_mon = NCT6779_REG_TEMP_MON;
4051 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4053 reg_temp_mon = NCT6792_REG_TEMP_MON;
4054 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4056 reg_temp_over = NCT6779_REG_TEMP_OVER;
4057 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4058 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4059 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4060 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4066 data->have_in = BIT(data->in_num) - 1;
4067 data->have_temp = 0;
4070 * On some boards, not all available temperature sources are monitored,
4071 * even though some of the monitoring registers are unused.
4072 * Get list of unused monitoring registers, then detect if any fan
4073 * controls are configured to use unmonitored temperature sources.
4074 * If so, assign the unmonitored temperature sources to available
4075 * monitoring registers.
4079 for (i = 0; i < num_reg_temp; i++) {
4080 if (reg_temp[i] == 0)
4083 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4084 if (!src || (mask & BIT(src)))
4085 available |= BIT(i);
4091 * Now find unmonitored temperature registers and enable monitoring
4092 * if additional monitoring registers are available.
4094 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4095 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4098 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4099 for (i = 0; i < num_reg_temp; i++) {
4100 if (reg_temp[i] == 0)
4103 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4104 if (!src || (mask & BIT(src)))
4107 if (!(data->temp_mask & BIT(src))) {
4109 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4110 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4116 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4117 if (src <= data->temp_fixed_num) {
4118 data->have_temp |= BIT(src - 1);
4119 data->have_temp_fixed |= BIT(src - 1);
4120 data->reg_temp[0][src - 1] = reg_temp[i];
4121 data->reg_temp[1][src - 1] = reg_temp_over[i];
4122 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4123 if (reg_temp_crit_h && reg_temp_crit_h[i])
4124 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4125 else if (reg_temp_crit[src - 1])
4126 data->reg_temp[3][src - 1]
4127 = reg_temp_crit[src - 1];
4128 if (reg_temp_crit_l && reg_temp_crit_l[i])
4129 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4130 data->reg_temp_config[src - 1] = reg_temp_config[i];
4131 data->temp_src[src - 1] = src;
4138 /* Use dynamic index for other sources */
4139 data->have_temp |= BIT(s);
4140 data->reg_temp[0][s] = reg_temp[i];
4141 data->reg_temp[1][s] = reg_temp_over[i];
4142 data->reg_temp[2][s] = reg_temp_hyst[i];
4143 data->reg_temp_config[s] = reg_temp_config[i];
4144 if (reg_temp_crit_h && reg_temp_crit_h[i])
4145 data->reg_temp[3][s] = reg_temp_crit_h[i];
4146 else if (reg_temp_crit[src - 1])
4147 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4148 if (reg_temp_crit_l && reg_temp_crit_l[i])
4149 data->reg_temp[4][s] = reg_temp_crit_l[i];
4151 data->temp_src[s] = src;
4156 * Repeat with temperatures used for fan control.
4157 * This set of registers does not support limits.
4159 for (i = 0; i < num_reg_temp_mon; i++) {
4160 if (reg_temp_mon[i] == 0)
4163 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4167 if (!(data->temp_mask & BIT(src))) {
4169 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4170 src, i, data->REG_TEMP_SEL[i],
4176 * For virtual temperature sources, the 'virtual' temperature
4177 * for each fan reflects a different temperature, and there
4178 * are no duplicates.
4180 if (!(data->virt_temp_mask & BIT(src))) {
4181 if (mask & BIT(src))
4186 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4187 if (src <= data->temp_fixed_num) {
4188 if (data->have_temp & BIT(src - 1))
4190 data->have_temp |= BIT(src - 1);
4191 data->have_temp_fixed |= BIT(src - 1);
4192 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4193 data->temp_src[src - 1] = src;
4200 /* Use dynamic index for other sources */
4201 data->have_temp |= BIT(s);
4202 data->reg_temp[0][s] = reg_temp_mon[i];
4203 data->temp_src[s] = src;
4207 #ifdef USE_ALTERNATE
4209 * Go through the list of alternate temp registers and enable
4211 * The temperature is already monitored if the respective bit in <mask>
4214 for (i = 0; i < 31; i++) {
4215 if (!(data->temp_mask & BIT(i + 1)))
4217 if (!reg_temp_alternate[i])
4219 if (mask & BIT(i + 1))
4221 if (i < data->temp_fixed_num) {
4222 if (data->have_temp & BIT(i))
4224 data->have_temp |= BIT(i);
4225 data->have_temp_fixed |= BIT(i);
4226 data->reg_temp[0][i] = reg_temp_alternate[i];
4227 if (i < num_reg_temp) {
4228 data->reg_temp[1][i] = reg_temp_over[i];
4229 data->reg_temp[2][i] = reg_temp_hyst[i];
4231 data->temp_src[i] = i + 1;
4235 if (s >= NUM_TEMP) /* Abort if no more space */
4238 data->have_temp |= BIT(s);
4239 data->reg_temp[0][s] = reg_temp_alternate[i];
4240 data->temp_src[s] = i + 1;
4243 #endif /* USE_ALTERNATE */
4245 /* Initialize the chip */
4246 nct6775_init_device(data);
4248 err = superio_enter(sio_data->sioreg);
4252 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4253 switch (data->kind) {
4255 data->have_vid = (cr2a & 0x40);
4258 data->have_vid = (cr2a & 0x60) == 0x40;
4272 * We can get the VID input values directly at logical device D 0xe3.
4274 if (data->have_vid) {
4275 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4276 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4277 data->vrm = vid_which_vrm();
4283 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4284 tmp = superio_inb(sio_data->sioreg,
4285 NCT6775_REG_CR_FAN_DEBOUNCE);
4286 switch (data->kind) {
4305 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4307 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4311 nct6775_check_fan_inputs(data);
4313 superio_exit(sio_data->sioreg);
4315 /* Read fan clock dividers immediately */
4316 nct6775_init_fan_common(dev, data);
4318 /* Register sysfs hooks */
4319 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4322 return PTR_ERR(group);
4324 data->groups[num_attr_groups++] = group;
4326 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4327 fls(data->have_in));
4329 return PTR_ERR(group);
4331 data->groups[num_attr_groups++] = group;
4333 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4334 fls(data->has_fan));
4336 return PTR_ERR(group);
4338 data->groups[num_attr_groups++] = group;
4340 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4341 fls(data->have_temp));
4343 return PTR_ERR(group);
4345 data->groups[num_attr_groups++] = group;
4346 data->groups[num_attr_groups++] = &nct6775_group_other;
4348 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4349 data, data->groups);
4350 return PTR_ERR_OR_ZERO(hwmon_dev);
4353 static void nct6791_enable_io_mapping(int sioaddr)
4357 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4359 pr_info("Enabling hardware monitor logical device mappings.\n");
4360 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4365 static int __maybe_unused nct6775_suspend(struct device *dev)
4367 struct nct6775_data *data = nct6775_update_device(dev);
4369 mutex_lock(&data->update_lock);
4370 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4371 if (data->kind == nct6775) {
4372 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4373 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4375 mutex_unlock(&data->update_lock);
4380 static int __maybe_unused nct6775_resume(struct device *dev)
4382 struct nct6775_data *data = dev_get_drvdata(dev);
4383 int sioreg = data->sioreg;
4387 mutex_lock(&data->update_lock);
4388 data->bank = 0xff; /* Force initial bank selection */
4390 err = superio_enter(sioreg);
4394 superio_select(sioreg, NCT6775_LD_HWM);
4395 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4396 if (reg != data->sio_reg_enable)
4397 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4399 if (data->kind == nct6791 || data->kind == nct6792 ||
4400 data->kind == nct6793 || data->kind == nct6795 ||
4401 data->kind == nct6796)
4402 nct6791_enable_io_mapping(sioreg);
4404 superio_exit(sioreg);
4406 /* Restore limits */
4407 for (i = 0; i < data->in_num; i++) {
4408 if (!(data->have_in & BIT(i)))
4411 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4413 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4417 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4418 if (!(data->has_fan_min & BIT(i)))
4421 nct6775_write_value(data, data->REG_FAN_MIN[i],
4425 for (i = 0; i < NUM_TEMP; i++) {
4426 if (!(data->have_temp & BIT(i)))
4429 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4430 if (data->reg_temp[j][i])
4431 nct6775_write_temp(data, data->reg_temp[j][i],
4435 /* Restore other settings */
4436 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4437 if (data->kind == nct6775) {
4438 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4439 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4443 /* Force re-reading all values */
4444 data->valid = false;
4445 mutex_unlock(&data->update_lock);
4450 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4452 static struct platform_driver nct6775_driver = {
4455 .pm = &nct6775_dev_pm_ops,
4457 .probe = nct6775_probe,
4460 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4461 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4467 err = superio_enter(sioaddr);
4471 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4472 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4473 if (force_id && val != 0xffff)
4476 switch (val & SIO_ID_MASK) {
4477 case SIO_NCT6106_ID:
4478 sio_data->kind = nct6106;
4480 case SIO_NCT6775_ID:
4481 sio_data->kind = nct6775;
4483 case SIO_NCT6776_ID:
4484 sio_data->kind = nct6776;
4486 case SIO_NCT6779_ID:
4487 sio_data->kind = nct6779;
4489 case SIO_NCT6791_ID:
4490 sio_data->kind = nct6791;
4492 case SIO_NCT6792_ID:
4493 sio_data->kind = nct6792;
4495 case SIO_NCT6793_ID:
4496 sio_data->kind = nct6793;
4498 case SIO_NCT6795_ID:
4499 sio_data->kind = nct6795;
4501 case SIO_NCT6796_ID:
4502 sio_data->kind = nct6796;
4506 pr_debug("unsupported chip ID: 0x%04x\n", val);
4507 superio_exit(sioaddr);
4511 /* We have a known chip, find the HWM I/O address */
4512 superio_select(sioaddr, NCT6775_LD_HWM);
4513 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4514 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4515 addr = val & IOREGION_ALIGNMENT;
4517 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4518 superio_exit(sioaddr);
4522 /* Activate logical device if needed */
4523 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4524 if (!(val & 0x01)) {
4525 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4526 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4529 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4530 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4531 sio_data->kind == nct6796)
4532 nct6791_enable_io_mapping(sioaddr);
4534 superio_exit(sioaddr);
4535 pr_info("Found %s or compatible chip at %#x:%#x\n",
4536 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4537 sio_data->sioreg = sioaddr;
4543 * when Super-I/O functions move to a separate file, the Super-I/O
4544 * bus will manage the lifetime of the device and this module will only keep
4545 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4546 * must keep track of the device
4548 static struct platform_device *pdev[2];
4550 static int __init sensors_nct6775_init(void)
4555 struct resource res;
4556 struct nct6775_sio_data sio_data;
4557 int sioaddr[2] = { 0x2e, 0x4e };
4559 err = platform_driver_register(&nct6775_driver);
4564 * initialize sio_data->kind and sio_data->sioreg.
4566 * when Super-I/O functions move to a separate file, the Super-I/O
4567 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4568 * nct6775 hardware monitor, and call probe()
4570 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4571 address = nct6775_find(sioaddr[i], &sio_data);
4577 pdev[i] = platform_device_alloc(DRVNAME, address);
4580 goto exit_device_unregister;
4583 err = platform_device_add_data(pdev[i], &sio_data,
4584 sizeof(struct nct6775_sio_data));
4586 goto exit_device_put;
4588 memset(&res, 0, sizeof(res));
4590 res.start = address + IOREGION_OFFSET;
4591 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4592 res.flags = IORESOURCE_IO;
4594 err = acpi_check_resource_conflict(&res);
4596 platform_device_put(pdev[i]);
4601 err = platform_device_add_resources(pdev[i], &res, 1);
4603 goto exit_device_put;
4605 /* platform_device_add calls probe() */
4606 err = platform_device_add(pdev[i]);
4608 goto exit_device_put;
4612 goto exit_unregister;
4618 platform_device_put(pdev[i]);
4619 exit_device_unregister:
4622 platform_device_unregister(pdev[i]);
4625 platform_driver_unregister(&nct6775_driver);
4629 static void __exit sensors_nct6775_exit(void)
4633 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4635 platform_device_unregister(pdev[i]);
4637 platform_driver_unregister(&nct6775_driver);
4640 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4641 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4642 MODULE_LICENSE("GPL");
4644 module_init(sensors_nct6775_init);
4645 module_exit(sensors_nct6775_exit);