drivers/gpu/drm/xlnx/zynqmp_dpsub.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * ZynqMP DPSUB Subsystem Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
   9  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  */
  11
  12 #ifndef _ZYNQMP_DPSUB_H_
  13 #define _ZYNQMP_DPSUB_H_
  14
  15 struct clk;
  16 struct device;
  17 struct drm_bridge;
  18 struct zynqmp_disp;
  19 struct zynqmp_disp_layer;
  20 struct zynqmp_dp;
  21 struct zynqmp_dpsub_drm;
  22
  23 #define ZYNQMP_DPSUB_NUM_LAYERS                         2
  24
  25 enum zynqmp_dpsub_port {
  26         ZYNQMP_DPSUB_PORT_LIVE_VIDEO,
  27         ZYNQMP_DPSUB_PORT_LIVE_GFX,
  28         ZYNQMP_DPSUB_PORT_LIVE_AUDIO,
  29         ZYNQMP_DPSUB_PORT_OUT_VIDEO,
  30         ZYNQMP_DPSUB_PORT_OUT_AUDIO,
  31         ZYNQMP_DPSUB_PORT_OUT_DP,
  32         ZYNQMP_DPSUB_NUM_PORTS,
  33 };
  34
  35 enum zynqmp_dpsub_format {
  36         ZYNQMP_DPSUB_FORMAT_RGB,
  37         ZYNQMP_DPSUB_FORMAT_YCRCB444,
  38         ZYNQMP_DPSUB_FORMAT_YCRCB422,
  39         ZYNQMP_DPSUB_FORMAT_YONLY,
  40 };
  41
  42 /**
  43  * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
  44  * @dev: The physical device
  45  * @apb_clk: The APB clock
  46  * @vid_clk: Video clock
  47  * @vid_clk_from_ps: True of the video clock comes from PS, false from PL
  48  * @aud_clk: Audio clock
  49  * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL
  50  * @connected_ports: Bitmask of connected ports in the device tree
  51  * @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is
  52  *      driven by the live input
  53  * @drm: The DRM/KMS device data
  54  * @bridge: The DP encoder bridge
  55  * @disp: The display controller
  56  * @dp: The DisplayPort controller
  57  * @dma_align: DMA alignment constraint (must be a power of 2)
  58  */
  59 struct zynqmp_dpsub {
  60         struct device *dev;
  61
  62         struct clk *apb_clk;
  63         struct clk *vid_clk;
  64         bool vid_clk_from_ps;
  65         struct clk *aud_clk;
  66         bool aud_clk_from_ps;
  67
  68         unsigned int connected_ports;
  69         bool dma_enabled;
  70
  71         struct zynqmp_dpsub_drm *drm;
  72         struct drm_bridge *bridge;
  73
  74         struct zynqmp_disp *disp;
  75         struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];
  76         struct zynqmp_dp *dp;
  77
  78         unsigned int dma_align;
  79 };
  80
  81 bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub);
  82 unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub);
  83
  84 void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);
  85
  86 #endif /* _ZYNQMP_DPSUB_H_ */