1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP Display Controller Driver
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_atomic_uapi.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_device.h>
17 #include <drm/drm_fb_cma_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_managed.h>
21 #include <drm/drm_plane.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_vblank.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/dma/xilinx_dpdma.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/spinlock.h>
36 #include "zynqmp_disp.h"
37 #include "zynqmp_disp_regs.h"
38 #include "zynqmp_dp.h"
39 #include "zynqmp_dpsub.h"
45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
46 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer.
48 * +------------------------------------------------------------+
49 * +--------+ | +----------------+ +-----------+ |
50 * | DPDMA | --->| | --> | Video | Video +-------------+ |
51 * | 4x vid | | | | | Rendering | -+--> | | | +------+
52 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
53 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
54 * | | and STC | +-----------+ | | Controller | | +------+
55 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
56 * | | | | Mixer | --+-> | | | +------+
57 * Live Audio --->| | --> | | || +-------------+ |
58 * | +----------------+ +-----------+ || |
59 * +---------------------------------------||-------------------+
64 * Only non-live input from the DPDMA and output to the DisplayPort Source
65 * Controller are currently supported. Interface with the programmable logic
66 * for live streams is not implemented.
68 * The display controller code creates planes for the DPDMA video and graphics
69 * layers, and a CRTC for the Video Rendering Pipeline.
72 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4
73 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6
75 #define ZYNQMP_DISP_NUM_LAYERS 2
76 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3
79 * struct zynqmp_disp_format - Display subsystem format information
80 * @drm_fmt: DRM format (4CC)
81 * @buf_fmt: AV buffer format
82 * @bus_fmt: Media bus formats (live formats)
83 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats
84 * @sf: Scaling factors for color components
86 struct zynqmp_disp_format {
95 * enum zynqmp_disp_layer_id - Layer identifier
96 * @ZYNQMP_DISP_LAYER_VID: Video layer
97 * @ZYNQMP_DISP_LAYER_GFX: Graphics layer
99 enum zynqmp_disp_layer_id {
100 ZYNQMP_DISP_LAYER_VID,
101 ZYNQMP_DISP_LAYER_GFX
105 * enum zynqmp_disp_layer_mode - Layer mode
106 * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode
107 * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode
109 enum zynqmp_disp_layer_mode {
110 ZYNQMP_DISP_LAYER_NONLIVE,
111 ZYNQMP_DISP_LAYER_LIVE
115 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer
117 * @xt: Interleaved DMA descriptor template
118 * @sgl: Data chunk for dma_interleaved_template
120 struct zynqmp_disp_layer_dma {
121 struct dma_chan *chan;
122 struct dma_interleaved_template xt;
123 struct data_chunk sgl;
127 * struct zynqmp_disp_layer_info - Static layer information
128 * @formats: Array of supported formats
129 * @num_formats: Number of formats in @formats array
130 * @num_channels: Number of DMA channels
132 struct zynqmp_disp_layer_info {
133 const struct zynqmp_disp_format *formats;
134 unsigned int num_formats;
135 unsigned int num_channels;
139 * struct zynqmp_disp_layer - Display layer (DRM plane)
142 * @disp: Back pointer to struct zynqmp_disp
143 * @info: Static layer information
144 * @dmas: DMA channels
145 * @disp_fmt: Current format information
146 * @drm_fmt: Current DRM format information
147 * @mode: Current operation mode
149 struct zynqmp_disp_layer {
150 struct drm_plane plane;
151 enum zynqmp_disp_layer_id id;
152 struct zynqmp_disp *disp;
153 const struct zynqmp_disp_layer_info *info;
155 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES];
157 const struct zynqmp_disp_format *disp_fmt;
158 const struct drm_format_info *drm_fmt;
159 enum zynqmp_disp_layer_mode mode;
163 * struct zynqmp_disp - Display controller
164 * @dev: Device structure
166 * @dpsub: Display subsystem
168 * @blend.base: Register I/O base address for the blender
169 * @avbuf.base: Register I/O base address for the audio/video buffer manager
170 * @audio.base: Registers I/O base address for the audio mixer
171 * @audio.clk: Audio clock
172 * @audio.clk_from_ps: True of the audio clock comes from PS, false from PL
173 * @layers: Layers (planes)
174 * @event: Pending vblank event request
176 * @pclk_from_ps: True of the video clock comes from PS, false from PL
180 struct drm_device *drm;
181 struct zynqmp_dpsub *dpsub;
183 struct drm_crtc crtc;
197 struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS];
199 struct drm_pending_vblank_event *event;
205 /* -----------------------------------------------------------------------------
206 * Audio/Video Buffer Manager
209 static const u32 scaling_factors_444[] = {
210 ZYNQMP_DISP_AV_BUF_4BIT_SF,
211 ZYNQMP_DISP_AV_BUF_4BIT_SF,
212 ZYNQMP_DISP_AV_BUF_4BIT_SF,
215 static const u32 scaling_factors_555[] = {
216 ZYNQMP_DISP_AV_BUF_5BIT_SF,
217 ZYNQMP_DISP_AV_BUF_5BIT_SF,
218 ZYNQMP_DISP_AV_BUF_5BIT_SF,
221 static const u32 scaling_factors_565[] = {
222 ZYNQMP_DISP_AV_BUF_5BIT_SF,
223 ZYNQMP_DISP_AV_BUF_6BIT_SF,
224 ZYNQMP_DISP_AV_BUF_5BIT_SF,
227 static const u32 scaling_factors_888[] = {
228 ZYNQMP_DISP_AV_BUF_8BIT_SF,
229 ZYNQMP_DISP_AV_BUF_8BIT_SF,
230 ZYNQMP_DISP_AV_BUF_8BIT_SF,
233 static const u32 scaling_factors_101010[] = {
234 ZYNQMP_DISP_AV_BUF_10BIT_SF,
235 ZYNQMP_DISP_AV_BUF_10BIT_SF,
236 ZYNQMP_DISP_AV_BUF_10BIT_SF,
239 /* List of video layer formats */
240 static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
242 .drm_fmt = DRM_FORMAT_VYUY,
243 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
245 .sf = scaling_factors_888,
247 .drm_fmt = DRM_FORMAT_UYVY,
248 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
250 .sf = scaling_factors_888,
252 .drm_fmt = DRM_FORMAT_YUYV,
253 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
255 .sf = scaling_factors_888,
257 .drm_fmt = DRM_FORMAT_YVYU,
258 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
260 .sf = scaling_factors_888,
262 .drm_fmt = DRM_FORMAT_YUV422,
263 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
265 .sf = scaling_factors_888,
267 .drm_fmt = DRM_FORMAT_YVU422,
268 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
270 .sf = scaling_factors_888,
272 .drm_fmt = DRM_FORMAT_YUV444,
273 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
275 .sf = scaling_factors_888,
277 .drm_fmt = DRM_FORMAT_YVU444,
278 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
280 .sf = scaling_factors_888,
282 .drm_fmt = DRM_FORMAT_NV16,
283 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
285 .sf = scaling_factors_888,
287 .drm_fmt = DRM_FORMAT_NV61,
288 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
290 .sf = scaling_factors_888,
292 .drm_fmt = DRM_FORMAT_BGR888,
293 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
295 .sf = scaling_factors_888,
297 .drm_fmt = DRM_FORMAT_RGB888,
298 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
300 .sf = scaling_factors_888,
302 .drm_fmt = DRM_FORMAT_XBGR8888,
303 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
305 .sf = scaling_factors_888,
307 .drm_fmt = DRM_FORMAT_XRGB8888,
308 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
310 .sf = scaling_factors_888,
312 .drm_fmt = DRM_FORMAT_XBGR2101010,
313 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
315 .sf = scaling_factors_101010,
317 .drm_fmt = DRM_FORMAT_XRGB2101010,
318 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
320 .sf = scaling_factors_101010,
322 .drm_fmt = DRM_FORMAT_YUV420,
323 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
325 .sf = scaling_factors_888,
327 .drm_fmt = DRM_FORMAT_YVU420,
328 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
330 .sf = scaling_factors_888,
332 .drm_fmt = DRM_FORMAT_NV12,
333 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
335 .sf = scaling_factors_888,
337 .drm_fmt = DRM_FORMAT_NV21,
338 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
340 .sf = scaling_factors_888,
344 /* List of graphics layer formats */
345 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = {
347 .drm_fmt = DRM_FORMAT_ABGR8888,
348 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
350 .sf = scaling_factors_888,
352 .drm_fmt = DRM_FORMAT_ARGB8888,
353 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
355 .sf = scaling_factors_888,
357 .drm_fmt = DRM_FORMAT_RGBA8888,
358 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
360 .sf = scaling_factors_888,
362 .drm_fmt = DRM_FORMAT_BGRA8888,
363 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
365 .sf = scaling_factors_888,
367 .drm_fmt = DRM_FORMAT_BGR888,
368 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888,
370 .sf = scaling_factors_888,
372 .drm_fmt = DRM_FORMAT_RGB888,
373 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888,
375 .sf = scaling_factors_888,
377 .drm_fmt = DRM_FORMAT_RGBA5551,
378 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
380 .sf = scaling_factors_555,
382 .drm_fmt = DRM_FORMAT_BGRA5551,
383 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
385 .sf = scaling_factors_555,
387 .drm_fmt = DRM_FORMAT_RGBA4444,
388 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
390 .sf = scaling_factors_444,
392 .drm_fmt = DRM_FORMAT_BGRA4444,
393 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
395 .sf = scaling_factors_444,
397 .drm_fmt = DRM_FORMAT_RGB565,
398 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
400 .sf = scaling_factors_565,
402 .drm_fmt = DRM_FORMAT_BGR565,
403 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
405 .sf = scaling_factors_565,
409 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg)
411 return readl(disp->avbuf.base + reg);
414 static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val)
416 writel(val, disp->avbuf.base + reg);
419 static bool zynqmp_disp_layer_is_gfx(const struct zynqmp_disp_layer *layer)
421 return layer->id == ZYNQMP_DISP_LAYER_GFX;
424 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer)
426 return layer->id == ZYNQMP_DISP_LAYER_VID;
430 * zynqmp_disp_avbuf_set_format - Set the input format for a layer
431 * @disp: Display controller
433 * @fmt: The format information
435 * Set the video buffer manager format for @layer to @fmt.
437 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp,
438 struct zynqmp_disp_layer *layer,
439 const struct zynqmp_disp_format *fmt)
444 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT);
445 val &= zynqmp_disp_layer_is_video(layer)
446 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK
447 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK;
449 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val);
451 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) {
452 unsigned int reg = zynqmp_disp_layer_is_video(layer)
453 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i)
454 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i);
456 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]);
461 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources
462 * @disp: Display controller
463 * @video_from_ps: True if the video clock originates from the PS
464 * @audio_from_ps: True if the audio clock originates from the PS
465 * @timings_internal: True if video timings are generated internally
467 * Set the source for the video and audio clocks, as well as for the video
468 * timings. Clocks can originate from the PS or PL, and timings can be
469 * generated internally or externally.
472 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp,
473 bool video_from_ps, bool audio_from_ps,
474 bool timings_internal)
479 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
481 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
482 if (timings_internal)
483 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
485 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val);
489 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels
490 * @disp: Display controller
492 * Enable all (video and audio) buffer channels.
494 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp)
499 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
500 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX <<
501 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
503 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++)
504 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
507 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
508 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX <<
509 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
511 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
512 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
517 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels
518 * @disp: Display controller
520 * Disable all (video and audio) buffer channels.
522 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp)
526 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
527 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i),
528 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH);
532 * zynqmp_disp_avbuf_enable_audio - Enable audio
533 * @disp: Display controller
535 * Enable all audio buffers with a non-live (memory) source.
537 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp)
541 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
542 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
543 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM;
544 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
545 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
549 * zynqmp_disp_avbuf_disable_audio - Disable audio
550 * @disp: Display controller
552 * Disable all audio buffers.
554 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp)
558 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
559 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
560 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE;
561 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
562 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
566 * zynqmp_disp_avbuf_enable_video - Enable a video layer
567 * @disp: Display controller
569 * @mode: Operating mode of layer
571 * Enable the video/graphics buffer for @layer.
573 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp,
574 struct zynqmp_disp_layer *layer,
575 enum zynqmp_disp_layer_mode mode)
579 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
580 if (zynqmp_disp_layer_is_video(layer)) {
581 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
582 if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
583 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM;
585 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE;
587 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
588 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
589 if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
590 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
592 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE;
594 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
598 * zynqmp_disp_avbuf_disable_video - Disable a video layer
599 * @disp: Display controller
602 * Disable the video/graphics buffer for @layer.
604 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp,
605 struct zynqmp_disp_layer *layer)
609 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT);
610 if (zynqmp_disp_layer_is_video(layer)) {
611 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
612 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE;
614 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
615 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE;
617 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
621 * zynqmp_disp_avbuf_enable - Enable the video pipe
622 * @disp: Display controller
624 * De-assert the video pipe reset.
626 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp)
628 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
632 * zynqmp_disp_avbuf_disable - Disable the video pipe
633 * @disp: Display controller
635 * Assert the video pipe reset.
637 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp)
639 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG,
640 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST);
643 /* -----------------------------------------------------------------------------
644 * Blender (Video Pipeline)
647 static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val)
649 writel(val, disp->blend.base + reg);
653 * Colorspace conversion matrices.
655 * Hardcode RGB <-> YUV conversion to full-range SDTV for now.
657 static const u16 csc_zero_matrix[] = {
663 static const u16 csc_identity_matrix[] = {
669 static const u32 csc_zero_offsets[] = {
673 static const u16 csc_rgb_to_sdtv_matrix[] = {
675 0x7d4d, 0x7ab3, 0x800,
676 0x800, 0x794d, 0x7eb3
679 static const u32 csc_rgb_to_sdtv_offsets[] = {
680 0x0, 0x8000000, 0x8000000
683 static const u16 csc_sdtv_to_rgb_matrix[] = {
685 0x1000, 0x7483, 0x7a7f,
689 static const u32 csc_sdtv_to_rgb_offsets[] = {
694 * zynqmp_disp_blend_set_output_format - Set the output format of the blender
695 * @disp: Display controller
696 * @format: Output format
698 * Set the output format of the blender to @format.
700 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp,
701 enum zynqmp_dpsub_format format)
703 static const unsigned int blend_output_fmts[] = {
704 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB,
705 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444,
706 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422
707 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE,
708 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY,
711 u32 fmt = blend_output_fmts[format];
716 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
717 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) {
718 coeffs = csc_identity_matrix;
719 offsets = csc_zero_offsets;
721 coeffs = csc_rgb_to_sdtv_matrix;
722 offsets = csc_rgb_to_sdtv_offsets;
725 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
726 zynqmp_disp_blend_write(disp,
727 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i),
730 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
731 zynqmp_disp_blend_write(disp,
732 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i),
737 * zynqmp_disp_blend_set_bg_color - Set the background color
738 * @disp: Display controller
739 * @rcr: Red/Cr color component
740 * @gy: Green/Y color component
741 * @bcb: Blue/Cb color component
743 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and
744 * B or Cr, Y and Cb components respectively depending on the selected output
747 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp,
748 u32 rcr, u32 gy, u32 bcb)
750 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr);
751 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy);
752 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb);
756 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending
757 * @disp: Display controller
758 * @enable: True to enable global alpha blending
759 * @alpha: Global alpha value (ignored if @enabled is false)
761 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,
762 bool enable, u32 alpha)
764 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
765 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) |
766 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0));
770 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer
771 * @disp: Display controller
773 * @coeffs: Colorspace conversion matrix
774 * @offsets: Colorspace conversion offsets
776 * Configure the input colorspace conversion matrix and offsets for the @layer.
777 * Columns of the matrix are automatically swapped based on the input format to
778 * handle RGB and YCrCb components permutations.
780 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp,
781 struct zynqmp_disp_layer *layer,
785 unsigned int swap[3] = { 0, 1, 2 };
789 if (layer->disp_fmt->swap) {
790 if (layer->drm_fmt->is_yuv) {
801 if (zynqmp_disp_layer_is_video(layer))
802 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0);
804 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0);
806 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) {
807 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]);
808 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]);
809 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]);
812 if (zynqmp_disp_layer_is_video(layer))
813 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0);
815 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0);
817 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
818 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]);
822 * zynqmp_disp_blend_layer_enable - Enable a layer
823 * @disp: Display controller
826 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
827 struct zynqmp_disp_layer *layer)
833 val = (layer->drm_fmt->is_yuv ?
834 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) |
835 (layer->drm_fmt->hsub > 1 ?
836 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0);
838 zynqmp_disp_blend_write(disp,
839 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
842 if (layer->drm_fmt->is_yuv) {
843 coeffs = csc_sdtv_to_rgb_matrix;
844 offsets = csc_sdtv_to_rgb_offsets;
846 coeffs = csc_identity_matrix;
847 offsets = csc_zero_offsets;
850 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets);
854 * zynqmp_disp_blend_layer_disable - Disable a layer
855 * @disp: Display controller
858 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp,
859 struct zynqmp_disp_layer *layer)
861 zynqmp_disp_blend_write(disp,
862 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
865 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix,
869 /* -----------------------------------------------------------------------------
873 static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val)
875 writel(val, disp->audio.base + reg);
879 * zynqmp_disp_audio_enable - Enable the audio mixer
880 * @disp: Display controller
882 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to
883 * default values by the reset, set the default mixer volume explicitly.
885 static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp)
887 /* Clear the audio soft reset register as it's an non-reset flop. */
888 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
889 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME,
890 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE);
894 * zynqmp_disp_audio_disable - Disable the audio mixer
895 * @disp: Display controller
897 * Disable the audio mixer by asserting its soft reset.
899 static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp)
901 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET,
902 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST);
905 static void zynqmp_disp_audio_init(struct zynqmp_disp *disp)
907 /* Try the live PL audio clock. */
908 disp->audio.clk = devm_clk_get(disp->dev, "dp_live_audio_aclk");
909 if (!IS_ERR(disp->audio.clk)) {
910 disp->audio.clk_from_ps = false;
914 /* If the live PL audio clock is not valid, fall back to PS clock. */
915 disp->audio.clk = devm_clk_get(disp->dev, "dp_aud_clk");
916 if (!IS_ERR(disp->audio.clk)) {
917 disp->audio.clk_from_ps = true;
921 dev_err(disp->dev, "audio disabled due to missing clock\n");
924 /* -----------------------------------------------------------------------------
925 * ZynqMP Display external functions for zynqmp_dp
929 * zynqmp_disp_handle_vblank - Handle the vblank event
930 * @disp: Display controller
932 * This function handles the vblank interrupt, and sends an event to
933 * CRTC object. This will be called by the DP vblank interrupt handler.
935 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp)
937 struct drm_crtc *crtc = &disp->crtc;
939 drm_crtc_handle_vblank(crtc);
943 * zynqmp_disp_audio_enabled - If the audio is enabled
944 * @disp: Display controller
946 * Return if the audio is enabled depending on the audio clock.
948 * Return: true if audio is enabled, or false.
950 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp)
952 return !!disp->audio.clk;
956 * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate
957 * @disp: Display controller
959 * Return: the current audio clock rate.
961 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp)
963 if (zynqmp_disp_audio_enabled(disp))
965 return clk_get_rate(disp->audio.clk);
969 * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask
970 * @disp: Display controller
972 * Return: the crtc mask of the zyqnmp_disp CRTC.
974 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp)
976 return drm_crtc_mask(&disp->crtc);
979 /* -----------------------------------------------------------------------------
980 * ZynqMP Display Layer & DRM Plane
984 * zynqmp_disp_layer_find_format - Find format information for a DRM format
986 * @drm_fmt: DRM format to search
988 * Search display subsystem format information corresponding to the given DRM
989 * format @drm_fmt for the @layer, and return a pointer to the format
992 * Return: A pointer to the format descriptor if found, NULL otherwise
994 static const struct zynqmp_disp_format *
995 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer,
1000 for (i = 0; i < layer->info->num_formats; i++) {
1001 if (layer->info->formats[i].drm_fmt == drm_fmt)
1002 return &layer->info->formats[i];
1009 * zynqmp_disp_layer_enable - Enable a layer
1012 * Enable the @layer in the audio/video buffer manager and the blender. DMA
1013 * channels are started separately by zynqmp_disp_layer_update().
1015 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer)
1017 zynqmp_disp_avbuf_enable_video(layer->disp, layer,
1018 ZYNQMP_DISP_LAYER_NONLIVE);
1019 zynqmp_disp_blend_layer_enable(layer->disp, layer);
1021 layer->mode = ZYNQMP_DISP_LAYER_NONLIVE;
1025 * zynqmp_disp_layer_disable - Disable the layer
1028 * Disable the layer by stopping its DMA channels and disabling it in the
1029 * audio/video buffer manager and the blender.
1031 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)
1035 for (i = 0; i < layer->drm_fmt->num_planes; i++)
1036 dmaengine_terminate_sync(layer->dmas[i].chan);
1038 zynqmp_disp_avbuf_disable_video(layer->disp, layer);
1039 zynqmp_disp_blend_layer_disable(layer->disp, layer);
1043 * zynqmp_disp_layer_set_format - Set the layer format
1045 * @state: The plane state
1047 * Set the format for @layer based on @state->fb->format. The layer must be
1050 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
1051 struct drm_plane_state *state)
1053 const struct drm_format_info *info = state->fb->format;
1056 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format);
1057 layer->drm_fmt = info;
1059 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt);
1062 * Set pconfig for each DMA channel to indicate they're part of a
1065 for (i = 0; i < info->num_planes; i++) {
1066 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1067 struct xilinx_dpdma_peripheral_config pconfig = {
1068 .video_group = true,
1070 struct dma_slave_config config = {
1071 .direction = DMA_MEM_TO_DEV,
1072 .peripheral_config = &pconfig,
1073 .peripheral_size = sizeof(pconfig),
1076 dmaengine_slave_config(dma->chan, &config);
1081 * zynqmp_disp_layer_update - Update the layer framebuffer
1083 * @state: The plane state
1085 * Update the framebuffer for the layer by issuing a new DMA engine transaction
1086 * for the new framebuffer.
1088 * Return: 0 on success, or the DMA descriptor failure error otherwise
1090 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
1091 struct drm_plane_state *state)
1093 const struct drm_format_info *info = layer->drm_fmt;
1096 for (i = 0; i < layer->drm_fmt->num_planes; i++) {
1097 unsigned int width = state->crtc_w / (i ? info->hsub : 1);
1098 unsigned int height = state->crtc_h / (i ? info->vsub : 1);
1099 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1100 struct dma_async_tx_descriptor *desc;
1103 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i);
1105 dma->xt.numf = height;
1106 dma->sgl.size = width * info->cpp[i];
1107 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
1108 dma->xt.src_start = paddr;
1109 dma->xt.frame_size = 1;
1110 dma->xt.dir = DMA_MEM_TO_DEV;
1111 dma->xt.src_sgl = true;
1112 dma->xt.dst_sgl = false;
1114 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt,
1119 dev_err(layer->disp->dev,
1120 "failed to prepare DMA descriptor\n");
1124 dmaengine_submit(desc);
1125 dma_async_issue_pending(dma->chan);
1131 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane)
1133 return container_of(plane, struct zynqmp_disp_layer, plane);
1137 zynqmp_disp_plane_atomic_check(struct drm_plane *plane,
1138 struct drm_atomic_state *state)
1140 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1142 struct drm_crtc_state *crtc_state;
1144 if (!new_plane_state->crtc)
1147 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
1148 if (IS_ERR(crtc_state))
1149 return PTR_ERR(crtc_state);
1151 return drm_atomic_helper_check_plane_state(new_plane_state,
1153 DRM_PLANE_HELPER_NO_SCALING,
1154 DRM_PLANE_HELPER_NO_SCALING,
1159 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane,
1160 struct drm_atomic_state *state)
1162 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
1164 struct zynqmp_disp_layer *layer = plane_to_layer(plane);
1169 zynqmp_disp_layer_disable(layer);
1171 if (zynqmp_disp_layer_is_gfx(layer))
1172 zynqmp_disp_blend_set_global_alpha(layer->disp, false,
1173 plane->state->alpha >> 8);
1177 zynqmp_disp_plane_atomic_update(struct drm_plane *plane,
1178 struct drm_atomic_state *state)
1180 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
1181 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1182 struct zynqmp_disp_layer *layer = plane_to_layer(plane);
1183 bool format_changed = false;
1185 if (!old_state->fb ||
1186 old_state->fb->format->format != new_state->fb->format->format)
1187 format_changed = true;
1190 * If the format has changed (including going from a previously
1191 * disabled state to any format), reconfigure the format. Disable the
1192 * plane first if needed.
1194 if (format_changed) {
1196 zynqmp_disp_layer_disable(layer);
1198 zynqmp_disp_layer_set_format(layer, new_state);
1201 zynqmp_disp_layer_update(layer, new_state);
1203 if (zynqmp_disp_layer_is_gfx(layer))
1204 zynqmp_disp_blend_set_global_alpha(layer->disp, true,
1205 plane->state->alpha >> 8);
1207 /* Enable or re-enable the plane is the format has changed. */
1209 zynqmp_disp_layer_enable(layer);
1212 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = {
1213 .atomic_check = zynqmp_disp_plane_atomic_check,
1214 .atomic_update = zynqmp_disp_plane_atomic_update,
1215 .atomic_disable = zynqmp_disp_plane_atomic_disable,
1218 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = {
1219 .update_plane = drm_atomic_helper_update_plane,
1220 .disable_plane = drm_atomic_helper_disable_plane,
1221 .destroy = drm_plane_cleanup,
1222 .reset = drm_atomic_helper_plane_reset,
1223 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1224 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1227 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp)
1232 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
1233 struct zynqmp_disp_layer *layer = &disp->layers[i];
1234 enum drm_plane_type type;
1237 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats),
1238 layer->info->num_formats,
1243 for (j = 0; j < layer->info->num_formats; ++j)
1244 drm_formats[j] = layer->info->formats[j].drm_fmt;
1246 /* Graphics layer is primary, and video layer is overlay. */
1247 type = zynqmp_disp_layer_is_video(layer)
1248 ? DRM_PLANE_TYPE_OVERLAY : DRM_PLANE_TYPE_PRIMARY;
1249 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0,
1250 &zynqmp_disp_plane_funcs,
1252 layer->info->num_formats,
1257 drm_plane_helper_add(&layer->plane,
1258 &zynqmp_disp_plane_helper_funcs);
1260 drm_plane_create_zpos_immutable_property(&layer->plane, i);
1261 if (zynqmp_disp_layer_is_gfx(layer))
1262 drm_plane_create_alpha_property(&layer->plane);
1269 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer
1270 * @disp: Display controller
1273 * Release the DMA channels associated with @layer.
1275 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
1276 struct zynqmp_disp_layer *layer)
1283 for (i = 0; i < layer->info->num_channels; i++) {
1284 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1289 /* Make sure the channel is terminated before release. */
1290 dmaengine_terminate_sync(dma->chan);
1291 dma_release_channel(dma->chan);
1296 * zynqmp_disp_destroy_layers - Destroy all layers
1297 * @disp: Display controller
1299 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)
1303 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
1304 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1308 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer
1309 * @disp: Display controller
1312 * Request all DMA engine channels needed by @layer.
1314 * Return: 0 on success, or the DMA channel request error otherwise
1316 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
1317 struct zynqmp_disp_layer *layer)
1319 static const char * const dma_names[] = { "vid", "gfx" };
1323 for (i = 0; i < layer->info->num_channels; i++) {
1324 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1325 char dma_channel_name[16];
1327 snprintf(dma_channel_name, sizeof(dma_channel_name),
1328 "%s%u", dma_names[layer->id], i);
1329 dma->chan = dma_request_chan(disp->dev, dma_channel_name);
1330 if (IS_ERR(dma->chan)) {
1331 dev_err(disp->dev, "failed to request dma channel\n");
1332 ret = PTR_ERR(dma->chan);
1342 * zynqmp_disp_create_layers - Create and initialize all layers
1343 * @disp: Display controller
1345 * Return: 0 on success, or the DMA channel request error otherwise
1347 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp)
1349 static const struct zynqmp_disp_layer_info layer_info[] = {
1350 [ZYNQMP_DISP_LAYER_VID] = {
1351 .formats = avbuf_vid_fmts,
1352 .num_formats = ARRAY_SIZE(avbuf_vid_fmts),
1355 [ZYNQMP_DISP_LAYER_GFX] = {
1356 .formats = avbuf_gfx_fmts,
1357 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts),
1365 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
1366 struct zynqmp_disp_layer *layer = &disp->layers[i];
1370 layer->info = &layer_info[i];
1372 ret = zynqmp_disp_layer_request_dma(disp, layer);
1380 zynqmp_disp_destroy_layers(disp);
1384 /* -----------------------------------------------------------------------------
1385 * ZynqMP Display & DRM CRTC
1389 * zynqmp_disp_enable - Enable the display controller
1390 * @disp: Display controller
1392 static void zynqmp_disp_enable(struct zynqmp_disp *disp)
1394 zynqmp_disp_avbuf_enable(disp);
1395 /* Choose clock source based on the DT clock handle. */
1396 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->pclk_from_ps,
1397 disp->audio.clk_from_ps, true);
1398 zynqmp_disp_avbuf_enable_channels(disp);
1399 zynqmp_disp_avbuf_enable_audio(disp);
1401 zynqmp_disp_audio_enable(disp);
1405 * zynqmp_disp_disable - Disable the display controller
1406 * @disp: Display controller
1408 static void zynqmp_disp_disable(struct zynqmp_disp *disp)
1410 zynqmp_disp_audio_disable(disp);
1412 zynqmp_disp_avbuf_disable_audio(disp);
1413 zynqmp_disp_avbuf_disable_channels(disp);
1414 zynqmp_disp_avbuf_disable(disp);
1417 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc)
1419 return container_of(crtc, struct zynqmp_disp, crtc);
1422 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc,
1423 struct drm_display_mode *adjusted_mode)
1425 struct zynqmp_disp *disp = crtc_to_disp(crtc);
1426 unsigned long mode_clock = adjusted_mode->clock * 1000;
1431 ret = clk_set_rate(disp->pclk, mode_clock);
1433 dev_err(disp->dev, "failed to set a pixel clock\n");
1437 rate = clk_get_rate(disp->pclk);
1438 diff = rate - mode_clock;
1439 if (abs(diff) > mode_clock / 20)
1441 "requested pixel rate: %lu actual rate: %lu\n",
1445 "requested pixel rate: %lu actual rate: %lu\n",
1452 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
1453 struct drm_atomic_state *state)
1455 struct zynqmp_disp *disp = crtc_to_disp(crtc);
1456 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1459 pm_runtime_get_sync(disp->dev);
1461 zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
1463 ret = clk_prepare_enable(disp->pclk);
1465 dev_err(disp->dev, "failed to enable a pixel clock\n");
1466 pm_runtime_put_sync(disp->dev);
1470 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB);
1471 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0);
1473 zynqmp_disp_enable(disp);
1475 /* Delay of 3 vblank intervals for timing gen to be stable */
1476 vrefresh = (adjusted_mode->clock * 1000) /
1477 (adjusted_mode->vtotal * adjusted_mode->htotal);
1478 msleep(3 * 1000 / vrefresh);
1482 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc,
1483 struct drm_atomic_state *state)
1485 struct zynqmp_disp *disp = crtc_to_disp(crtc);
1486 struct drm_plane_state *old_plane_state;
1489 * Disable the plane if active. The old plane state can be NULL in the
1490 * .shutdown() path if the plane is already disabled, skip
1491 * zynqmp_disp_plane_atomic_disable() in that case.
1493 old_plane_state = drm_atomic_get_old_plane_state(state, crtc->primary);
1494 if (old_plane_state)
1495 zynqmp_disp_plane_atomic_disable(crtc->primary, state);
1497 zynqmp_disp_disable(disp);
1499 drm_crtc_vblank_off(&disp->crtc);
1501 spin_lock_irq(&crtc->dev->event_lock);
1502 if (crtc->state->event) {
1503 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1504 crtc->state->event = NULL;
1506 spin_unlock_irq(&crtc->dev->event_lock);
1508 clk_disable_unprepare(disp->pclk);
1509 pm_runtime_put_sync(disp->dev);
1512 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc,
1513 struct drm_atomic_state *state)
1515 return drm_atomic_add_affected_planes(state, crtc);
1519 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc,
1520 struct drm_atomic_state *state)
1522 drm_crtc_vblank_on(crtc);
1526 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc,
1527 struct drm_atomic_state *state)
1529 if (crtc->state->event) {
1530 struct drm_pending_vblank_event *event;
1532 /* Consume the flip_done event from atomic helper. */
1533 event = crtc->state->event;
1534 crtc->state->event = NULL;
1536 event->pipe = drm_crtc_index(crtc);
1538 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1540 spin_lock_irq(&crtc->dev->event_lock);
1541 drm_crtc_arm_vblank_event(crtc, event);
1542 spin_unlock_irq(&crtc->dev->event_lock);
1546 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = {
1547 .atomic_enable = zynqmp_disp_crtc_atomic_enable,
1548 .atomic_disable = zynqmp_disp_crtc_atomic_disable,
1549 .atomic_check = zynqmp_disp_crtc_atomic_check,
1550 .atomic_begin = zynqmp_disp_crtc_atomic_begin,
1551 .atomic_flush = zynqmp_disp_crtc_atomic_flush,
1554 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc)
1556 struct zynqmp_disp *disp = crtc_to_disp(crtc);
1558 zynqmp_dp_enable_vblank(disp->dpsub->dp);
1563 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc)
1565 struct zynqmp_disp *disp = crtc_to_disp(crtc);
1567 zynqmp_dp_disable_vblank(disp->dpsub->dp);
1570 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = {
1571 .destroy = drm_crtc_cleanup,
1572 .set_config = drm_atomic_helper_set_config,
1573 .page_flip = drm_atomic_helper_page_flip,
1574 .reset = drm_atomic_helper_crtc_reset,
1575 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1576 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1577 .enable_vblank = zynqmp_disp_crtc_enable_vblank,
1578 .disable_vblank = zynqmp_disp_crtc_disable_vblank,
1581 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp)
1583 struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane;
1586 ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane,
1587 NULL, &zynqmp_disp_crtc_funcs, NULL);
1591 drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs);
1593 /* Start with vertical blanking interrupt reporting disabled. */
1594 drm_crtc_vblank_off(&disp->crtc);
1599 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp)
1601 u32 possible_crtcs = drm_crtc_mask(&disp->crtc);
1604 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
1605 disp->layers[i].plane.possible_crtcs = possible_crtcs;
1608 /* -----------------------------------------------------------------------------
1609 * Initialization & Cleanup
1612 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub)
1614 struct zynqmp_disp *disp = dpsub->disp;
1617 ret = zynqmp_disp_create_planes(disp);
1621 ret = zynqmp_disp_create_crtc(disp);
1625 zynqmp_disp_map_crtc_to_plane(disp);
1630 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm)
1632 struct platform_device *pdev = to_platform_device(dpsub->dev);
1633 struct zynqmp_disp *disp;
1634 struct zynqmp_disp_layer *layer;
1635 struct resource *res;
1638 disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL);
1642 disp->dev = &pdev->dev;
1643 disp->dpsub = dpsub;
1648 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend");
1649 disp->blend.base = devm_ioremap_resource(disp->dev, res);
1650 if (IS_ERR(disp->blend.base))
1651 return PTR_ERR(disp->blend.base);
1653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf");
1654 disp->avbuf.base = devm_ioremap_resource(disp->dev, res);
1655 if (IS_ERR(disp->avbuf.base))
1656 return PTR_ERR(disp->avbuf.base);
1658 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud");
1659 disp->audio.base = devm_ioremap_resource(disp->dev, res);
1660 if (IS_ERR(disp->audio.base))
1661 return PTR_ERR(disp->audio.base);
1663 /* Try the live PL video clock */
1664 disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk");
1665 if (!IS_ERR(disp->pclk))
1666 disp->pclk_from_ps = false;
1667 else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER)
1668 return PTR_ERR(disp->pclk);
1670 /* If the live PL video clock is not valid, fall back to PS clock */
1671 if (IS_ERR_OR_NULL(disp->pclk)) {
1672 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in");
1673 if (IS_ERR(disp->pclk)) {
1674 dev_err(disp->dev, "failed to init any video clock\n");
1675 return PTR_ERR(disp->pclk);
1677 disp->pclk_from_ps = true;
1680 zynqmp_disp_audio_init(disp);
1682 ret = zynqmp_disp_create_layers(disp);
1686 layer = &disp->layers[ZYNQMP_DISP_LAYER_VID];
1687 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align;
1692 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub)
1694 struct zynqmp_disp *disp = dpsub->disp;
1696 zynqmp_disp_destroy_layers(disp);