1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022 Intel Corporation
6 #include "xe_guc_hwconfig.h"
8 #include <drm/drm_managed.h>
10 #include "abi/guc_actions_abi.h"
12 #include "xe_device.h"
17 static int send_get_hwconfig(struct xe_guc *guc, u32 ggtt_addr, u32 size)
20 XE_GUC_ACTION_GET_HWCONFIG,
21 lower_32_bits(ggtt_addr),
22 upper_32_bits(ggtt_addr),
26 return xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
29 static int guc_hwconfig_size(struct xe_guc *guc, u32 *size)
31 int ret = send_get_hwconfig(guc, 0, 0);
40 static int guc_hwconfig_copy(struct xe_guc *guc)
42 int ret = send_get_hwconfig(guc, xe_bo_ggtt_addr(guc->hwconfig.bo),
51 int xe_guc_hwconfig_init(struct xe_guc *guc)
53 struct xe_device *xe = guc_to_xe(guc);
54 struct xe_gt *gt = guc_to_gt(guc);
55 struct xe_tile *tile = gt_to_tile(gt);
60 /* Initialization already done */
65 * All hwconfig the same across GTs so only GT0 needs to be configured
67 if (gt->info.id != XE_GT0)
70 /* ADL_P, DG2+ supports hwconfig table */
71 if (GRAPHICS_VERx100(xe) < 1255 && xe->info.platform != XE_ALDERLAKE_P)
74 err = guc_hwconfig_size(guc, &size);
80 bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
81 XE_BO_CREATE_SYSTEM_BIT |
82 XE_BO_CREATE_GGTT_BIT);
85 guc->hwconfig.bo = bo;
86 guc->hwconfig.size = size;
88 return guc_hwconfig_copy(guc);
91 u32 xe_guc_hwconfig_size(struct xe_guc *guc)
93 return !guc->hwconfig.bo ? 0 : guc->hwconfig.size;
96 void xe_guc_hwconfig_copy(struct xe_guc *guc, void *dst)
98 struct xe_device *xe = guc_to_xe(guc);
100 XE_WARN_ON(!guc->hwconfig.bo);
102 xe_map_memcpy_from(xe, dst, &guc->hwconfig.bo->vmap, 0,