1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2023 Intel Corporation
6 #ifndef _XE_INSTR_DEFS_H_
7 #define _XE_INSTR_DEFS_H_
9 #include "regs/xe_reg_defs.h"
12 * The first dword of any GPU instruction is the "instruction header." Bits
13 * 31:29 identify the general type of the command and determine how exact
14 * opcodes and sub-opcodes will be encoded in the remaining bits.
16 #define XE_INSTR_CMD_TYPE GENMASK(31, 29)
17 #define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
18 #define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
19 #define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
22 * Most (but not all) instructions have a "length" field in the instruction
23 * header. The value expected is the total number of dwords for the
24 * instruction, minus two.
26 * Some instructions have length fields longer or shorter than 8 bits, but
27 * those are rare. This definition can be used for the common case where
28 * the length field is from 7:0.
30 #define XE_INSTR_LEN_MASK GENMASK(7, 0)
31 #define XE_INSTR_NUM_DW(x) REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2)