1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2023 Intel Corporation
6 #ifndef _XE_GSC_COMMANDS_H_
7 #define _XE_GSC_COMMANDS_H_
9 #include "instructions/xe_instr_defs.h"
12 * All GSCCS-specific commands have fixed length, so we can include it in the
13 * defines. Note that the generic GSC command header structure includes an
14 * optional data field in bits 9-21, but there are no commands that actually use
15 * it; some of the commands are instead defined as having an extended length
16 * field spanning bits 0-15, even if the extra bits are not required because the
17 * longest GSCCS command is only 8 dwords. To handle this, the defines below use
18 * a single field for both data and len. If we ever get a commands that does
19 * actually have data and this approach doesn't work for it we can re-work it
23 #define GSC_OPCODE REG_GENMASK(28, 22)
24 #define GSC_CMD_DATA_AND_LEN REG_GENMASK(21, 0)
26 #define __GSC_INSTR(op, dl) \
28 REG_FIELD_PREP(GSC_OPCODE, op) | \
29 REG_FIELD_PREP(GSC_CMD_DATA_AND_LEN, dl))
31 #define GSC_HECI_CMD_PKT __GSC_INSTR(0, 6)
33 #define GSC_FW_LOAD __GSC_INSTR(1, 2)
34 #define GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)