drivers/gpu/drm/virtio/virtgpu_ioctl.c

   1 /*
   2  * Copyright (C) 2015 Red Hat, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Authors:
   6  *    Dave Airlie
   7  *    Alon Levy
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/virtgpu_drm.h>
  30 #include <drm/ttm/ttm_execbuf_util.h>
  31
  32 #include "virtgpu_drv.h"
  33
  34 static void convert_to_hw_box(struct virtio_gpu_box *dst,
  35                               const struct drm_virtgpu_3d_box *src)
  36 {
  37         dst->x = cpu_to_le32(src->x);
  38         dst->y = cpu_to_le32(src->y);
  39         dst->z = cpu_to_le32(src->z);
  40         dst->w = cpu_to_le32(src->w);
  41         dst->h = cpu_to_le32(src->h);
  42         dst->d = cpu_to_le32(src->d);
  43 }
  44
  45 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
  46                                 struct drm_file *file_priv)
  47 {
  48         struct virtio_gpu_device *vgdev = dev->dev_private;
  49         struct drm_virtgpu_map *virtio_gpu_map = data;
  50
  51         return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
  52                                          virtio_gpu_map->handle,
  53                                          &virtio_gpu_map->offset);
  54 }
  55
  56 static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
  57                                            struct list_head *head)
  58 {
  59         struct ttm_operation_ctx ctx = { false, false };
  60         struct ttm_validate_buffer *buf;
  61         struct ttm_buffer_object *bo;
  62         struct virtio_gpu_object *qobj;
  63         int ret;
  64
  65         ret = ttm_eu_reserve_buffers(ticket, head, true, NULL);
  66         if (ret != 0)
  67                 return ret;
  68
  69         list_for_each_entry(buf, head, head) {
  70                 bo = buf->bo;
  71                 qobj = container_of(bo, struct virtio_gpu_object, tbo);
  72                 ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
  73                 if (ret) {
  74                         ttm_eu_backoff_reservation(ticket, head);
  75                         return ret;
  76                 }
  77         }
  78         return 0;
  79 }
  80
  81 static void virtio_gpu_unref_list(struct list_head *head)
  82 {
  83         struct ttm_validate_buffer *buf;
  84         struct ttm_buffer_object *bo;
  85         struct virtio_gpu_object *qobj;
  86
  87         list_for_each_entry(buf, head, head) {
  88                 bo = buf->bo;
  89                 qobj = container_of(bo, struct virtio_gpu_object, tbo);
  90
  91                 drm_gem_object_put_unlocked(&qobj->gem_base);
  92         }
  93 }
  94
  95 /*
  96  * Usage of execbuffer:
  97  * Relocations need to take into account the full VIRTIO_GPUDrawable size.
  98  * However, the command as passed from user space must *not* contain the initial
  99  * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
 100  */
 101 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
 102                                  struct drm_file *drm_file)
 103 {
 104         struct drm_virtgpu_execbuffer *exbuf = data;
 105         struct virtio_gpu_device *vgdev = dev->dev_private;
 106         struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
 107         struct drm_gem_object *gobj;
 108         struct virtio_gpu_fence *fence;
 109         struct virtio_gpu_object *qobj;
 110         int ret;
 111         uint32_t *bo_handles = NULL;
 112         void __user *user_bo_handles = NULL;
 113         struct list_head validate_list;
 114         struct ttm_validate_buffer *buflist = NULL;
 115         int i;
 116         struct ww_acquire_ctx ticket;
 117         void *buf;
 118
 119         if (vgdev->has_virgl_3d == false)
 120                 return -ENOSYS;
 121
 122         INIT_LIST_HEAD(&validate_list);
 123         if (exbuf->num_bo_handles) {
 124
 125                 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
 126                                            sizeof(uint32_t), GFP_KERNEL);
 127                 buflist = kvmalloc_array(exbuf->num_bo_handles,
 128                                            sizeof(struct ttm_validate_buffer),
 129                                            GFP_KERNEL | __GFP_ZERO);
 130                 if (!bo_handles || !buflist) {
 131                         kvfree(bo_handles);
 132                         kvfree(buflist);
 133                         return -ENOMEM;
 134                 }
 135
 136                 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles;
 137                 if (copy_from_user(bo_handles, user_bo_handles,
 138                                    exbuf->num_bo_handles * sizeof(uint32_t))) {
 139                         ret = -EFAULT;
 140                         kvfree(bo_handles);
 141                         kvfree(buflist);
 142                         return ret;
 143                 }
 144
 145                 for (i = 0; i < exbuf->num_bo_handles; i++) {
 146                         gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
 147                         if (!gobj) {
 148                                 kvfree(bo_handles);
 149                                 kvfree(buflist);
 150                                 return -ENOENT;
 151                         }
 152
 153                         qobj = gem_to_virtio_gpu_obj(gobj);
 154                         buflist[i].bo = &qobj->tbo;
 155
 156                         list_add(&buflist[i].head, &validate_list);
 157                 }
 158                 kvfree(bo_handles);
 159         }
 160
 161         ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
 162         if (ret)
 163                 goto out_free;
 164
 165         buf = memdup_user((void __user *)(uintptr_t)exbuf->command,
 166                           exbuf->size);
 167         if (IS_ERR(buf)) {
 168                 ret = PTR_ERR(buf);
 169                 goto out_unresv;
 170         }
 171
 172         fence = virtio_gpu_fence_alloc(vgdev);
 173         if (!fence) {
 174                 kfree(buf);
 175                 ret = -ENOMEM;
 176                 goto out_unresv;
 177         }
 178         virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
 179                               vfpriv->ctx_id, &fence);
 180
 181         ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
 182
 183         /* fence the command bo */
 184         virtio_gpu_unref_list(&validate_list);
 185         kvfree(buflist);
 186         dma_fence_put(&fence->f);
 187         return 0;
 188
 189 out_unresv:
 190         ttm_eu_backoff_reservation(&ticket, &validate_list);
 191 out_free:
 192         virtio_gpu_unref_list(&validate_list);
 193         kvfree(buflist);
 194         return ret;
 195 }
 196
 197 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
 198                                      struct drm_file *file_priv)
 199 {
 200         struct virtio_gpu_device *vgdev = dev->dev_private;
 201         struct drm_virtgpu_getparam *param = data;
 202         int value;
 203
 204         switch (param->param) {
 205         case VIRTGPU_PARAM_3D_FEATURES:
 206                 value = vgdev->has_virgl_3d == true ? 1 : 0;
 207                 break;
 208         case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
 209                 value = 1;
 210                 break;
 211         default:
 212                 return -EINVAL;
 213         }
 214         if (copy_to_user((void __user *)(unsigned long)param->value,
 215                          &value, sizeof(int))) {
 216                 return -EFAULT;
 217         }
 218         return 0;
 219 }
 220
 221 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
 222                                             struct drm_file *file_priv)
 223 {
 224         struct virtio_gpu_device *vgdev = dev->dev_private;
 225         struct drm_virtgpu_resource_create *rc = data;
 226         int ret;
 227         struct virtio_gpu_object *qobj;
 228         struct drm_gem_object *obj;
 229         uint32_t handle = 0;
 230         uint32_t size;
 231         struct list_head validate_list;
 232         struct ttm_validate_buffer mainbuf;
 233         struct virtio_gpu_fence *fence = NULL;
 234         struct ww_acquire_ctx ticket;
 235         struct virtio_gpu_resource_create_3d rc_3d;
 236
 237         if (vgdev->has_virgl_3d == false) {
 238                 if (rc->depth > 1)
 239                         return -EINVAL;
 240                 if (rc->nr_samples > 1)
 241                         return -EINVAL;
 242                 if (rc->last_level > 1)
 243                         return -EINVAL;
 244                 if (rc->target != 2)
 245                         return -EINVAL;
 246                 if (rc->array_size > 1)
 247                         return -EINVAL;
 248         }
 249
 250         INIT_LIST_HEAD(&validate_list);
 251         memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
 252
 253         size = rc->size;
 254
 255         /* allocate a single page size object */
 256         if (size == 0)
 257                 size = PAGE_SIZE;
 258
 259         qobj = virtio_gpu_alloc_object(dev, size, false, false);
 260         if (IS_ERR(qobj))
 261                 return PTR_ERR(qobj);
 262         obj = &qobj->gem_base;
 263
 264         if (!vgdev->has_virgl_3d) {
 265                 virtio_gpu_cmd_create_resource(vgdev, qobj, rc->format,
 266                                                rc->width, rc->height);
 267
 268                 ret = virtio_gpu_object_attach(vgdev, qobj, NULL);
 269         } else {
 270                 /* use a gem reference since unref list undoes them */
 271                 drm_gem_object_get(&qobj->gem_base);
 272                 mainbuf.bo = &qobj->tbo;
 273                 list_add(&mainbuf.head, &validate_list);
 274
 275                 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
 276                 if (ret) {
 277                         DRM_DEBUG("failed to validate\n");
 278                         goto fail_unref;
 279                 }
 280
 281                 rc_3d.resource_id = cpu_to_le32(qobj->hw_res_handle);
 282                 rc_3d.target = cpu_to_le32(rc->target);
 283                 rc_3d.format = cpu_to_le32(rc->format);
 284                 rc_3d.bind = cpu_to_le32(rc->bind);
 285                 rc_3d.width = cpu_to_le32(rc->width);
 286                 rc_3d.height = cpu_to_le32(rc->height);
 287                 rc_3d.depth = cpu_to_le32(rc->depth);
 288                 rc_3d.array_size = cpu_to_le32(rc->array_size);
 289                 rc_3d.last_level = cpu_to_le32(rc->last_level);
 290                 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples);
 291                 rc_3d.flags = cpu_to_le32(rc->flags);
 292
 293                 fence = virtio_gpu_fence_alloc(vgdev);
 294                 if (!fence) {
 295                         ret = -ENOMEM;
 296                         goto fail_backoff;
 297                 }
 298
 299                 virtio_gpu_cmd_resource_create_3d(vgdev, qobj, &rc_3d, NULL);
 300                 ret = virtio_gpu_object_attach(vgdev, qobj, &fence);
 301                 if (ret) {
 302                         virtio_gpu_fence_cleanup(fence);
 303                         goto fail_backoff;
 304                 }
 305                 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
 306         }
 307
 308         ret = drm_gem_handle_create(file_priv, obj, &handle);
 309         if (ret) {
 310
 311                 drm_gem_object_release(obj);
 312                 if (vgdev->has_virgl_3d) {
 313                         virtio_gpu_unref_list(&validate_list);
 314                         dma_fence_put(&fence->f);
 315                 }
 316                 return ret;
 317         }
 318         drm_gem_object_put_unlocked(obj);
 319
 320         rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
 321         rc->bo_handle = handle;
 322
 323         if (vgdev->has_virgl_3d) {
 324                 virtio_gpu_unref_list(&validate_list);
 325                 dma_fence_put(&fence->f);
 326         }
 327         return 0;
 328 fail_backoff:
 329         ttm_eu_backoff_reservation(&ticket, &validate_list);
 330 fail_unref:
 331         if (vgdev->has_virgl_3d) {
 332                 virtio_gpu_unref_list(&validate_list);
 333                 dma_fence_put(&fence->f);
 334         }
 335 //fail_obj:
 336 //      drm_gem_object_handle_unreference_unlocked(obj);
 337         return ret;
 338 }
 339
 340 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
 341                                           struct drm_file *file_priv)
 342 {
 343         struct drm_virtgpu_resource_info *ri = data;
 344         struct drm_gem_object *gobj = NULL;
 345         struct virtio_gpu_object *qobj = NULL;
 346
 347         gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
 348         if (gobj == NULL)
 349                 return -ENOENT;
 350
 351         qobj = gem_to_virtio_gpu_obj(gobj);
 352
 353         ri->size = qobj->gem_base.size;
 354         ri->res_handle = qobj->hw_res_handle;
 355         drm_gem_object_put_unlocked(gobj);
 356         return 0;
 357 }
 358
 359 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
 360                                                void *data,
 361                                                struct drm_file *file)
 362 {
 363         struct virtio_gpu_device *vgdev = dev->dev_private;
 364         struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
 365         struct drm_virtgpu_3d_transfer_from_host *args = data;
 366         struct ttm_operation_ctx ctx = { true, false };
 367         struct drm_gem_object *gobj = NULL;
 368         struct virtio_gpu_object *qobj = NULL;
 369         struct virtio_gpu_fence *fence;
 370         int ret;
 371         u32 offset = args->offset;
 372         struct virtio_gpu_box box;
 373
 374         if (vgdev->has_virgl_3d == false)
 375                 return -ENOSYS;
 376
 377         gobj = drm_gem_object_lookup(file, args->bo_handle);
 378         if (gobj == NULL)
 379                 return -ENOENT;
 380
 381         qobj = gem_to_virtio_gpu_obj(gobj);
 382
 383         ret = virtio_gpu_object_reserve(qobj, false);
 384         if (ret)
 385                 goto out;
 386
 387         ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
 388         if (unlikely(ret))
 389                 goto out_unres;
 390
 391         convert_to_hw_box(&box, &args->box);
 392
 393         fence = virtio_gpu_fence_alloc(vgdev);
 394         if (!fence) {
 395                 ret = -ENOMEM;
 396                 goto out_unres;
 397         }
 398         virtio_gpu_cmd_transfer_from_host_3d
 399                 (vgdev, qobj->hw_res_handle,
 400                  vfpriv->ctx_id, offset, args->level,
 401                  &box, &fence);
 402         reservation_object_add_excl_fence(qobj->tbo.resv,
 403                                           &fence->f);
 404
 405         dma_fence_put(&fence->f);
 406 out_unres:
 407         virtio_gpu_object_unreserve(qobj);
 408 out:
 409         drm_gem_object_put_unlocked(gobj);
 410         return ret;
 411 }
 412
 413 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
 414                                              struct drm_file *file)
 415 {
 416         struct virtio_gpu_device *vgdev = dev->dev_private;
 417         struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
 418         struct drm_virtgpu_3d_transfer_to_host *args = data;
 419         struct ttm_operation_ctx ctx = { true, false };
 420         struct drm_gem_object *gobj = NULL;
 421         struct virtio_gpu_object *qobj = NULL;
 422         struct virtio_gpu_fence *fence;
 423         struct virtio_gpu_box box;
 424         int ret;
 425         u32 offset = args->offset;
 426
 427         gobj = drm_gem_object_lookup(file, args->bo_handle);
 428         if (gobj == NULL)
 429                 return -ENOENT;
 430
 431         qobj = gem_to_virtio_gpu_obj(gobj);
 432
 433         ret = virtio_gpu_object_reserve(qobj, false);
 434         if (ret)
 435                 goto out;
 436
 437         ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
 438         if (unlikely(ret))
 439                 goto out_unres;
 440
 441         convert_to_hw_box(&box, &args->box);
 442         if (!vgdev->has_virgl_3d) {
 443                 virtio_gpu_cmd_transfer_to_host_2d
 444                         (vgdev, qobj, offset,
 445                          box.w, box.h, box.x, box.y, NULL);
 446         } else {
 447                 fence = virtio_gpu_fence_alloc(vgdev);
 448                 if (!fence) {
 449                         ret = -ENOMEM;
 450                         goto out_unres;
 451                 }
 452                 virtio_gpu_cmd_transfer_to_host_3d
 453                         (vgdev, qobj,
 454                          vfpriv ? vfpriv->ctx_id : 0, offset,
 455                          args->level, &box, &fence);
 456                 reservation_object_add_excl_fence(qobj->tbo.resv,
 457                                                   &fence->f);
 458                 dma_fence_put(&fence->f);
 459         }
 460
 461 out_unres:
 462         virtio_gpu_object_unreserve(qobj);
 463 out:
 464         drm_gem_object_put_unlocked(gobj);
 465         return ret;
 466 }
 467
 468 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
 469                             struct drm_file *file)
 470 {
 471         struct drm_virtgpu_3d_wait *args = data;
 472         struct drm_gem_object *gobj = NULL;
 473         struct virtio_gpu_object *qobj = NULL;
 474         int ret;
 475         bool nowait = false;
 476
 477         gobj = drm_gem_object_lookup(file, args->handle);
 478         if (gobj == NULL)
 479                 return -ENOENT;
 480
 481         qobj = gem_to_virtio_gpu_obj(gobj);
 482
 483         if (args->flags & VIRTGPU_WAIT_NOWAIT)
 484                 nowait = true;
 485         ret = virtio_gpu_object_wait(qobj, nowait);
 486
 487         drm_gem_object_put_unlocked(gobj);
 488         return ret;
 489 }
 490
 491 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
 492                                 void *data, struct drm_file *file)
 493 {
 494         struct virtio_gpu_device *vgdev = dev->dev_private;
 495         struct drm_virtgpu_get_caps *args = data;
 496         unsigned size, host_caps_size;
 497         int i;
 498         int found_valid = -1;
 499         int ret;
 500         struct virtio_gpu_drv_cap_cache *cache_ent;
 501         void *ptr;
 502
 503         if (vgdev->num_capsets == 0)
 504                 return -ENOSYS;
 505
 506         /* don't allow userspace to pass 0 */
 507         if (args->size == 0)
 508                 return -EINVAL;
 509
 510         spin_lock(&vgdev->display_info_lock);
 511         for (i = 0; i < vgdev->num_capsets; i++) {
 512                 if (vgdev->capsets[i].id == args->cap_set_id) {
 513                         if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
 514                                 found_valid = i;
 515                                 break;
 516                         }
 517                 }
 518         }
 519
 520         if (found_valid == -1) {
 521                 spin_unlock(&vgdev->display_info_lock);
 522                 return -EINVAL;
 523         }
 524
 525         host_caps_size = vgdev->capsets[found_valid].max_size;
 526         /* only copy to user the minimum of the host caps size or the guest caps size */
 527         size = min(args->size, host_caps_size);
 528
 529         list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
 530                 if (cache_ent->id == args->cap_set_id &&
 531                     cache_ent->version == args->cap_set_ver) {
 532                         ptr = cache_ent->caps_cache;
 533                         spin_unlock(&vgdev->display_info_lock);
 534                         goto copy_exit;
 535                 }
 536         }
 537         spin_unlock(&vgdev->display_info_lock);
 538
 539         /* not in cache - need to talk to hw */
 540         virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
 541                                   &cache_ent);
 542
 543         ret = wait_event_timeout(vgdev->resp_wq,
 544                                  atomic_read(&cache_ent->is_valid), 5 * HZ);
 545         if (!ret)
 546                 return -EBUSY;
 547
 548         ptr = cache_ent->caps_cache;
 549
 550 copy_exit:
 551         if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size))
 552                 return -EFAULT;
 553
 554         return 0;
 555 }
 556
 557 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
 558         DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
 559                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 560
 561         DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
 562                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 563
 564         DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
 565                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 566
 567         DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
 568                           virtio_gpu_resource_create_ioctl,
 569                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 570
 571         DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
 572                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 573
 574         /* make transfer async to the main ring? - no sure, can we
 575          * thread these in the underlying GL
 576          */
 577         DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
 578                           virtio_gpu_transfer_from_host_ioctl,
 579                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 580         DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
 581                           virtio_gpu_transfer_to_host_ioctl,
 582                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 583
 584         DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
 585                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 586
 587         DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
 588                           DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
 589 };