drivers/gpu/drm/vc4/vc4_plane.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 plane module
  11  *
  12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  13  *
  14  * At atomic modeset check time, we compute the HVS display element
  15  * state that would be necessary for displaying the plane (giving us a
  16  * chance to figure out if a plane configuration is invalid), then at
  17  * atomic flush time the CRTC will ask us to write our element state
  18  * into the region of the HVS that it has allocated for us.
  19  */
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "uapi/drm/vc4_drm.h"
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 static const struct hvs_format {
  31         u32 drm; /* DRM_FORMAT_* */
  32         u32 hvs; /* HVS_FORMAT_* */
  33         u32 pixel_order;
  34 } hvs_formats[] = {
  35         {
  36                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  37                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  38         },
  39         {
  40                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  41                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  42         },
  43         {
  44                 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  45                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  46         },
  47         {
  48                 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  49                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  50         },
  51         {
  52                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  53                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  54         },
  55         {
  56                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  57                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  58         },
  59         {
  60                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  61                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  62         },
  63         {
  64                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  65                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  66         },
  67         {
  68                 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  69                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  70         },
  71         {
  72                 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  73                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  74         },
  75         {
  76                 .drm = DRM_FORMAT_YUV422,
  77                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  78                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  79         },
  80         {
  81                 .drm = DRM_FORMAT_YVU422,
  82                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  83                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  84         },
  85         {
  86                 .drm = DRM_FORMAT_YUV420,
  87                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  88                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  89         },
  90         {
  91                 .drm = DRM_FORMAT_YVU420,
  92                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  93                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  94         },
  95         {
  96                 .drm = DRM_FORMAT_NV12,
  97                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  98                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  99         },
 100         {
 101                 .drm = DRM_FORMAT_NV21,
 102                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 103                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 104         },
 105         {
 106                 .drm = DRM_FORMAT_NV16,
 107                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 108                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 109         },
 110         {
 111                 .drm = DRM_FORMAT_NV61,
 112                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 113                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 114         },
 115 };
 116
 117 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 118 {
 119         unsigned i;
 120
 121         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 122                 if (hvs_formats[i].drm == drm_format)
 123                         return &hvs_formats[i];
 124         }
 125
 126         return NULL;
 127 }
 128
 129 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 130 {
 131         if (dst > src)
 132                 return VC4_SCALING_PPF;
 133         else if (dst < src)
 134                 return VC4_SCALING_TPZ;
 135         else
 136                 return VC4_SCALING_NONE;
 137 }
 138
 139 static bool plane_enabled(struct drm_plane_state *state)
 140 {
 141         return state->fb && state->crtc;
 142 }
 143
 144 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 145 {
 146         struct vc4_plane_state *vc4_state;
 147
 148         if (WARN_ON(!plane->state))
 149                 return NULL;
 150
 151         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 152         if (!vc4_state)
 153                 return NULL;
 154
 155         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 156
 157         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 158
 159         if (vc4_state->dlist) {
 160                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 161                                            vc4_state->dlist_count * 4,
 162                                            GFP_KERNEL);
 163                 if (!vc4_state->dlist) {
 164                         kfree(vc4_state);
 165                         return NULL;
 166                 }
 167                 vc4_state->dlist_size = vc4_state->dlist_count;
 168         }
 169
 170         return &vc4_state->base;
 171 }
 172
 173 static void vc4_plane_destroy_state(struct drm_plane *plane,
 174                                     struct drm_plane_state *state)
 175 {
 176         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 177         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 178
 179         if (vc4_state->lbm.allocated) {
 180                 unsigned long irqflags;
 181
 182                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 183                 drm_mm_remove_node(&vc4_state->lbm);
 184                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 185         }
 186
 187         kfree(vc4_state->dlist);
 188         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 189         kfree(state);
 190 }
 191
 192 /* Called during init to allocate the plane's atomic state. */
 193 static void vc4_plane_reset(struct drm_plane *plane)
 194 {
 195         struct vc4_plane_state *vc4_state;
 196
 197         WARN_ON(plane->state);
 198
 199         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 200         if (!vc4_state)
 201                 return;
 202
 203         __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
 204 }
 205
 206 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 207 {
 208         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 209                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 210                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 211
 212                 if (!new_dlist)
 213                         return;
 214                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 215
 216                 kfree(vc4_state->dlist);
 217                 vc4_state->dlist = new_dlist;
 218                 vc4_state->dlist_size = new_size;
 219         }
 220
 221         vc4_state->dlist[vc4_state->dlist_count++] = val;
 222 }
 223
 224 /* Returns the scl0/scl1 field based on whether the dimensions need to
 225  * be up/down/non-scaled.
 226  *
 227  * This is a replication of a table from the spec.
 228  */
 229 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 230 {
 231         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 232
 233         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 234         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 235                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 236         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 237                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 238         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 239                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 240         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 241                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 242         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 243                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 244         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 245                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 246         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 247                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 248         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 249                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 250         default:
 251         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 252                 /* The unity case is independently handled by
 253                  * SCALER_CTL0_UNITY.
 254                  */
 255                 return 0;
 256         }
 257 }
 258
 259 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 260 {
 261         struct drm_plane *plane = state->plane;
 262         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 263         struct drm_framebuffer *fb = state->fb;
 264         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 265         u32 subpixel_src_mask = (1 << 16) - 1;
 266         u32 format = fb->format->format;
 267         int num_planes = fb->format->num_planes;
 268         u32 h_subsample = 1;
 269         u32 v_subsample = 1;
 270         int i;
 271
 272         for (i = 0; i < num_planes; i++)
 273                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 274
 275         /* We don't support subpixel source positioning for scaling. */
 276         if ((state->src_x & subpixel_src_mask) ||
 277             (state->src_y & subpixel_src_mask) ||
 278             (state->src_w & subpixel_src_mask) ||
 279             (state->src_h & subpixel_src_mask)) {
 280                 return -EINVAL;
 281         }
 282
 283         vc4_state->src_x = state->src_x >> 16;
 284         vc4_state->src_y = state->src_y >> 16;
 285         vc4_state->src_w[0] = state->src_w >> 16;
 286         vc4_state->src_h[0] = state->src_h >> 16;
 287
 288         vc4_state->crtc_x = state->crtc_x;
 289         vc4_state->crtc_y = state->crtc_y;
 290         vc4_state->crtc_w = state->crtc_w;
 291         vc4_state->crtc_h = state->crtc_h;
 292
 293         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 294                                                        vc4_state->crtc_w);
 295         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 296                                                        vc4_state->crtc_h);
 297
 298         if (num_planes > 1) {
 299                 vc4_state->is_yuv = true;
 300
 301                 h_subsample = drm_format_horz_chroma_subsampling(format);
 302                 v_subsample = drm_format_vert_chroma_subsampling(format);
 303                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 304                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 305
 306                 vc4_state->x_scaling[1] =
 307                         vc4_get_scaling_mode(vc4_state->src_w[1],
 308                                              vc4_state->crtc_w);
 309                 vc4_state->y_scaling[1] =
 310                         vc4_get_scaling_mode(vc4_state->src_h[1],
 311                                              vc4_state->crtc_h);
 312
 313                 /* YUV conversion requires that scaling be enabled,
 314                  * even on a plane that's otherwise 1:1.  Choose TPZ
 315                  * for simplicity.
 316                  */
 317                 if (vc4_state->x_scaling[0] == VC4_SCALING_NONE)
 318                         vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
 319                 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
 320                         vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
 321         } else {
 322                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 323                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 324         }
 325
 326         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 327                                vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
 328                                vc4_state->x_scaling[1] == VC4_SCALING_NONE &&
 329                                vc4_state->y_scaling[1] == VC4_SCALING_NONE);
 330
 331         /* No configuring scaling on the cursor plane, since it gets
 332            non-vblank-synced updates, and scaling requires requires
 333            LBM changes which have to be vblank-synced.
 334          */
 335         if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
 336                 return -EINVAL;
 337
 338         /* Clamp the on-screen start x/y to 0.  The hardware doesn't
 339          * support negative y, and negative x wastes bandwidth.
 340          */
 341         if (vc4_state->crtc_x < 0) {
 342                 for (i = 0; i < num_planes; i++) {
 343                         u32 cpp = fb->format->cpp[i];
 344                         u32 subs = ((i == 0) ? 1 : h_subsample);
 345
 346                         vc4_state->offsets[i] += (cpp *
 347                                                   (-vc4_state->crtc_x) / subs);
 348                 }
 349                 vc4_state->src_w[0] += vc4_state->crtc_x;
 350                 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
 351                 vc4_state->crtc_x = 0;
 352         }
 353
 354         if (vc4_state->crtc_y < 0) {
 355                 for (i = 0; i < num_planes; i++) {
 356                         u32 subs = ((i == 0) ? 1 : v_subsample);
 357
 358                         vc4_state->offsets[i] += (fb->pitches[i] *
 359                                                   (-vc4_state->crtc_y) / subs);
 360                 }
 361                 vc4_state->src_h[0] += vc4_state->crtc_y;
 362                 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
 363                 vc4_state->crtc_y = 0;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 370 {
 371         u32 scale, recip;
 372
 373         scale = (1 << 16) * src / dst;
 374
 375         /* The specs note that while the reciprocal would be defined
 376          * as (1<<32)/scale, ~0 is close enough.
 377          */
 378         recip = ~0 / scale;
 379
 380         vc4_dlist_write(vc4_state,
 381                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 382                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 383         vc4_dlist_write(vc4_state,
 384                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 385 }
 386
 387 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 388 {
 389         u32 scale = (1 << 16) * src / dst;
 390
 391         vc4_dlist_write(vc4_state,
 392                         SCALER_PPF_AGC |
 393                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 394                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 395 }
 396
 397 static u32 vc4_lbm_size(struct drm_plane_state *state)
 398 {
 399         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 400         /* This is the worst case number.  One of the two sizes will
 401          * be used depending on the scaling configuration.
 402          */
 403         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 404         u32 lbm;
 405
 406         if (!vc4_state->is_yuv) {
 407                 if (vc4_state->is_unity)
 408                         return 0;
 409                 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 410                         lbm = pix_per_line * 8;
 411                 else {
 412                         /* In special cases, this multiplier might be 12. */
 413                         lbm = pix_per_line * 16;
 414                 }
 415         } else {
 416                 /* There are cases for this going down to a multiplier
 417                  * of 2, but according to the firmware source, the
 418                  * table in the docs is somewhat wrong.
 419                  */
 420                 lbm = pix_per_line * 16;
 421         }
 422
 423         lbm = roundup(lbm, 32);
 424
 425         return lbm;
 426 }
 427
 428 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 429                                          int channel)
 430 {
 431         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 432
 433         /* Ch0 H-PPF Word 0: Scaling Parameters */
 434         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 435                 vc4_write_ppf(vc4_state,
 436                               vc4_state->src_w[channel], vc4_state->crtc_w);
 437         }
 438
 439         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 440         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 441                 vc4_write_ppf(vc4_state,
 442                               vc4_state->src_h[channel], vc4_state->crtc_h);
 443                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 444         }
 445
 446         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 447         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 448                 vc4_write_tpz(vc4_state,
 449                               vc4_state->src_w[channel], vc4_state->crtc_w);
 450         }
 451
 452         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 453         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 454                 vc4_write_tpz(vc4_state,
 455                               vc4_state->src_h[channel], vc4_state->crtc_h);
 456                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 457         }
 458 }
 459
 460 /* Writes out a full display list for an active plane to the plane's
 461  * private dlist state.
 462  */
 463 static int vc4_plane_mode_set(struct drm_plane *plane,
 464                               struct drm_plane_state *state)
 465 {
 466         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 467         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 468         struct drm_framebuffer *fb = state->fb;
 469         u32 ctl0_offset = vc4_state->dlist_count;
 470         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 471         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 472         int num_planes = drm_format_num_planes(format->drm);
 473         bool mix_plane_alpha;
 474         bool covers_screen;
 475         u32 scl0, scl1, pitch0;
 476         u32 lbm_size, tiling;
 477         unsigned long irqflags;
 478         u32 hvs_format = format->hvs;
 479         int ret, i;
 480
 481         ret = vc4_plane_setup_clipping_and_scaling(state);
 482         if (ret)
 483                 return ret;
 484
 485         /* Allocate the LBM memory that the HVS will use for temporary
 486          * storage due to our scaling/format conversion.
 487          */
 488         lbm_size = vc4_lbm_size(state);
 489         if (lbm_size) {
 490                 if (!vc4_state->lbm.allocated) {
 491                         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 492                         ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 493                                                          &vc4_state->lbm,
 494                                                          lbm_size, 32, 0, 0);
 495                         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 496                 } else {
 497                         WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 498                 }
 499         }
 500
 501         if (ret)
 502                 return ret;
 503
 504         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 505          * and 4:4:4, scl1 should be set to scl0 so both channels of
 506          * the scaler do the same thing.  For YUV, the Y plane needs
 507          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 508          * the scl fields here.
 509          */
 510         if (num_planes == 1) {
 511                 scl0 = vc4_get_scl_field(state, 0);
 512                 scl1 = scl0;
 513         } else {
 514                 scl0 = vc4_get_scl_field(state, 1);
 515                 scl1 = vc4_get_scl_field(state, 0);
 516         }
 517
 518         switch (base_format_mod) {
 519         case DRM_FORMAT_MOD_LINEAR:
 520                 tiling = SCALER_CTL0_TILING_LINEAR;
 521                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 522                 break;
 523
 524         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 525                 /* For T-tiled, the FB pitch is "how many bytes from
 526                  * one row to the next, such that pitch * tile_h ==
 527                  * tile_size * tiles_per_row."
 528                  */
 529                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 530                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 531                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 532
 533                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 534
 535                 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
 536                           VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
 537                           VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
 538                 break;
 539         }
 540
 541         case DRM_FORMAT_MOD_BROADCOM_SAND64:
 542         case DRM_FORMAT_MOD_BROADCOM_SAND128:
 543         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 544                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
 545
 546                 /* Column-based NV12 or RGBA.
 547                  */
 548                 if (fb->format->num_planes > 1) {
 549                         if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) {
 550                                 DRM_DEBUG_KMS("SAND format only valid for NV12/21");
 551                                 return -EINVAL;
 552                         }
 553                         hvs_format = HVS_PIXEL_FORMAT_H264;
 554                 } else {
 555                         if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) {
 556                                 DRM_DEBUG_KMS("SAND256 format only valid for H.264");
 557                                 return -EINVAL;
 558                         }
 559                 }
 560
 561                 switch (base_format_mod) {
 562                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 563                         tiling = SCALER_CTL0_TILING_64B;
 564                         break;
 565                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 566                         tiling = SCALER_CTL0_TILING_128B;
 567                         break;
 568                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 569                         tiling = SCALER_CTL0_TILING_256B_OR_T;
 570                         break;
 571                 default:
 572                         break;
 573                 }
 574
 575                 if (param > SCALER_TILE_HEIGHT_MASK) {
 576                         DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
 577                         return -EINVAL;
 578                 }
 579
 580                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
 581                 break;
 582         }
 583
 584         default:
 585                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 586                               (long long)fb->modifier);
 587                 return -EINVAL;
 588         }
 589
 590         /* Control word */
 591         vc4_dlist_write(vc4_state,
 592                         SCALER_CTL0_VALID |
 593                         VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
 594                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 595                         (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 596                         VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 597                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 598                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 599                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 600
 601         /* Position Word 0: Image Positions and Alpha Value */
 602         vc4_state->pos0_offset = vc4_state->dlist_count;
 603         vc4_dlist_write(vc4_state,
 604                         VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
 605                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 606                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 607
 608         /* Position Word 1: Scaled Image Dimensions. */
 609         if (!vc4_state->is_unity) {
 610                 vc4_dlist_write(vc4_state,
 611                                 VC4_SET_FIELD(vc4_state->crtc_w,
 612                                               SCALER_POS1_SCL_WIDTH) |
 613                                 VC4_SET_FIELD(vc4_state->crtc_h,
 614                                               SCALER_POS1_SCL_HEIGHT));
 615         }
 616
 617         /* Don't waste cycles mixing with plane alpha if the set alpha
 618          * is opaque or there is no per-pixel alpha information.
 619          * In any case we use the alpha property value as the fixed alpha.
 620          */
 621         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 622                           fb->format->has_alpha;
 623
 624         /* Position Word 2: Source Image Size, Alpha */
 625         vc4_state->pos2_offset = vc4_state->dlist_count;
 626         vc4_dlist_write(vc4_state,
 627                         VC4_SET_FIELD(fb->format->has_alpha ?
 628                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 629                                       SCALER_POS2_ALPHA_MODE_FIXED,
 630                                       SCALER_POS2_ALPHA_MODE) |
 631                         (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
 632                         (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
 633                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 634                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 635
 636         /* Position Word 3: Context.  Written by the HVS. */
 637         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 638
 639
 640         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 641          *
 642          * The pointers may be any byte address.
 643          */
 644         vc4_state->ptr0_offset = vc4_state->dlist_count;
 645         for (i = 0; i < num_planes; i++)
 646                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 647
 648         /* Pointer Context Word 0/1/2: Written by the HVS */
 649         for (i = 0; i < num_planes; i++)
 650                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 651
 652         /* Pitch word 0 */
 653         vc4_dlist_write(vc4_state, pitch0);
 654
 655         /* Pitch word 1/2 */
 656         for (i = 1; i < num_planes; i++) {
 657                 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
 658                         vc4_dlist_write(vc4_state,
 659                                         VC4_SET_FIELD(fb->pitches[i],
 660                                                       SCALER_SRC_PITCH));
 661                 } else {
 662                         vc4_dlist_write(vc4_state, pitch0);
 663                 }
 664         }
 665
 666         /* Colorspace conversion words */
 667         if (vc4_state->is_yuv) {
 668                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 669                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 670                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 671         }
 672
 673         if (!vc4_state->is_unity) {
 674                 /* LBM Base Address. */
 675                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 676                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 677                         vc4_dlist_write(vc4_state, vc4_state->lbm.start);
 678                 }
 679
 680                 if (num_planes > 1) {
 681                         /* Emit Cb/Cr as channel 0 and Y as channel
 682                          * 1. This matches how we set up scl0/scl1
 683                          * above.
 684                          */
 685                         vc4_write_scaling_parameters(state, 1);
 686                 }
 687                 vc4_write_scaling_parameters(state, 0);
 688
 689                 /* If any PPF setup was done, then all the kernel
 690                  * pointers get uploaded.
 691                  */
 692                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 693                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 694                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 695                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 696                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 697                                                    SCALER_PPF_KERNEL_OFFSET);
 698
 699                         /* HPPF plane 0 */
 700                         vc4_dlist_write(vc4_state, kernel);
 701                         /* VPPF plane 0 */
 702                         vc4_dlist_write(vc4_state, kernel);
 703                         /* HPPF plane 1 */
 704                         vc4_dlist_write(vc4_state, kernel);
 705                         /* VPPF plane 1 */
 706                         vc4_dlist_write(vc4_state, kernel);
 707                 }
 708         }
 709
 710         vc4_state->dlist[ctl0_offset] |=
 711                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 712
 713         /* crtc_* are already clipped coordinates. */
 714         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
 715                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
 716                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
 717         /* Background fill might be necessary when the plane has per-pixel
 718          * alpha content or a non-opaque plane alpha and could blend from the
 719          * background or does not cover the entire screen.
 720          */
 721         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
 722                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
 723
 724         return 0;
 725 }
 726
 727 /* If a modeset involves changing the setup of a plane, the atomic
 728  * infrastructure will call this to validate a proposed plane setup.
 729  * However, if a plane isn't getting updated, this (and the
 730  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 731  * compute the dlist here and have all active plane dlists get updated
 732  * in the CRTC's flush.
 733  */
 734 static int vc4_plane_atomic_check(struct drm_plane *plane,
 735                                   struct drm_plane_state *state)
 736 {
 737         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 738
 739         vc4_state->dlist_count = 0;
 740
 741         if (plane_enabled(state))
 742                 return vc4_plane_mode_set(plane, state);
 743         else
 744                 return 0;
 745 }
 746
 747 static void vc4_plane_atomic_update(struct drm_plane *plane,
 748                                     struct drm_plane_state *old_state)
 749 {
 750         /* No contents here.  Since we don't know where in the CRTC's
 751          * dlist we should be stored, our dlist is uploaded to the
 752          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 753          * time.
 754          */
 755 }
 756
 757 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 758 {
 759         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 760         int i;
 761
 762         vc4_state->hw_dlist = dlist;
 763
 764         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 765         for (i = 0; i < vc4_state->dlist_count; i++)
 766                 writel(vc4_state->dlist[i], &dlist[i]);
 767
 768         return vc4_state->dlist_count;
 769 }
 770
 771 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 772 {
 773         const struct vc4_plane_state *vc4_state =
 774                 container_of(state, typeof(*vc4_state), base);
 775
 776         return vc4_state->dlist_count;
 777 }
 778
 779 /* Updates the plane to immediately (well, once the FIFO needs
 780  * refilling) scan out from at a new framebuffer.
 781  */
 782 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 783 {
 784         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 785         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 786         uint32_t addr;
 787
 788         /* We're skipping the address adjustment for negative origin,
 789          * because this is only called on the primary plane.
 790          */
 791         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
 792         addr = bo->paddr + fb->offsets[0];
 793
 794         /* Write the new address into the hardware immediately.  The
 795          * scanout will start from this address as soon as the FIFO
 796          * needs to refill with pixels.
 797          */
 798         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 799
 800         /* Also update the CPU-side dlist copy, so that any later
 801          * atomic updates that don't do a new modeset on our plane
 802          * also use our updated address.
 803          */
 804         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
 805 }
 806
 807 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
 808                                           struct drm_plane_state *state)
 809 {
 810         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 811
 812         if (plane->state->fb != state->fb) {
 813                 vc4_plane_async_set_fb(plane, state->fb);
 814                 drm_atomic_set_fb_for_plane(plane->state, state->fb);
 815         }
 816
 817         /* Set the cursor's position on the screen.  This is the
 818          * expected change from the drm_mode_cursor_universal()
 819          * helper.
 820          */
 821         plane->state->crtc_x = state->crtc_x;
 822         plane->state->crtc_y = state->crtc_y;
 823
 824         /* Allow changing the start position within the cursor BO, if
 825          * that matters.
 826          */
 827         plane->state->src_x = state->src_x;
 828         plane->state->src_y = state->src_y;
 829
 830         /* Update the display list based on the new crtc_x/y. */
 831         vc4_plane_atomic_check(plane, plane->state);
 832
 833         /* Note that we can't just call vc4_plane_write_dlist()
 834          * because that would smash the context data that the HVS is
 835          * currently using.
 836          */
 837         writel(vc4_state->dlist[vc4_state->pos0_offset],
 838                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
 839         writel(vc4_state->dlist[vc4_state->pos2_offset],
 840                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
 841         writel(vc4_state->dlist[vc4_state->ptr0_offset],
 842                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 843 }
 844
 845 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
 846                                         struct drm_plane_state *state)
 847 {
 848         /* No configuring new scaling in the fast path. */
 849         if (plane->state->crtc_w != state->crtc_w ||
 850             plane->state->crtc_h != state->crtc_h ||
 851             plane->state->src_w != state->src_w ||
 852             plane->state->src_h != state->src_h)
 853                 return -EINVAL;
 854
 855         return 0;
 856 }
 857
 858 static int vc4_prepare_fb(struct drm_plane *plane,
 859                           struct drm_plane_state *state)
 860 {
 861         struct vc4_bo *bo;
 862         struct dma_fence *fence;
 863         int ret;
 864
 865         if (!state->fb)
 866                 return 0;
 867
 868         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 869
 870         fence = reservation_object_get_excl_rcu(bo->resv);
 871         drm_atomic_set_fence_for_plane(state, fence);
 872
 873         if (plane->state->fb == state->fb)
 874                 return 0;
 875
 876         ret = vc4_bo_inc_usecnt(bo);
 877         if (ret)
 878                 return ret;
 879
 880         return 0;
 881 }
 882
 883 static void vc4_cleanup_fb(struct drm_plane *plane,
 884                            struct drm_plane_state *state)
 885 {
 886         struct vc4_bo *bo;
 887
 888         if (plane->state->fb == state->fb || !state->fb)
 889                 return;
 890
 891         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 892         vc4_bo_dec_usecnt(bo);
 893 }
 894
 895 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 896         .atomic_check = vc4_plane_atomic_check,
 897         .atomic_update = vc4_plane_atomic_update,
 898         .prepare_fb = vc4_prepare_fb,
 899         .cleanup_fb = vc4_cleanup_fb,
 900         .atomic_async_check = vc4_plane_atomic_async_check,
 901         .atomic_async_update = vc4_plane_atomic_async_update,
 902 };
 903
 904 static void vc4_plane_destroy(struct drm_plane *plane)
 905 {
 906         drm_plane_helper_disable(plane, NULL);
 907         drm_plane_cleanup(plane);
 908 }
 909
 910 static bool vc4_format_mod_supported(struct drm_plane *plane,
 911                                      uint32_t format,
 912                                      uint64_t modifier)
 913 {
 914         /* Support T_TILING for RGB formats only. */
 915         switch (format) {
 916         case DRM_FORMAT_XRGB8888:
 917         case DRM_FORMAT_ARGB8888:
 918         case DRM_FORMAT_ABGR8888:
 919         case DRM_FORMAT_XBGR8888:
 920         case DRM_FORMAT_RGB565:
 921         case DRM_FORMAT_BGR565:
 922         case DRM_FORMAT_ARGB1555:
 923         case DRM_FORMAT_XRGB1555:
 924                 switch (fourcc_mod_broadcom_mod(modifier)) {
 925                 case DRM_FORMAT_MOD_LINEAR:
 926                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
 927                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 928                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 929                         return true;
 930                 default:
 931                         return false;
 932                 }
 933         case DRM_FORMAT_NV12:
 934         case DRM_FORMAT_NV21:
 935                 switch (fourcc_mod_broadcom_mod(modifier)) {
 936                 case DRM_FORMAT_MOD_LINEAR:
 937                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 938                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 939                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 940                         return true;
 941                 default:
 942                         return false;
 943                 }
 944         case DRM_FORMAT_YUV422:
 945         case DRM_FORMAT_YVU422:
 946         case DRM_FORMAT_YUV420:
 947         case DRM_FORMAT_YVU420:
 948         case DRM_FORMAT_NV16:
 949         case DRM_FORMAT_NV61:
 950         default:
 951                 return (modifier == DRM_FORMAT_MOD_LINEAR);
 952         }
 953 }
 954
 955 static const struct drm_plane_funcs vc4_plane_funcs = {
 956         .update_plane = drm_atomic_helper_update_plane,
 957         .disable_plane = drm_atomic_helper_disable_plane,
 958         .destroy = vc4_plane_destroy,
 959         .set_property = NULL,
 960         .reset = vc4_plane_reset,
 961         .atomic_duplicate_state = vc4_plane_duplicate_state,
 962         .atomic_destroy_state = vc4_plane_destroy_state,
 963         .format_mod_supported = vc4_format_mod_supported,
 964 };
 965
 966 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 967                                  enum drm_plane_type type)
 968 {
 969         struct drm_plane *plane = NULL;
 970         struct vc4_plane *vc4_plane;
 971         u32 formats[ARRAY_SIZE(hvs_formats)];
 972         u32 num_formats = 0;
 973         int ret = 0;
 974         unsigned i;
 975         static const uint64_t modifiers[] = {
 976                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 977                 DRM_FORMAT_MOD_BROADCOM_SAND128,
 978                 DRM_FORMAT_MOD_BROADCOM_SAND64,
 979                 DRM_FORMAT_MOD_BROADCOM_SAND256,
 980                 DRM_FORMAT_MOD_LINEAR,
 981                 DRM_FORMAT_MOD_INVALID
 982         };
 983
 984         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
 985                                  GFP_KERNEL);
 986         if (!vc4_plane)
 987                 return ERR_PTR(-ENOMEM);
 988
 989         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 990                 /* Don't allow YUV in cursor planes, since that means
 991                  * tuning on the scaler, which we don't allow for the
 992                  * cursor.
 993                  */
 994                 if (type != DRM_PLANE_TYPE_CURSOR ||
 995                     hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
 996                         formats[num_formats++] = hvs_formats[i].drm;
 997                 }
 998         }
 999         plane = &vc4_plane->base;
1000         ret = drm_universal_plane_init(dev, plane, 0,
1001                                        &vc4_plane_funcs,
1002                                        formats, num_formats,
1003                                        modifiers, type, NULL);
1004
1005         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1006
1007         drm_plane_create_alpha_property(plane);
1008
1009         return plane;
1010 }