drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_gem_framebuffer_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 #define HVS_NUM_CHANNELS 3
  28
  29 struct vc4_ctm_state {
  30         struct drm_private_state base;
  31         struct drm_color_ctm *ctm;
  32         int fifo;
  33 };
  34
  35 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  36 {
  37         return container_of(priv, struct vc4_ctm_state, base);
  38 }
  39
  40 struct vc4_hvs_state {
  41         struct drm_private_state base;
  42
  43         struct {
  44                 unsigned in_use: 1;
  45                 struct drm_crtc_commit *pending_commit;
  46         } fifo_state[HVS_NUM_CHANNELS];
  47 };
  48
  49 static struct vc4_hvs_state *
  50 to_vc4_hvs_state(struct drm_private_state *priv)
  51 {
  52         return container_of(priv, struct vc4_hvs_state, base);
  53 }
  54
  55 struct vc4_load_tracker_state {
  56         struct drm_private_state base;
  57         u64 hvs_load;
  58         u64 membus_load;
  59 };
  60
  61 static struct vc4_load_tracker_state *
  62 to_vc4_load_tracker_state(struct drm_private_state *priv)
  63 {
  64         return container_of(priv, struct vc4_load_tracker_state, base);
  65 }
  66
  67 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  68                                                struct drm_private_obj *manager)
  69 {
  70         struct drm_device *dev = state->dev;
  71         struct vc4_dev *vc4 = to_vc4_dev(dev);
  72         struct drm_private_state *priv_state;
  73         int ret;
  74
  75         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  76         if (ret)
  77                 return ERR_PTR(ret);
  78
  79         priv_state = drm_atomic_get_private_obj_state(state, manager);
  80         if (IS_ERR(priv_state))
  81                 return ERR_CAST(priv_state);
  82
  83         return to_vc4_ctm_state(priv_state);
  84 }
  85
  86 static struct drm_private_state *
  87 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  88 {
  89         struct vc4_ctm_state *state;
  90
  91         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  92         if (!state)
  93                 return NULL;
  94
  95         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  96
  97         return &state->base;
  98 }
  99
 100 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
 101                                   struct drm_private_state *state)
 102 {
 103         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
 104
 105         kfree(ctm_state);
 106 }
 107
 108 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 109         .atomic_duplicate_state = vc4_ctm_duplicate_state,
 110         .atomic_destroy_state = vc4_ctm_destroy_state,
 111 };
 112
 113 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
 114 {
 115         struct vc4_dev *vc4 = to_vc4_dev(dev);
 116
 117         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 118 }
 119
 120 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 121 {
 122         struct vc4_ctm_state *ctm_state;
 123
 124         drm_modeset_lock_init(&vc4->ctm_state_lock);
 125
 126         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 127         if (!ctm_state)
 128                 return -ENOMEM;
 129
 130         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 131                                     &vc4_ctm_state_funcs);
 132
 133         return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
 134 }
 135
 136 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 137 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 138 {
 139         u16 r;
 140
 141         /* Sign bit. */
 142         r = in & BIT_ULL(63) ? BIT(9) : 0;
 143
 144         if ((in & GENMASK_ULL(62, 32)) > 0) {
 145                 /* We have zero integer bits so we can only saturate here. */
 146                 r |= GENMASK(8, 0);
 147         } else {
 148                 /* Otherwise take the 9 most important fractional bits. */
 149                 r |= (in >> 23) & GENMASK(8, 0);
 150         }
 151
 152         return r;
 153 }
 154
 155 static void
 156 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 157 {
 158         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 159         struct drm_color_ctm *ctm = ctm_state->ctm;
 160
 161         if (ctm_state->fifo) {
 162                 HVS_WRITE(SCALER_OLEDCOEF2,
 163                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 164                                         SCALER_OLEDCOEF2_R_TO_R) |
 165                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 166                                         SCALER_OLEDCOEF2_R_TO_G) |
 167                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 168                                         SCALER_OLEDCOEF2_R_TO_B));
 169                 HVS_WRITE(SCALER_OLEDCOEF1,
 170                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 171                                         SCALER_OLEDCOEF1_G_TO_R) |
 172                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 173                                         SCALER_OLEDCOEF1_G_TO_G) |
 174                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 175                                         SCALER_OLEDCOEF1_G_TO_B));
 176                 HVS_WRITE(SCALER_OLEDCOEF0,
 177                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 178                                         SCALER_OLEDCOEF0_B_TO_R) |
 179                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 180                                         SCALER_OLEDCOEF0_B_TO_G) |
 181                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 182                                         SCALER_OLEDCOEF0_B_TO_B));
 183         }
 184
 185         HVS_WRITE(SCALER_OLEDOFFS,
 186                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 187 }
 188
 189 static struct vc4_hvs_state *
 190 vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
 191 {
 192         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 193         struct drm_private_state *priv_state;
 194
 195         priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
 196         if (IS_ERR(priv_state))
 197                 return ERR_CAST(priv_state);
 198
 199         return to_vc4_hvs_state(priv_state);
 200 }
 201
 202 static struct vc4_hvs_state *
 203 vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
 204 {
 205         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 206         struct drm_private_state *priv_state;
 207
 208         priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
 209         if (IS_ERR(priv_state))
 210                 return ERR_CAST(priv_state);
 211
 212         return to_vc4_hvs_state(priv_state);
 213 }
 214
 215 static struct vc4_hvs_state *
 216 vc4_hvs_get_global_state(struct drm_atomic_state *state)
 217 {
 218         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 219         struct drm_private_state *priv_state;
 220
 221         priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
 222         if (IS_ERR(priv_state))
 223                 return ERR_CAST(priv_state);
 224
 225         return to_vc4_hvs_state(priv_state);
 226 }
 227
 228 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 229                                      struct drm_atomic_state *state)
 230 {
 231         struct drm_crtc_state *crtc_state;
 232         struct drm_crtc *crtc;
 233         unsigned int i;
 234
 235         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 236                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 237                 u32 dispctrl;
 238                 u32 dsp3_mux;
 239
 240                 if (!crtc_state->active)
 241                         continue;
 242
 243                 if (vc4_state->assigned_channel != 2)
 244                         continue;
 245
 246                 /*
 247                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 248                  * FIFO X'.
 249                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 250                  *
 251                  * DSP3 is connected to FIFO2 unless the transposer is
 252                  * enabled. In this case, FIFO 2 is directly accessed by the
 253                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 254                  * route.
 255                  */
 256                 if (vc4_state->feed_txp)
 257                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 258                 else
 259                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 260
 261                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 262                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 263                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 264         }
 265 }
 266
 267 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 268                                      struct drm_atomic_state *state)
 269 {
 270         struct drm_crtc_state *crtc_state;
 271         struct drm_crtc *crtc;
 272         unsigned char mux;
 273         unsigned int i;
 274         u32 reg;
 275
 276         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 277                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 278                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 279
 280                 if (!vc4_state->update_muxing)
 281                         continue;
 282
 283                 switch (vc4_crtc->data->hvs_output) {
 284                 case 2:
 285                         mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 286                         reg = HVS_READ(SCALER_DISPECTRL);
 287                         HVS_WRITE(SCALER_DISPECTRL,
 288                                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 289                                   VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
 290                         break;
 291
 292                 case 3:
 293                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 294                                 mux = 3;
 295                         else
 296                                 mux = vc4_state->assigned_channel;
 297
 298                         reg = HVS_READ(SCALER_DISPCTRL);
 299                         HVS_WRITE(SCALER_DISPCTRL,
 300                                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 301                                   VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
 302                         break;
 303
 304                 case 4:
 305                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 306                                 mux = 3;
 307                         else
 308                                 mux = vc4_state->assigned_channel;
 309
 310                         reg = HVS_READ(SCALER_DISPEOLN);
 311                         HVS_WRITE(SCALER_DISPEOLN,
 312                                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 313                                   VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
 314
 315                         break;
 316
 317                 case 5:
 318                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 319                                 mux = 3;
 320                         else
 321                                 mux = vc4_state->assigned_channel;
 322
 323                         reg = HVS_READ(SCALER_DISPDITHER);
 324                         HVS_WRITE(SCALER_DISPDITHER,
 325                                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 326                                   VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
 327                         break;
 328
 329                 default:
 330                         break;
 331                 }
 332         }
 333 }
 334
 335 static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 336 {
 337         struct drm_device *dev = state->dev;
 338         struct vc4_dev *vc4 = to_vc4_dev(dev);
 339         struct vc4_hvs *hvs = vc4->hvs;
 340         struct drm_crtc_state *old_crtc_state;
 341         struct drm_crtc_state *new_crtc_state;
 342         struct drm_crtc *crtc;
 343         struct vc4_hvs_state *old_hvs_state;
 344         int i;
 345
 346         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 347                 struct vc4_crtc_state *vc4_crtc_state;
 348
 349                 if (!new_crtc_state->commit)
 350                         continue;
 351
 352                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 353                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 354         }
 355
 356         if (vc4->hvs->hvs5)
 357                 clk_set_min_rate(hvs->core_clk, 500000000);
 358
 359         old_hvs_state = vc4_hvs_get_old_global_state(state);
 360         if (!old_hvs_state)
 361                 return;
 362
 363         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 364                 struct vc4_crtc_state *vc4_crtc_state =
 365                         to_vc4_crtc_state(old_crtc_state);
 366                 unsigned int channel = vc4_crtc_state->assigned_channel;
 367                 int ret;
 368
 369                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 370                         continue;
 371
 372                 if (!old_hvs_state->fifo_state[channel].in_use)
 373                         continue;
 374
 375                 ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit);
 376                 if (ret)
 377                         drm_err(dev, "Timed out waiting for commit\n");
 378         }
 379
 380         drm_atomic_helper_commit_modeset_disables(dev, state);
 381
 382         vc4_ctm_commit(vc4, state);
 383
 384         if (vc4->hvs->hvs5)
 385                 vc5_hvs_pv_muxing_commit(vc4, state);
 386         else
 387                 vc4_hvs_pv_muxing_commit(vc4, state);
 388
 389         drm_atomic_helper_commit_planes(dev, state, 0);
 390
 391         drm_atomic_helper_commit_modeset_enables(dev, state);
 392
 393         drm_atomic_helper_fake_vblank(state);
 394
 395         drm_atomic_helper_commit_hw_done(state);
 396
 397         drm_atomic_helper_wait_for_flip_done(dev, state);
 398
 399         drm_atomic_helper_cleanup_planes(dev, state);
 400
 401         if (vc4->hvs->hvs5)
 402                 clk_set_min_rate(hvs->core_clk, 0);
 403 }
 404
 405 static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
 406 {
 407         struct drm_crtc_state *crtc_state;
 408         struct vc4_hvs_state *hvs_state;
 409         struct drm_crtc *crtc;
 410         unsigned int i;
 411
 412         hvs_state = vc4_hvs_get_new_global_state(state);
 413         if (!hvs_state)
 414                 return -EINVAL;
 415
 416         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 417                 struct vc4_crtc_state *vc4_crtc_state =
 418                         to_vc4_crtc_state(crtc_state);
 419                 unsigned int channel =
 420                         vc4_crtc_state->assigned_channel;
 421
 422                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 423                         continue;
 424
 425                 if (!hvs_state->fifo_state[channel].in_use)
 426                         continue;
 427
 428                 hvs_state->fifo_state[channel].pending_commit =
 429                         drm_crtc_commit_get(crtc_state->commit);
 430         }
 431
 432         return 0;
 433 }
 434
 435 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 436                                              struct drm_file *file_priv,
 437                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 438 {
 439         struct drm_mode_fb_cmd2 mode_cmd_local;
 440
 441         /* If the user didn't specify a modifier, use the
 442          * vc4_set_tiling_ioctl() state for the BO.
 443          */
 444         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 445                 struct drm_gem_object *gem_obj;
 446                 struct vc4_bo *bo;
 447
 448                 gem_obj = drm_gem_object_lookup(file_priv,
 449                                                 mode_cmd->handles[0]);
 450                 if (!gem_obj) {
 451                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 452                                   mode_cmd->handles[0]);
 453                         return ERR_PTR(-ENOENT);
 454                 }
 455                 bo = to_vc4_bo(gem_obj);
 456
 457                 mode_cmd_local = *mode_cmd;
 458
 459                 if (bo->t_format) {
 460                         mode_cmd_local.modifier[0] =
 461                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 462                 } else {
 463                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 464                 }
 465
 466                 drm_gem_object_put(gem_obj);
 467
 468                 mode_cmd = &mode_cmd_local;
 469         }
 470
 471         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 472 }
 473
 474 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 475  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 476  * we don't allow userland to set a CTM that we have no hope of approximating.
 477  */
 478 static int
 479 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 480 {
 481         struct vc4_dev *vc4 = to_vc4_dev(dev);
 482         struct vc4_ctm_state *ctm_state = NULL;
 483         struct drm_crtc *crtc;
 484         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 485         struct drm_color_ctm *ctm;
 486         int i;
 487
 488         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 489                 /* CTM is being disabled. */
 490                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 491                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 492                         if (IS_ERR(ctm_state))
 493                                 return PTR_ERR(ctm_state);
 494                         ctm_state->fifo = 0;
 495                 }
 496         }
 497
 498         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 499                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 500                         continue;
 501
 502                 if (!ctm_state) {
 503                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 504                         if (IS_ERR(ctm_state))
 505                                 return PTR_ERR(ctm_state);
 506                 }
 507
 508                 /* CTM is being enabled or the matrix changed. */
 509                 if (new_crtc_state->ctm) {
 510                         struct vc4_crtc_state *vc4_crtc_state =
 511                                 to_vc4_crtc_state(new_crtc_state);
 512
 513                         /* fifo is 1-based since 0 disables CTM. */
 514                         int fifo = vc4_crtc_state->assigned_channel + 1;
 515
 516                         /* Check userland isn't trying to turn on CTM for more
 517                          * than one CRTC at a time.
 518                          */
 519                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 520                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 521                                 return -EINVAL;
 522                         }
 523
 524                         /* Check we can approximate the specified CTM.
 525                          * We disallow scalars |c| > 1.0 since the HW has
 526                          * no integer bits.
 527                          */
 528                         ctm = new_crtc_state->ctm->data;
 529                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 530                                 u64 val = ctm->matrix[i];
 531
 532                                 val &= ~BIT_ULL(63);
 533                                 if (val > BIT_ULL(32))
 534                                         return -EINVAL;
 535                         }
 536
 537                         ctm_state->fifo = fifo;
 538                         ctm_state->ctm = ctm;
 539                 }
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 546 {
 547         struct drm_plane_state *old_plane_state, *new_plane_state;
 548         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 549         struct vc4_load_tracker_state *load_state;
 550         struct drm_private_state *priv_state;
 551         struct drm_plane *plane;
 552         int i;
 553
 554         priv_state = drm_atomic_get_private_obj_state(state,
 555                                                       &vc4->load_tracker);
 556         if (IS_ERR(priv_state))
 557                 return PTR_ERR(priv_state);
 558
 559         load_state = to_vc4_load_tracker_state(priv_state);
 560         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 561                                        new_plane_state, i) {
 562                 struct vc4_plane_state *vc4_plane_state;
 563
 564                 if (old_plane_state->fb && old_plane_state->crtc) {
 565                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 566                         load_state->membus_load -= vc4_plane_state->membus_load;
 567                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 568                 }
 569
 570                 if (new_plane_state->fb && new_plane_state->crtc) {
 571                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 572                         load_state->membus_load += vc4_plane_state->membus_load;
 573                         load_state->hvs_load += vc4_plane_state->hvs_load;
 574                 }
 575         }
 576
 577         /* Don't check the load when the tracker is disabled. */
 578         if (!vc4->load_tracker_enabled)
 579                 return 0;
 580
 581         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 582          * the system work when other blocks are accessing the memory.
 583          */
 584         if (load_state->membus_load > SZ_1G + SZ_512M)
 585                 return -ENOSPC;
 586
 587         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 588          * consider the maximum number of cycles is 240M.
 589          */
 590         if (load_state->hvs_load > 240000000ULL)
 591                 return -ENOSPC;
 592
 593         return 0;
 594 }
 595
 596 static struct drm_private_state *
 597 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 598 {
 599         struct vc4_load_tracker_state *state;
 600
 601         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 602         if (!state)
 603                 return NULL;
 604
 605         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 606
 607         return &state->base;
 608 }
 609
 610 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 611                                            struct drm_private_state *state)
 612 {
 613         struct vc4_load_tracker_state *load_state;
 614
 615         load_state = to_vc4_load_tracker_state(state);
 616         kfree(load_state);
 617 }
 618
 619 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 620         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 621         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 622 };
 623
 624 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 625 {
 626         struct vc4_dev *vc4 = to_vc4_dev(dev);
 627
 628         drm_atomic_private_obj_fini(&vc4->load_tracker);
 629 }
 630
 631 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 632 {
 633         struct vc4_load_tracker_state *load_state;
 634
 635         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 636         if (!load_state)
 637                 return -ENOMEM;
 638
 639         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 640                                     &load_state->base,
 641                                     &vc4_load_tracker_state_funcs);
 642
 643         return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 644 }
 645
 646 static struct drm_private_state *
 647 vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
 648 {
 649         struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
 650         struct vc4_hvs_state *state;
 651         unsigned int i;
 652
 653         state = kzalloc(sizeof(*state), GFP_KERNEL);
 654         if (!state)
 655                 return NULL;
 656
 657         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 658
 659
 660         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 661                 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
 662
 663                 if (!old_state->fifo_state[i].pending_commit)
 664                         continue;
 665
 666                 state->fifo_state[i].pending_commit =
 667                         drm_crtc_commit_get(old_state->fifo_state[i].pending_commit);
 668         }
 669
 670         return &state->base;
 671 }
 672
 673 static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
 674                                            struct drm_private_state *state)
 675 {
 676         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 677         unsigned int i;
 678
 679         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 680                 if (!hvs_state->fifo_state[i].pending_commit)
 681                         continue;
 682
 683                 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
 684         }
 685
 686         kfree(hvs_state);
 687 }
 688
 689 static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
 690         .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
 691         .atomic_destroy_state = vc4_hvs_channels_destroy_state,
 692 };
 693
 694 static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
 695 {
 696         struct vc4_dev *vc4 = to_vc4_dev(dev);
 697
 698         drm_atomic_private_obj_fini(&vc4->hvs_channels);
 699 }
 700
 701 static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
 702 {
 703         struct vc4_hvs_state *state;
 704
 705         state = kzalloc(sizeof(*state), GFP_KERNEL);
 706         if (!state)
 707                 return -ENOMEM;
 708
 709         drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
 710                                     &state->base,
 711                                     &vc4_hvs_state_funcs);
 712
 713         return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
 714 }
 715
 716 /*
 717  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
 718  * the TXP (and therefore all the CRTCs found on that platform).
 719  *
 720  * The naive (and our initial) implementation would just iterate over
 721  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 722  * from the pool of available FIFOs. However, there are a few corner
 723  * cases that need to be considered:
 724  *
 725  * - When running in a dual-display setup (so with two CRTCs involved),
 726  *   we can update the state of a single CRTC (for example by changing
 727  *   its mode using xrandr under X11) without affecting the other. In
 728  *   this case, the other CRTC wouldn't be in the state at all, so we
 729  *   need to consider all the running CRTCs in the DRM device to assign
 730  *   a FIFO, not just the one in the state.
 731  *
 732  * - To fix the above, we can't use drm_atomic_get_crtc_state on all
 733  *   enabled CRTCs to pull their CRTC state into the global state, since
 734  *   a page flip would start considering their vblank to complete. Since
 735  *   we don't have a guarantee that they are actually active, that
 736  *   vblank might never happen, and shouldn't even be considered if we
 737  *   want to do a page flip on a single CRTC. That can be tested by
 738  *   doing a modetest -v first on HDMI1 and then on HDMI0.
 739  *
 740  * - Since we need the pixelvalve to be disabled and enabled back when
 741  *   the FIFO is changed, we should keep the FIFO assigned for as long
 742  *   as the CRTC is enabled, only considering it free again once that
 743  *   CRTC has been disabled. This can be tested by booting X11 on a
 744  *   single display, and changing the resolution down and then back up.
 745  */
 746 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 747                                       struct drm_atomic_state *state)
 748 {
 749         struct vc4_hvs_state *hvs_new_state;
 750         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 751         struct drm_crtc *crtc;
 752         unsigned int unassigned_channels = 0;
 753         unsigned int i;
 754
 755         hvs_new_state = vc4_hvs_get_global_state(state);
 756         if (!hvs_new_state)
 757                 return -EINVAL;
 758
 759         for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
 760                 if (!hvs_new_state->fifo_state[i].in_use)
 761                         unassigned_channels |= BIT(i);
 762
 763         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 764                 struct vc4_crtc_state *old_vc4_crtc_state =
 765                         to_vc4_crtc_state(old_crtc_state);
 766                 struct vc4_crtc_state *new_vc4_crtc_state =
 767                         to_vc4_crtc_state(new_crtc_state);
 768                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 769                 unsigned int matching_channels;
 770                 unsigned int channel;
 771
 772                 /* Nothing to do here, let's skip it */
 773                 if (old_crtc_state->enable == new_crtc_state->enable)
 774                         continue;
 775
 776                 /* Muxing will need to be modified, mark it as such */
 777                 new_vc4_crtc_state->update_muxing = true;
 778
 779                 /* If we're disabling our CRTC, we put back our channel */
 780                 if (!new_crtc_state->enable) {
 781                         channel = old_vc4_crtc_state->assigned_channel;
 782                         hvs_new_state->fifo_state[channel].in_use = false;
 783                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 784                         continue;
 785                 }
 786
 787                 /*
 788                  * The problem we have to solve here is that we have
 789                  * up to 7 encoders, connected to up to 6 CRTCs.
 790                  *
 791                  * Those CRTCs, depending on the instance, can be
 792                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 793                  * the change the muxing between FIFOs and outputs in
 794                  * the HVS accordingly.
 795                  *
 796                  * It would be pretty hard to come up with an
 797                  * algorithm that would generically solve
 798                  * this. However, the current routing trees we support
 799                  * allow us to simplify a bit the problem.
 800                  *
 801                  * Indeed, with the current supported layouts, if we
 802                  * try to assign in the ascending crtc index order the
 803                  * FIFOs, we can't fall into the situation where an
 804                  * earlier CRTC that had multiple routes is assigned
 805                  * one that was the only option for a later CRTC.
 806                  *
 807                  * If the layout changes and doesn't give us that in
 808                  * the future, we will need to have something smarter,
 809                  * but it works so far.
 810                  */
 811                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 812                 if (!matching_channels)
 813                         return -EINVAL;
 814
 815                 channel = ffs(matching_channels) - 1;
 816                 new_vc4_crtc_state->assigned_channel = channel;
 817                 unassigned_channels &= ~BIT(channel);
 818                 hvs_new_state->fifo_state[channel].in_use = true;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int
 825 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 826 {
 827         int ret;
 828
 829         ret = vc4_pv_muxing_atomic_check(dev, state);
 830         if (ret)
 831                 return ret;
 832
 833         ret = vc4_ctm_atomic_check(dev, state);
 834         if (ret < 0)
 835                 return ret;
 836
 837         ret = drm_atomic_helper_check(dev, state);
 838         if (ret)
 839                 return ret;
 840
 841         return vc4_load_tracker_atomic_check(state);
 842 }
 843
 844 static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
 845         .atomic_commit_setup    = vc4_atomic_commit_setup,
 846         .atomic_commit_tail     = vc4_atomic_commit_tail,
 847 };
 848
 849 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 850         .atomic_check = vc4_atomic_check,
 851         .atomic_commit = drm_atomic_helper_commit,
 852         .fb_create = vc4_fb_create,
 853 };
 854
 855 int vc4_kms_load(struct drm_device *dev)
 856 {
 857         struct vc4_dev *vc4 = to_vc4_dev(dev);
 858         bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 859                                               "brcm,bcm2711-vc5");
 860         int ret;
 861
 862         /*
 863          * The limits enforced by the load tracker aren't relevant for
 864          * the BCM2711, but the load tracker computations are used for
 865          * the core clock rate calculation.
 866          */
 867         if (!is_vc5) {
 868                 /* Start with the load tracker enabled. Can be
 869                  * disabled through the debugfs load_tracker file.
 870                  */
 871                 vc4->load_tracker_enabled = true;
 872         }
 873
 874         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 875         dev->vblank_disable_immediate = true;
 876
 877         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 878         if (ret < 0) {
 879                 dev_err(dev->dev, "failed to initialize vblank\n");
 880                 return ret;
 881         }
 882
 883         if (is_vc5) {
 884                 dev->mode_config.max_width = 7680;
 885                 dev->mode_config.max_height = 7680;
 886         } else {
 887                 dev->mode_config.max_width = 2048;
 888                 dev->mode_config.max_height = 2048;
 889         }
 890
 891         dev->mode_config.funcs = &vc4_mode_funcs;
 892         dev->mode_config.helper_private = &vc4_mode_config_helpers;
 893         dev->mode_config.preferred_depth = 24;
 894         dev->mode_config.async_page_flip = true;
 895
 896         ret = vc4_ctm_obj_init(vc4);
 897         if (ret)
 898                 return ret;
 899
 900         ret = vc4_load_tracker_obj_init(vc4);
 901         if (ret)
 902                 return ret;
 903
 904         ret = vc4_hvs_channels_obj_init(vc4);
 905         if (ret)
 906                 return ret;
 907
 908         drm_mode_config_reset(dev);
 909
 910         drm_kms_helper_poll_init(dev);
 911
 912         return 0;
 913 }