drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_gem_framebuffer_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 #define HVS_NUM_CHANNELS 3
  28
  29 struct vc4_ctm_state {
  30         struct drm_private_state base;
  31         struct drm_color_ctm *ctm;
  32         int fifo;
  33 };
  34
  35 static struct vc4_ctm_state *
  36 to_vc4_ctm_state(const struct drm_private_state *priv)
  37 {
  38         return container_of(priv, struct vc4_ctm_state, base);
  39 }
  40
  41 struct vc4_hvs_state {
  42         struct drm_private_state base;
  43         unsigned long core_clock_rate;
  44
  45         struct {
  46                 unsigned in_use: 1;
  47                 unsigned long fifo_load;
  48                 struct drm_crtc_commit *pending_commit;
  49         } fifo_state[HVS_NUM_CHANNELS];
  50 };
  51
  52 static struct vc4_hvs_state *
  53 to_vc4_hvs_state(const struct drm_private_state *priv)
  54 {
  55         return container_of(priv, struct vc4_hvs_state, base);
  56 }
  57
  58 struct vc4_load_tracker_state {
  59         struct drm_private_state base;
  60         u64 hvs_load;
  61         u64 membus_load;
  62 };
  63
  64 static struct vc4_load_tracker_state *
  65 to_vc4_load_tracker_state(const struct drm_private_state *priv)
  66 {
  67         return container_of(priv, struct vc4_load_tracker_state, base);
  68 }
  69
  70 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  71                                                struct drm_private_obj *manager)
  72 {
  73         struct drm_device *dev = state->dev;
  74         struct vc4_dev *vc4 = to_vc4_dev(dev);
  75         struct drm_private_state *priv_state;
  76         int ret;
  77
  78         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  79         if (ret)
  80                 return ERR_PTR(ret);
  81
  82         priv_state = drm_atomic_get_private_obj_state(state, manager);
  83         if (IS_ERR(priv_state))
  84                 return ERR_CAST(priv_state);
  85
  86         return to_vc4_ctm_state(priv_state);
  87 }
  88
  89 static struct drm_private_state *
  90 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  91 {
  92         struct vc4_ctm_state *state;
  93
  94         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  95         if (!state)
  96                 return NULL;
  97
  98         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  99
 100         return &state->base;
 101 }
 102
 103 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
 104                                   struct drm_private_state *state)
 105 {
 106         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
 107
 108         kfree(ctm_state);
 109 }
 110
 111 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 112         .atomic_duplicate_state = vc4_ctm_duplicate_state,
 113         .atomic_destroy_state = vc4_ctm_destroy_state,
 114 };
 115
 116 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
 117 {
 118         struct vc4_dev *vc4 = to_vc4_dev(dev);
 119
 120         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 121 }
 122
 123 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 124 {
 125         struct vc4_ctm_state *ctm_state;
 126
 127         drm_modeset_lock_init(&vc4->ctm_state_lock);
 128
 129         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 130         if (!ctm_state)
 131                 return -ENOMEM;
 132
 133         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 134                                     &vc4_ctm_state_funcs);
 135
 136         return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
 137 }
 138
 139 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 140 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 141 {
 142         u16 r;
 143
 144         /* Sign bit. */
 145         r = in & BIT_ULL(63) ? BIT(9) : 0;
 146
 147         if ((in & GENMASK_ULL(62, 32)) > 0) {
 148                 /* We have zero integer bits so we can only saturate here. */
 149                 r |= GENMASK(8, 0);
 150         } else {
 151                 /* Otherwise take the 9 most important fractional bits. */
 152                 r |= (in >> 23) & GENMASK(8, 0);
 153         }
 154
 155         return r;
 156 }
 157
 158 static void
 159 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 160 {
 161         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 162         struct drm_color_ctm *ctm = ctm_state->ctm;
 163
 164         if (ctm_state->fifo) {
 165                 HVS_WRITE(SCALER_OLEDCOEF2,
 166                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 167                                         SCALER_OLEDCOEF2_R_TO_R) |
 168                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 169                                         SCALER_OLEDCOEF2_R_TO_G) |
 170                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 171                                         SCALER_OLEDCOEF2_R_TO_B));
 172                 HVS_WRITE(SCALER_OLEDCOEF1,
 173                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 174                                         SCALER_OLEDCOEF1_G_TO_R) |
 175                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 176                                         SCALER_OLEDCOEF1_G_TO_G) |
 177                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 178                                         SCALER_OLEDCOEF1_G_TO_B));
 179                 HVS_WRITE(SCALER_OLEDCOEF0,
 180                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 181                                         SCALER_OLEDCOEF0_B_TO_R) |
 182                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 183                                         SCALER_OLEDCOEF0_B_TO_G) |
 184                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 185                                         SCALER_OLEDCOEF0_B_TO_B));
 186         }
 187
 188         HVS_WRITE(SCALER_OLEDOFFS,
 189                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 190 }
 191
 192 static struct vc4_hvs_state *
 193 vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
 194 {
 195         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 196         struct drm_private_state *priv_state;
 197
 198         priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
 199         if (IS_ERR(priv_state))
 200                 return ERR_CAST(priv_state);
 201
 202         return to_vc4_hvs_state(priv_state);
 203 }
 204
 205 static struct vc4_hvs_state *
 206 vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
 207 {
 208         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 209         struct drm_private_state *priv_state;
 210
 211         priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
 212         if (IS_ERR(priv_state))
 213                 return ERR_CAST(priv_state);
 214
 215         return to_vc4_hvs_state(priv_state);
 216 }
 217
 218 static struct vc4_hvs_state *
 219 vc4_hvs_get_global_state(struct drm_atomic_state *state)
 220 {
 221         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 222         struct drm_private_state *priv_state;
 223
 224         priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
 225         if (IS_ERR(priv_state))
 226                 return ERR_CAST(priv_state);
 227
 228         return to_vc4_hvs_state(priv_state);
 229 }
 230
 231 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 232                                      struct drm_atomic_state *state)
 233 {
 234         struct drm_crtc_state *crtc_state;
 235         struct drm_crtc *crtc;
 236         unsigned int i;
 237
 238         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 239                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 240                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 241                 u32 dispctrl;
 242                 u32 dsp3_mux;
 243
 244                 if (!crtc_state->active)
 245                         continue;
 246
 247                 if (vc4_state->assigned_channel != 2)
 248                         continue;
 249
 250                 /*
 251                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 252                  * FIFO X'.
 253                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 254                  *
 255                  * DSP3 is connected to FIFO2 unless the transposer is
 256                  * enabled. In this case, FIFO 2 is directly accessed by the
 257                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 258                  * route.
 259                  */
 260                 if (vc4_crtc->feeds_txp)
 261                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 262                 else
 263                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 264
 265                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 266                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 267                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 268         }
 269 }
 270
 271 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 272                                      struct drm_atomic_state *state)
 273 {
 274         struct drm_crtc_state *crtc_state;
 275         struct drm_crtc *crtc;
 276         unsigned char mux;
 277         unsigned int i;
 278         u32 reg;
 279
 280         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 281                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 282                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 283
 284                 if (!vc4_state->update_muxing)
 285                         continue;
 286
 287                 switch (vc4_crtc->data->hvs_output) {
 288                 case 2:
 289                         mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 290                         reg = HVS_READ(SCALER_DISPECTRL);
 291                         HVS_WRITE(SCALER_DISPECTRL,
 292                                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 293                                   VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
 294                         break;
 295
 296                 case 3:
 297                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 298                                 mux = 3;
 299                         else
 300                                 mux = vc4_state->assigned_channel;
 301
 302                         reg = HVS_READ(SCALER_DISPCTRL);
 303                         HVS_WRITE(SCALER_DISPCTRL,
 304                                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 305                                   VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
 306                         break;
 307
 308                 case 4:
 309                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 310                                 mux = 3;
 311                         else
 312                                 mux = vc4_state->assigned_channel;
 313
 314                         reg = HVS_READ(SCALER_DISPEOLN);
 315                         HVS_WRITE(SCALER_DISPEOLN,
 316                                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 317                                   VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
 318
 319                         break;
 320
 321                 case 5:
 322                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 323                                 mux = 3;
 324                         else
 325                                 mux = vc4_state->assigned_channel;
 326
 327                         reg = HVS_READ(SCALER_DISPDITHER);
 328                         HVS_WRITE(SCALER_DISPDITHER,
 329                                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 330                                   VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
 331                         break;
 332
 333                 default:
 334                         break;
 335                 }
 336         }
 337 }
 338
 339 static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 340 {
 341         struct drm_device *dev = state->dev;
 342         struct vc4_dev *vc4 = to_vc4_dev(dev);
 343         struct vc4_hvs *hvs = vc4->hvs;
 344         struct drm_crtc_state *new_crtc_state;
 345         struct vc4_hvs_state *new_hvs_state;
 346         struct drm_crtc *crtc;
 347         struct vc4_hvs_state *old_hvs_state;
 348         unsigned int channel;
 349         int i;
 350
 351         old_hvs_state = vc4_hvs_get_old_global_state(state);
 352         if (WARN_ON(IS_ERR(old_hvs_state)))
 353                 return;
 354
 355         new_hvs_state = vc4_hvs_get_new_global_state(state);
 356         if (WARN_ON(IS_ERR(new_hvs_state)))
 357                 return;
 358
 359         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 360                 struct vc4_crtc_state *vc4_crtc_state;
 361
 362                 if (!new_crtc_state->commit)
 363                         continue;
 364
 365                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 366                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 367         }
 368
 369         for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
 370                 struct drm_crtc_commit *commit;
 371                 int ret;
 372
 373                 if (!old_hvs_state->fifo_state[channel].in_use)
 374                         continue;
 375
 376                 commit = old_hvs_state->fifo_state[channel].pending_commit;
 377                 if (!commit)
 378                         continue;
 379
 380                 ret = drm_crtc_commit_wait(commit);
 381                 if (ret)
 382                         drm_err(dev, "Timed out waiting for commit\n");
 383
 384                 drm_crtc_commit_put(commit);
 385                 old_hvs_state->fifo_state[channel].pending_commit = NULL;
 386         }
 387
 388         if (vc4->hvs->hvs5) {
 389                 unsigned long core_rate = max_t(unsigned long,
 390                                                 500000000,
 391                                                 new_hvs_state->core_clock_rate);
 392
 393                 clk_set_min_rate(hvs->core_clk, core_rate);
 394         }
 395         drm_atomic_helper_commit_modeset_disables(dev, state);
 396
 397         vc4_ctm_commit(vc4, state);
 398
 399         if (vc4->hvs->hvs5)
 400                 vc5_hvs_pv_muxing_commit(vc4, state);
 401         else
 402                 vc4_hvs_pv_muxing_commit(vc4, state);
 403
 404         drm_atomic_helper_commit_planes(dev, state, 0);
 405
 406         drm_atomic_helper_commit_modeset_enables(dev, state);
 407
 408         drm_atomic_helper_fake_vblank(state);
 409
 410         drm_atomic_helper_commit_hw_done(state);
 411
 412         drm_atomic_helper_wait_for_flip_done(dev, state);
 413
 414         drm_atomic_helper_cleanup_planes(dev, state);
 415
 416         if (vc4->hvs->hvs5) {
 417                 drm_dbg(dev, "Running the core clock at %lu Hz\n",
 418                         new_hvs_state->core_clock_rate);
 419
 420                 clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate);
 421         }
 422 }
 423
 424 static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
 425 {
 426         struct drm_crtc_state *crtc_state;
 427         struct vc4_hvs_state *hvs_state;
 428         struct drm_crtc *crtc;
 429         unsigned int i;
 430
 431         hvs_state = vc4_hvs_get_new_global_state(state);
 432         if (WARN_ON(IS_ERR(hvs_state)))
 433                 return PTR_ERR(hvs_state);
 434
 435         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 436                 struct vc4_crtc_state *vc4_crtc_state =
 437                         to_vc4_crtc_state(crtc_state);
 438                 unsigned int channel =
 439                         vc4_crtc_state->assigned_channel;
 440
 441                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 442                         continue;
 443
 444                 if (!hvs_state->fifo_state[channel].in_use)
 445                         continue;
 446
 447                 hvs_state->fifo_state[channel].pending_commit =
 448                         drm_crtc_commit_get(crtc_state->commit);
 449         }
 450
 451         return 0;
 452 }
 453
 454 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 455                                              struct drm_file *file_priv,
 456                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 457 {
 458         struct drm_mode_fb_cmd2 mode_cmd_local;
 459
 460         /* If the user didn't specify a modifier, use the
 461          * vc4_set_tiling_ioctl() state for the BO.
 462          */
 463         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 464                 struct drm_gem_object *gem_obj;
 465                 struct vc4_bo *bo;
 466
 467                 gem_obj = drm_gem_object_lookup(file_priv,
 468                                                 mode_cmd->handles[0]);
 469                 if (!gem_obj) {
 470                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 471                                   mode_cmd->handles[0]);
 472                         return ERR_PTR(-ENOENT);
 473                 }
 474                 bo = to_vc4_bo(gem_obj);
 475
 476                 mode_cmd_local = *mode_cmd;
 477
 478                 if (bo->t_format) {
 479                         mode_cmd_local.modifier[0] =
 480                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 481                 } else {
 482                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 483                 }
 484
 485                 drm_gem_object_put(gem_obj);
 486
 487                 mode_cmd = &mode_cmd_local;
 488         }
 489
 490         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 491 }
 492
 493 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 494  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 495  * we don't allow userland to set a CTM that we have no hope of approximating.
 496  */
 497 static int
 498 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 499 {
 500         struct vc4_dev *vc4 = to_vc4_dev(dev);
 501         struct vc4_ctm_state *ctm_state = NULL;
 502         struct drm_crtc *crtc;
 503         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 504         struct drm_color_ctm *ctm;
 505         int i;
 506
 507         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 508                 /* CTM is being disabled. */
 509                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 510                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 511                         if (IS_ERR(ctm_state))
 512                                 return PTR_ERR(ctm_state);
 513                         ctm_state->fifo = 0;
 514                 }
 515         }
 516
 517         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 518                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 519                         continue;
 520
 521                 if (!ctm_state) {
 522                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 523                         if (IS_ERR(ctm_state))
 524                                 return PTR_ERR(ctm_state);
 525                 }
 526
 527                 /* CTM is being enabled or the matrix changed. */
 528                 if (new_crtc_state->ctm) {
 529                         struct vc4_crtc_state *vc4_crtc_state =
 530                                 to_vc4_crtc_state(new_crtc_state);
 531
 532                         /* fifo is 1-based since 0 disables CTM. */
 533                         int fifo = vc4_crtc_state->assigned_channel + 1;
 534
 535                         /* Check userland isn't trying to turn on CTM for more
 536                          * than one CRTC at a time.
 537                          */
 538                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 539                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 540                                 return -EINVAL;
 541                         }
 542
 543                         /* Check we can approximate the specified CTM.
 544                          * We disallow scalars |c| > 1.0 since the HW has
 545                          * no integer bits.
 546                          */
 547                         ctm = new_crtc_state->ctm->data;
 548                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 549                                 u64 val = ctm->matrix[i];
 550
 551                                 val &= ~BIT_ULL(63);
 552                                 if (val > BIT_ULL(32))
 553                                         return -EINVAL;
 554                         }
 555
 556                         ctm_state->fifo = fifo;
 557                         ctm_state->ctm = ctm;
 558                 }
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 565 {
 566         struct drm_plane_state *old_plane_state, *new_plane_state;
 567         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 568         struct vc4_load_tracker_state *load_state;
 569         struct drm_private_state *priv_state;
 570         struct drm_plane *plane;
 571         int i;
 572
 573         priv_state = drm_atomic_get_private_obj_state(state,
 574                                                       &vc4->load_tracker);
 575         if (IS_ERR(priv_state))
 576                 return PTR_ERR(priv_state);
 577
 578         load_state = to_vc4_load_tracker_state(priv_state);
 579         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 580                                        new_plane_state, i) {
 581                 struct vc4_plane_state *vc4_plane_state;
 582
 583                 if (old_plane_state->fb && old_plane_state->crtc) {
 584                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 585                         load_state->membus_load -= vc4_plane_state->membus_load;
 586                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 587                 }
 588
 589                 if (new_plane_state->fb && new_plane_state->crtc) {
 590                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 591                         load_state->membus_load += vc4_plane_state->membus_load;
 592                         load_state->hvs_load += vc4_plane_state->hvs_load;
 593                 }
 594         }
 595
 596         /* Don't check the load when the tracker is disabled. */
 597         if (!vc4->load_tracker_enabled)
 598                 return 0;
 599
 600         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 601          * the system work when other blocks are accessing the memory.
 602          */
 603         if (load_state->membus_load > SZ_1G + SZ_512M)
 604                 return -ENOSPC;
 605
 606         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 607          * consider the maximum number of cycles is 240M.
 608          */
 609         if (load_state->hvs_load > 240000000ULL)
 610                 return -ENOSPC;
 611
 612         return 0;
 613 }
 614
 615 static struct drm_private_state *
 616 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 617 {
 618         struct vc4_load_tracker_state *state;
 619
 620         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 621         if (!state)
 622                 return NULL;
 623
 624         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 625
 626         return &state->base;
 627 }
 628
 629 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 630                                            struct drm_private_state *state)
 631 {
 632         struct vc4_load_tracker_state *load_state;
 633
 634         load_state = to_vc4_load_tracker_state(state);
 635         kfree(load_state);
 636 }
 637
 638 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 639         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 640         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 641 };
 642
 643 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 644 {
 645         struct vc4_dev *vc4 = to_vc4_dev(dev);
 646
 647         drm_atomic_private_obj_fini(&vc4->load_tracker);
 648 }
 649
 650 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 651 {
 652         struct vc4_load_tracker_state *load_state;
 653
 654         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 655         if (!load_state)
 656                 return -ENOMEM;
 657
 658         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 659                                     &load_state->base,
 660                                     &vc4_load_tracker_state_funcs);
 661
 662         return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 663 }
 664
 665 static struct drm_private_state *
 666 vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
 667 {
 668         struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
 669         struct vc4_hvs_state *state;
 670         unsigned int i;
 671
 672         state = kzalloc(sizeof(*state), GFP_KERNEL);
 673         if (!state)
 674                 return NULL;
 675
 676         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 677
 678         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 679                 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
 680                 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load;
 681         }
 682
 683         state->core_clock_rate = old_state->core_clock_rate;
 684
 685         return &state->base;
 686 }
 687
 688 static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
 689                                            struct drm_private_state *state)
 690 {
 691         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 692         unsigned int i;
 693
 694         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 695                 if (!hvs_state->fifo_state[i].pending_commit)
 696                         continue;
 697
 698                 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
 699         }
 700
 701         kfree(hvs_state);
 702 }
 703
 704 static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
 705         .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
 706         .atomic_destroy_state = vc4_hvs_channels_destroy_state,
 707 };
 708
 709 static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
 710 {
 711         struct vc4_dev *vc4 = to_vc4_dev(dev);
 712
 713         drm_atomic_private_obj_fini(&vc4->hvs_channels);
 714 }
 715
 716 static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
 717 {
 718         struct vc4_hvs_state *state;
 719
 720         state = kzalloc(sizeof(*state), GFP_KERNEL);
 721         if (!state)
 722                 return -ENOMEM;
 723
 724         drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
 725                                     &state->base,
 726                                     &vc4_hvs_state_funcs);
 727
 728         return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
 729 }
 730
 731 /*
 732  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
 733  * the TXP (and therefore all the CRTCs found on that platform).
 734  *
 735  * The naive (and our initial) implementation would just iterate over
 736  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 737  * from the pool of available FIFOs. However, there are a few corner
 738  * cases that need to be considered:
 739  *
 740  * - When running in a dual-display setup (so with two CRTCs involved),
 741  *   we can update the state of a single CRTC (for example by changing
 742  *   its mode using xrandr under X11) without affecting the other. In
 743  *   this case, the other CRTC wouldn't be in the state at all, so we
 744  *   need to consider all the running CRTCs in the DRM device to assign
 745  *   a FIFO, not just the one in the state.
 746  *
 747  * - To fix the above, we can't use drm_atomic_get_crtc_state on all
 748  *   enabled CRTCs to pull their CRTC state into the global state, since
 749  *   a page flip would start considering their vblank to complete. Since
 750  *   we don't have a guarantee that they are actually active, that
 751  *   vblank might never happen, and shouldn't even be considered if we
 752  *   want to do a page flip on a single CRTC. That can be tested by
 753  *   doing a modetest -v first on HDMI1 and then on HDMI0.
 754  *
 755  * - Since we need the pixelvalve to be disabled and enabled back when
 756  *   the FIFO is changed, we should keep the FIFO assigned for as long
 757  *   as the CRTC is enabled, only considering it free again once that
 758  *   CRTC has been disabled. This can be tested by booting X11 on a
 759  *   single display, and changing the resolution down and then back up.
 760  */
 761 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 762                                       struct drm_atomic_state *state)
 763 {
 764         struct vc4_hvs_state *hvs_new_state;
 765         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 766         struct drm_crtc *crtc;
 767         unsigned int unassigned_channels = 0;
 768         unsigned int i;
 769
 770         hvs_new_state = vc4_hvs_get_global_state(state);
 771         if (IS_ERR(hvs_new_state))
 772                 return PTR_ERR(hvs_new_state);
 773
 774         for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
 775                 if (!hvs_new_state->fifo_state[i].in_use)
 776                         unassigned_channels |= BIT(i);
 777
 778         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 779                 struct vc4_crtc_state *old_vc4_crtc_state =
 780                         to_vc4_crtc_state(old_crtc_state);
 781                 struct vc4_crtc_state *new_vc4_crtc_state =
 782                         to_vc4_crtc_state(new_crtc_state);
 783                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 784                 unsigned int matching_channels;
 785                 unsigned int channel;
 786
 787                 /* Nothing to do here, let's skip it */
 788                 if (old_crtc_state->enable == new_crtc_state->enable)
 789                         continue;
 790
 791                 /* Muxing will need to be modified, mark it as such */
 792                 new_vc4_crtc_state->update_muxing = true;
 793
 794                 /* If we're disabling our CRTC, we put back our channel */
 795                 if (!new_crtc_state->enable) {
 796                         channel = old_vc4_crtc_state->assigned_channel;
 797                         hvs_new_state->fifo_state[channel].in_use = false;
 798                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 799                         continue;
 800                 }
 801
 802                 /*
 803                  * The problem we have to solve here is that we have
 804                  * up to 7 encoders, connected to up to 6 CRTCs.
 805                  *
 806                  * Those CRTCs, depending on the instance, can be
 807                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 808                  * the change the muxing between FIFOs and outputs in
 809                  * the HVS accordingly.
 810                  *
 811                  * It would be pretty hard to come up with an
 812                  * algorithm that would generically solve
 813                  * this. However, the current routing trees we support
 814                  * allow us to simplify a bit the problem.
 815                  *
 816                  * Indeed, with the current supported layouts, if we
 817                  * try to assign in the ascending crtc index order the
 818                  * FIFOs, we can't fall into the situation where an
 819                  * earlier CRTC that had multiple routes is assigned
 820                  * one that was the only option for a later CRTC.
 821                  *
 822                  * If the layout changes and doesn't give us that in
 823                  * the future, we will need to have something smarter,
 824                  * but it works so far.
 825                  */
 826                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 827                 if (!matching_channels)
 828                         return -EINVAL;
 829
 830                 channel = ffs(matching_channels) - 1;
 831                 new_vc4_crtc_state->assigned_channel = channel;
 832                 unassigned_channels &= ~BIT(channel);
 833                 hvs_new_state->fifo_state[channel].in_use = true;
 834         }
 835
 836         return 0;
 837 }
 838
 839 static int
 840 vc4_core_clock_atomic_check(struct drm_atomic_state *state)
 841 {
 842         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 843         struct drm_private_state *priv_state;
 844         struct vc4_hvs_state *hvs_new_state;
 845         struct vc4_load_tracker_state *load_state;
 846         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 847         struct drm_crtc *crtc;
 848         unsigned int num_outputs;
 849         unsigned long pixel_rate;
 850         unsigned long cob_rate;
 851         unsigned int i;
 852
 853         priv_state = drm_atomic_get_private_obj_state(state,
 854                                                       &vc4->load_tracker);
 855         if (IS_ERR(priv_state))
 856                 return PTR_ERR(priv_state);
 857
 858         load_state = to_vc4_load_tracker_state(priv_state);
 859
 860         hvs_new_state = vc4_hvs_get_global_state(state);
 861         if (IS_ERR(hvs_new_state))
 862                 return PTR_ERR(hvs_new_state);
 863
 864         for_each_oldnew_crtc_in_state(state, crtc,
 865                                       old_crtc_state,
 866                                       new_crtc_state,
 867                                       i) {
 868                 if (old_crtc_state->active) {
 869                         struct vc4_crtc_state *old_vc4_state =
 870                                 to_vc4_crtc_state(old_crtc_state);
 871                         unsigned int channel = old_vc4_state->assigned_channel;
 872
 873                         hvs_new_state->fifo_state[channel].fifo_load = 0;
 874                 }
 875
 876                 if (new_crtc_state->active) {
 877                         struct vc4_crtc_state *new_vc4_state =
 878                                 to_vc4_crtc_state(new_crtc_state);
 879                         unsigned int channel = new_vc4_state->assigned_channel;
 880
 881                         hvs_new_state->fifo_state[channel].fifo_load =
 882                                 new_vc4_state->hvs_load;
 883                 }
 884         }
 885
 886         cob_rate = 0;
 887         num_outputs = 0;
 888         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 889                 if (!hvs_new_state->fifo_state[i].in_use)
 890                         continue;
 891
 892                 num_outputs++;
 893                 cob_rate += hvs_new_state->fifo_state[i].fifo_load;
 894         }
 895
 896         pixel_rate = load_state->hvs_load;
 897         if (num_outputs > 1) {
 898                 pixel_rate = (pixel_rate * 40) / 100;
 899         } else {
 900                 pixel_rate = (pixel_rate * 60) / 100;
 901         }
 902
 903         hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
 904
 905         return 0;
 906 }
 907
 908
 909 static int
 910 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 911 {
 912         int ret;
 913
 914         ret = vc4_pv_muxing_atomic_check(dev, state);
 915         if (ret)
 916                 return ret;
 917
 918         ret = vc4_ctm_atomic_check(dev, state);
 919         if (ret < 0)
 920                 return ret;
 921
 922         ret = drm_atomic_helper_check(dev, state);
 923         if (ret)
 924                 return ret;
 925
 926         ret = vc4_load_tracker_atomic_check(state);
 927         if (ret)
 928                 return ret;
 929
 930         return vc4_core_clock_atomic_check(state);
 931 }
 932
 933 static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
 934         .atomic_commit_setup    = vc4_atomic_commit_setup,
 935         .atomic_commit_tail     = vc4_atomic_commit_tail,
 936 };
 937
 938 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 939         .atomic_check = vc4_atomic_check,
 940         .atomic_commit = drm_atomic_helper_commit,
 941         .fb_create = vc4_fb_create,
 942 };
 943
 944 int vc4_kms_load(struct drm_device *dev)
 945 {
 946         struct vc4_dev *vc4 = to_vc4_dev(dev);
 947         bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 948                                               "brcm,bcm2711-vc5");
 949         int ret;
 950
 951         /*
 952          * The limits enforced by the load tracker aren't relevant for
 953          * the BCM2711, but the load tracker computations are used for
 954          * the core clock rate calculation.
 955          */
 956         if (!is_vc5) {
 957                 /* Start with the load tracker enabled. Can be
 958                  * disabled through the debugfs load_tracker file.
 959                  */
 960                 vc4->load_tracker_enabled = true;
 961         }
 962
 963         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 964         dev->vblank_disable_immediate = true;
 965
 966         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 967         if (ret < 0) {
 968                 dev_err(dev->dev, "failed to initialize vblank\n");
 969                 return ret;
 970         }
 971
 972         if (is_vc5) {
 973                 dev->mode_config.max_width = 7680;
 974                 dev->mode_config.max_height = 7680;
 975         } else {
 976                 dev->mode_config.max_width = 2048;
 977                 dev->mode_config.max_height = 2048;
 978         }
 979
 980         dev->mode_config.funcs = &vc4_mode_funcs;
 981         dev->mode_config.helper_private = &vc4_mode_config_helpers;
 982         dev->mode_config.preferred_depth = 24;
 983         dev->mode_config.async_page_flip = true;
 984
 985         ret = vc4_ctm_obj_init(vc4);
 986         if (ret)
 987                 return ret;
 988
 989         ret = vc4_load_tracker_obj_init(vc4);
 990         if (ret)
 991                 return ret;
 992
 993         ret = vc4_hvs_channels_obj_init(vc4);
 994         if (ret)
 995                 return ret;
 996
 997         drm_mode_config_reset(dev);
 998
 999         drm_kms_helper_poll_init(dev);
1000
1001         return 0;
1002 }