drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <linux/clk.h>
  39 #include <linux/component.h>
  40 #include <linux/i2c.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/rational.h>
  46 #include <linux/reset.h>
  47 #include <sound/dmaengine_pcm.h>
  48 #include <sound/pcm_drm_eld.h>
  49 #include <sound/pcm_params.h>
  50 #include <sound/soc.h>
  51 #include "media/cec.h"
  52 #include "vc4_drv.h"
  53 #include "vc4_hdmi.h"
  54 #include "vc4_hdmi_regs.h"
  55 #include "vc4_regs.h"
  56
  57 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  58 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  59 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  60 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  61 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  62 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  63
  64 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  65 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  66 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  67 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  68
  69 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  70 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  71 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  72 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  73 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  74 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  75
  76 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  77 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  78
  79 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  80 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  81
  82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  84
  85 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  86
  87 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  88 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  89
  90 # define VC4_HD_M_SW_RST                        BIT(2)
  91 # define VC4_HD_M_ENABLE                        BIT(0)
  92
  93 #define CEC_CLOCK_FREQ 40000
  94 #define VC4_HSM_MID_CLOCK 149985000
  95
  96 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
  97
  98 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
  99 {
 100         struct drm_info_node *node = (struct drm_info_node *)m->private;
 101         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 102         struct drm_printer p = drm_seq_file_printer(m);
 103
 104         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 105         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 106
 107         return 0;
 108 }
 109
 110 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 111 {
 112         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 113         udelay(1);
 114         HDMI_WRITE(HDMI_M_CTL, 0);
 115
 116         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 117
 118         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 119                    VC4_HDMI_SW_RESET_HDMI |
 120                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 121
 122         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 123 }
 124
 125 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 126 {
 127         reset_control_reset(vc4_hdmi->reset);
 128
 129         HDMI_WRITE(HDMI_DVP_CTL, 0);
 130
 131         HDMI_WRITE(HDMI_CLOCK_STOP,
 132                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 133 }
 134
 135 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 136 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 137 {
 138         u16 clk_cnt;
 139         u32 value;
 140
 141         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 142         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 143
 144         /*
 145          * Set the clock divider: the hsm_clock rate and this divider
 146          * setting will give a 40 kHz CEC clock.
 147          */
 148         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 149         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 150         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 151 }
 152 #else
 153 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 154 #endif
 155
 156 static enum drm_connector_status
 157 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 158 {
 159         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 160         bool connected = false;
 161
 162         if (vc4_hdmi->hpd_gpio) {
 163                 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
 164                     vc4_hdmi->hpd_active_low)
 165                         connected = true;
 166         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 167                 connected = true;
 168         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 169                 connected = true;
 170         }
 171
 172         if (connected) {
 173                 if (connector->status != connector_status_connected) {
 174                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 175
 176                         if (edid) {
 177                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 178                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 179                                 kfree(edid);
 180                         }
 181                 }
 182
 183                 return connector_status_connected;
 184         }
 185
 186         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 187         return connector_status_disconnected;
 188 }
 189
 190 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 191 {
 192         drm_connector_unregister(connector);
 193         drm_connector_cleanup(connector);
 194 }
 195
 196 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 197 {
 198         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 199         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 200         int ret = 0;
 201         struct edid *edid;
 202
 203         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 204         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 205         if (!edid)
 206                 return -ENODEV;
 207
 208         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 209
 210         drm_connector_update_edid_property(connector, edid);
 211         ret = drm_add_edid_modes(connector, edid);
 212         kfree(edid);
 213
 214         return ret;
 215 }
 216
 217 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 218                                            struct drm_atomic_state *state)
 219 {
 220         struct drm_connector_state *old_state =
 221                 drm_atomic_get_old_connector_state(state, connector);
 222         struct drm_connector_state *new_state =
 223                 drm_atomic_get_new_connector_state(state, connector);
 224         struct drm_crtc *crtc = new_state->crtc;
 225
 226         if (!crtc)
 227                 return 0;
 228
 229         if (old_state->colorspace != new_state->colorspace ||
 230             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 231                 struct drm_crtc_state *crtc_state;
 232
 233                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 234                 if (IS_ERR(crtc_state))
 235                         return PTR_ERR(crtc_state);
 236
 237                 crtc_state->mode_changed = true;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 244 {
 245         struct vc4_hdmi_connector_state *old_state =
 246                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 247         struct vc4_hdmi_connector_state *new_state =
 248                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 249
 250         if (connector->state)
 251                 __drm_atomic_helper_connector_destroy_state(connector->state);
 252
 253         kfree(old_state);
 254         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 255
 256         if (!new_state)
 257                 return;
 258
 259         new_state->base.max_bpc = 8;
 260         new_state->base.max_requested_bpc = 8;
 261         drm_atomic_helper_connector_tv_reset(connector);
 262 }
 263
 264 static struct drm_connector_state *
 265 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 266 {
 267         struct drm_connector_state *conn_state = connector->state;
 268         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 269         struct vc4_hdmi_connector_state *new_state;
 270
 271         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 272         if (!new_state)
 273                 return NULL;
 274
 275         new_state->pixel_rate = vc4_state->pixel_rate;
 276         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 277
 278         return &new_state->base;
 279 }
 280
 281 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 282         .detect = vc4_hdmi_connector_detect,
 283         .fill_modes = drm_helper_probe_single_connector_modes,
 284         .destroy = vc4_hdmi_connector_destroy,
 285         .reset = vc4_hdmi_connector_reset,
 286         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 287         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 288 };
 289
 290 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 291         .get_modes = vc4_hdmi_connector_get_modes,
 292         .atomic_check = vc4_hdmi_connector_atomic_check,
 293 };
 294
 295 static int vc4_hdmi_connector_init(struct drm_device *dev,
 296                                    struct vc4_hdmi *vc4_hdmi)
 297 {
 298         struct drm_connector *connector = &vc4_hdmi->connector;
 299         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 300         int ret;
 301
 302         drm_connector_init_with_ddc(dev, connector,
 303                                     &vc4_hdmi_connector_funcs,
 304                                     DRM_MODE_CONNECTOR_HDMIA,
 305                                     vc4_hdmi->ddc);
 306         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 307
 308         /*
 309          * Some of the properties below require access to state, like bpc.
 310          * Allocate some default initial connector state with our reset helper.
 311          */
 312         if (connector->funcs->reset)
 313                 connector->funcs->reset(connector);
 314
 315         /* Create and attach TV margin props to this connector. */
 316         ret = drm_mode_create_tv_margin_properties(dev);
 317         if (ret)
 318                 return ret;
 319
 320         ret = drm_mode_create_hdmi_colorspace_property(connector);
 321         if (ret)
 322                 return ret;
 323
 324         drm_connector_attach_colorspace_property(connector);
 325         drm_connector_attach_tv_margin_properties(connector);
 326         drm_connector_attach_max_bpc_property(connector, 8, 12);
 327
 328         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 329                              DRM_CONNECTOR_POLL_DISCONNECT);
 330
 331         connector->interlace_allowed = 1;
 332         connector->doublescan_allowed = 0;
 333
 334         if (vc4_hdmi->variant->supports_hdr)
 335                 drm_connector_attach_hdr_output_metadata_property(connector);
 336
 337         drm_connector_attach_encoder(connector, encoder);
 338
 339         return 0;
 340 }
 341
 342 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 343                                 enum hdmi_infoframe_type type,
 344                                 bool poll)
 345 {
 346         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 347         u32 packet_id = type - 0x80;
 348
 349         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 350                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 351
 352         if (!poll)
 353                 return 0;
 354
 355         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 356                           BIT(packet_id)), 100);
 357 }
 358
 359 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 360                                      union hdmi_infoframe *frame)
 361 {
 362         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 363         u32 packet_id = frame->any.type - 0x80;
 364         const struct vc4_hdmi_register *ram_packet_start =
 365                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 366         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 367         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 368                                                        ram_packet_start->reg);
 369         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 370         ssize_t len, i;
 371         int ret;
 372
 373         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 374                     VC4_HDMI_RAM_PACKET_ENABLE),
 375                   "Packet RAM has to be on to store the packet.");
 376
 377         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 378         if (len < 0)
 379                 return;
 380
 381         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 382         if (ret) {
 383                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 384                 return;
 385         }
 386
 387         for (i = 0; i < len; i += 7) {
 388                 writel(buffer[i + 0] << 0 |
 389                        buffer[i + 1] << 8 |
 390                        buffer[i + 2] << 16,
 391                        base + packet_reg);
 392                 packet_reg += 4;
 393
 394                 writel(buffer[i + 3] << 0 |
 395                        buffer[i + 4] << 8 |
 396                        buffer[i + 5] << 16 |
 397                        buffer[i + 6] << 24,
 398                        base + packet_reg);
 399                 packet_reg += 4;
 400         }
 401
 402         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 403                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 404         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 405                         BIT(packet_id)), 100);
 406         if (ret)
 407                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 408 }
 409
 410 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 411 {
 412         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 413         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 414         struct drm_connector *connector = &vc4_hdmi->connector;
 415         struct drm_connector_state *cstate = connector->state;
 416         struct drm_crtc *crtc = encoder->crtc;
 417         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 418         union hdmi_infoframe frame;
 419         int ret;
 420
 421         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 422                                                        connector, mode);
 423         if (ret < 0) {
 424                 DRM_ERROR("couldn't fill AVI infoframe\n");
 425                 return;
 426         }
 427
 428         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 429                                            connector, mode,
 430                                            vc4_encoder->limited_rgb_range ?
 431                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 432                                            HDMI_QUANTIZATION_RANGE_FULL);
 433         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 434         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 435
 436         vc4_hdmi_write_infoframe(encoder, &frame);
 437 }
 438
 439 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 440 {
 441         union hdmi_infoframe frame;
 442         int ret;
 443
 444         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 445         if (ret < 0) {
 446                 DRM_ERROR("couldn't fill SPD infoframe\n");
 447                 return;
 448         }
 449
 450         frame.spd.sdi = HDMI_SPD_SDI_PC;
 451
 452         vc4_hdmi_write_infoframe(encoder, &frame);
 453 }
 454
 455 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 456 {
 457         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 458         union hdmi_infoframe frame;
 459
 460         hdmi_audio_infoframe_init(&frame.audio);
 461
 462         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 463         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 464         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 465         frame.audio.channels = vc4_hdmi->audio.channels;
 466
 467         vc4_hdmi_write_infoframe(encoder, &frame);
 468 }
 469
 470 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 471 {
 472         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 473         struct drm_connector *connector = &vc4_hdmi->connector;
 474         struct drm_connector_state *conn_state = connector->state;
 475         union hdmi_infoframe frame;
 476
 477         if (!vc4_hdmi->variant->supports_hdr)
 478                 return;
 479
 480         if (!conn_state->hdr_output_metadata)
 481                 return;
 482
 483         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 484                 return;
 485
 486         vc4_hdmi_write_infoframe(encoder, &frame);
 487 }
 488
 489 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 490 {
 491         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 492
 493         vc4_hdmi_set_avi_infoframe(encoder);
 494         vc4_hdmi_set_spd_infoframe(encoder);
 495         /*
 496          * If audio was streaming, then we need to reenabled the audio
 497          * infoframe here during encoder_enable.
 498          */
 499         if (vc4_hdmi->audio.streaming)
 500                 vc4_hdmi_set_audio_infoframe(encoder);
 501
 502         vc4_hdmi_set_hdr_infoframe(encoder);
 503 }
 504
 505 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 506                                                struct drm_atomic_state *state)
 507 {
 508         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 509
 510         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 511
 512         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
 513                    VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
 514
 515         HDMI_WRITE(HDMI_VID_CTL,
 516                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 517 }
 518
 519 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 520                                                  struct drm_atomic_state *state)
 521 {
 522         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 523         int ret;
 524
 525         if (vc4_hdmi->variant->phy_disable)
 526                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 527
 528         HDMI_WRITE(HDMI_VID_CTL,
 529                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 530
 531         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 532         clk_disable_unprepare(vc4_hdmi->hsm_clock);
 533         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 534
 535         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 536         if (ret < 0)
 537                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 538 }
 539
 540 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 541 {
 542 }
 543
 544 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 545 {
 546         u32 csc_ctl;
 547
 548         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 549                                 VC4_HD_CSC_CTL_ORDER);
 550
 551         if (enable) {
 552                 /* CEA VICs other than #1 requre limited range RGB
 553                  * output unless overridden by an AVI infoframe.
 554                  * Apply a colorspace conversion to squash 0-255 down
 555                  * to 16-235.  The matrix here is:
 556                  *
 557                  * [ 0      0      0.8594 16]
 558                  * [ 0      0.8594 0      16]
 559                  * [ 0.8594 0      0      16]
 560                  * [ 0      0      0       1]
 561                  */
 562                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 563                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 564                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 565                                          VC4_HD_CSC_CTL_MODE);
 566
 567                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 568                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 569                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 570                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 571                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 572                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 573         }
 574
 575         /* The RGB order applies even when CSC is disabled. */
 576         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 577 }
 578
 579 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 580 {
 581         u32 csc_ctl;
 582
 583         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 584
 585         if (enable) {
 586                 /* CEA VICs other than #1 requre limited range RGB
 587                  * output unless overridden by an AVI infoframe.
 588                  * Apply a colorspace conversion to squash 0-255 down
 589                  * to 16-235.  The matrix here is:
 590                  *
 591                  * [ 0.8594 0      0      16]
 592                  * [ 0      0.8594 0      16]
 593                  * [ 0      0      0.8594 16]
 594                  * [ 0      0      0       1]
 595                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 596                  */
 597                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 598                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 599                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 600                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 601                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 602                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 603         } else {
 604                 /* Still use the matrix for full range, but make it unity.
 605                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 606                  */
 607                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 608                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 609                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 610                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 611                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 612                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 613         }
 614
 615         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 616 }
 617
 618 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 619                                  struct drm_connector_state *state,
 620                                  struct drm_display_mode *mode)
 621 {
 622         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 623         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 624         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 625         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 626         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 627                                    VC4_HDMI_VERTA_VSP) |
 628                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 629                                    VC4_HDMI_VERTA_VFP) |
 630                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 631         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 632                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 633                                    VC4_HDMI_VERTB_VBP));
 634         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 635                           VC4_SET_FIELD(mode->crtc_vtotal -
 636                                         mode->crtc_vsync_end -
 637                                         interlaced,
 638                                         VC4_HDMI_VERTB_VBP));
 639
 640         HDMI_WRITE(HDMI_HORZA,
 641                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 642                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 643                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 644                                  VC4_HDMI_HORZA_HAP));
 645
 646         HDMI_WRITE(HDMI_HORZB,
 647                    VC4_SET_FIELD((mode->htotal -
 648                                   mode->hsync_end) * pixel_rep,
 649                                  VC4_HDMI_HORZB_HBP) |
 650                    VC4_SET_FIELD((mode->hsync_end -
 651                                   mode->hsync_start) * pixel_rep,
 652                                  VC4_HDMI_HORZB_HSP) |
 653                    VC4_SET_FIELD((mode->hsync_start -
 654                                   mode->hdisplay) * pixel_rep,
 655                                  VC4_HDMI_HORZB_HFP));
 656
 657         HDMI_WRITE(HDMI_VERTA0, verta);
 658         HDMI_WRITE(HDMI_VERTA1, verta);
 659
 660         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 661         HDMI_WRITE(HDMI_VERTB1, vertb);
 662 }
 663
 664 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 665                                  struct drm_connector_state *state,
 666                                  struct drm_display_mode *mode)
 667 {
 668         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 669         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 670         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 671         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 672         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 673                                    VC5_HDMI_VERTA_VSP) |
 674                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 675                                    VC5_HDMI_VERTA_VFP) |
 676                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 677         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 678                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 679                                    VC4_HDMI_VERTB_VBP));
 680         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 681                           VC4_SET_FIELD(mode->crtc_vtotal -
 682                                         mode->crtc_vsync_end -
 683                                         interlaced,
 684                                         VC4_HDMI_VERTB_VBP));
 685         unsigned char gcp;
 686         bool gcp_en;
 687         u32 reg;
 688
 689         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 690         HDMI_WRITE(HDMI_HORZA,
 691                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 692                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 693                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 694                                  VC5_HDMI_HORZA_HAP) |
 695                    VC4_SET_FIELD((mode->hsync_start -
 696                                   mode->hdisplay) * pixel_rep,
 697                                  VC5_HDMI_HORZA_HFP));
 698
 699         HDMI_WRITE(HDMI_HORZB,
 700                    VC4_SET_FIELD((mode->htotal -
 701                                   mode->hsync_end) * pixel_rep,
 702                                  VC5_HDMI_HORZB_HBP) |
 703                    VC4_SET_FIELD((mode->hsync_end -
 704                                   mode->hsync_start) * pixel_rep,
 705                                  VC5_HDMI_HORZB_HSP));
 706
 707         HDMI_WRITE(HDMI_VERTA0, verta);
 708         HDMI_WRITE(HDMI_VERTA1, verta);
 709
 710         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 711         HDMI_WRITE(HDMI_VERTB1, vertb);
 712
 713         switch (state->max_bpc) {
 714         case 12:
 715                 gcp = 6;
 716                 gcp_en = true;
 717                 break;
 718         case 10:
 719                 gcp = 5;
 720                 gcp_en = true;
 721                 break;
 722         case 8:
 723         default:
 724                 gcp = 4;
 725                 gcp_en = false;
 726                 break;
 727         }
 728
 729         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 730         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 731                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 732         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 733                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 734         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 735
 736         reg = HDMI_READ(HDMI_GCP_WORD_1);
 737         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 738         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 739         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 740
 741         reg = HDMI_READ(HDMI_GCP_CONFIG);
 742         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 743         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 744         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 745
 746         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 747 }
 748
 749 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 750 {
 751         u32 drift;
 752         int ret;
 753
 754         drift = HDMI_READ(HDMI_FIFO_CTL);
 755         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 756
 757         HDMI_WRITE(HDMI_FIFO_CTL,
 758                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 759         HDMI_WRITE(HDMI_FIFO_CTL,
 760                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 761         usleep_range(1000, 1100);
 762         HDMI_WRITE(HDMI_FIFO_CTL,
 763                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 764         HDMI_WRITE(HDMI_FIFO_CTL,
 765                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 766
 767         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 768                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 769         WARN_ONCE(ret, "Timeout waiting for "
 770                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 771 }
 772
 773 static struct drm_connector_state *
 774 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 775                                      struct drm_atomic_state *state)
 776 {
 777         struct drm_connector_state *conn_state;
 778         struct drm_connector *connector;
 779         unsigned int i;
 780
 781         for_each_new_connector_in_state(state, connector, conn_state, i) {
 782                 if (conn_state->best_encoder == encoder)
 783                         return conn_state;
 784         }
 785
 786         return NULL;
 787 }
 788
 789 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 790                                                 struct drm_atomic_state *state)
 791 {
 792         struct drm_connector_state *conn_state =
 793                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 794         struct vc4_hdmi_connector_state *vc4_conn_state =
 795                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 796         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 797         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 798         unsigned long pixel_rate, hsm_rate;
 799         int ret;
 800
 801         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
 802         if (ret < 0) {
 803                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 804                 return;
 805         }
 806
 807         pixel_rate = vc4_conn_state->pixel_rate;
 808         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 809         if (ret) {
 810                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 811                 return;
 812         }
 813
 814         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 815         if (ret) {
 816                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 817                 return;
 818         }
 819
 820         /*
 821          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 822          * be faster than pixel clock, infinitesimally faster, tested in
 823          * simulation. Otherwise, exact value is unimportant for HDMI
 824          * operation." This conflicts with bcm2835's vc4 documentation, which
 825          * states HSM's clock has to be at least 108% of the pixel clock.
 826          *
 827          * Real life tests reveal that vc4's firmware statement holds up, and
 828          * users are able to use pixel clocks closer to HSM's, namely for
 829          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 830          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 831          * 162MHz.
 832          *
 833          * Additionally, the AXI clock needs to be at least 25% of
 834          * pixel clock, but HSM ends up being the limiting factor.
 835          */
 836         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 837         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 838         if (ret) {
 839                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 840                 return;
 841         }
 842
 843         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
 844         if (ret) {
 845                 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
 846                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 847                 return;
 848         }
 849
 850         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 851
 852         /*
 853          * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
 854          * at 300MHz.
 855          */
 856         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
 857                                (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
 858         if (ret) {
 859                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 860                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 861                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 862                 return;
 863         }
 864
 865         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 866         if (ret) {
 867                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 868                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 869                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 870                 return;
 871         }
 872
 873         if (vc4_hdmi->variant->phy_init)
 874                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 875
 876         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 877                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 878                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 879                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 880
 881         if (vc4_hdmi->variant->set_timings)
 882                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 883 }
 884
 885 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 886                                              struct drm_atomic_state *state)
 887 {
 888         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 889         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 890         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 891
 892         if (vc4_encoder->hdmi_monitor &&
 893             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 894                 if (vc4_hdmi->variant->csc_setup)
 895                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 896
 897                 vc4_encoder->limited_rgb_range = true;
 898         } else {
 899                 if (vc4_hdmi->variant->csc_setup)
 900                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 901
 902                 vc4_encoder->limited_rgb_range = false;
 903         }
 904
 905         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 906 }
 907
 908 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
 909                                               struct drm_atomic_state *state)
 910 {
 911         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 912         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 913         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 914         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 915         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 916         int ret;
 917
 918         HDMI_WRITE(HDMI_VID_CTL,
 919                    VC4_HD_VID_CTL_ENABLE |
 920                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 921                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
 922                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 923                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 924
 925         HDMI_WRITE(HDMI_VID_CTL,
 926                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
 927
 928         if (vc4_encoder->hdmi_monitor) {
 929                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 930                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 931                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 932
 933                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 934                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 935                 WARN_ONCE(ret, "Timeout waiting for "
 936                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 937         } else {
 938                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 939                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 940                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 941                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 942                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 943                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 944
 945                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 946                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 947                 WARN_ONCE(ret, "Timeout waiting for "
 948                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 949         }
 950
 951         if (vc4_encoder->hdmi_monitor) {
 952                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 953                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 954                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 955                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 956                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 957
 958                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 959                            VC4_HDMI_RAM_PACKET_ENABLE);
 960
 961                 vc4_hdmi_set_infoframes(encoder);
 962         }
 963
 964         vc4_hdmi_recenter_fifo(vc4_hdmi);
 965 }
 966
 967 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 968 {
 969 }
 970
 971 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
 972 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
 973
 974 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 975                                          struct drm_crtc_state *crtc_state,
 976                                          struct drm_connector_state *conn_state)
 977 {
 978         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 979         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 980         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 981         unsigned long long pixel_rate = mode->clock * 1000;
 982         unsigned long long tmds_rate;
 983
 984         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 985             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 986              (mode->hsync_end % 2) || (mode->htotal % 2)))
 987                 return -EINVAL;
 988
 989         /*
 990          * The 1440p@60 pixel rate is in the same range than the first
 991          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
 992          * bandwidth). Slightly lower the frequency to bring it out of
 993          * the WiFi range.
 994          */
 995         tmds_rate = pixel_rate * 10;
 996         if (vc4_hdmi->disable_wifi_frequencies &&
 997             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
 998              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
 999                 mode->clock = 238560;
1000                 pixel_rate = mode->clock * 1000;
1001         }
1002
1003         if (conn_state->max_bpc == 12) {
1004                 pixel_rate = pixel_rate * 150;
1005                 do_div(pixel_rate, 100);
1006         } else if (conn_state->max_bpc == 10) {
1007                 pixel_rate = pixel_rate * 125;
1008                 do_div(pixel_rate, 100);
1009         }
1010
1011         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1012                 pixel_rate = pixel_rate * 2;
1013
1014         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1015                 return -EINVAL;
1016
1017         vc4_state->pixel_rate = pixel_rate;
1018
1019         return 0;
1020 }
1021
1022 static enum drm_mode_status
1023 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1024                             const struct drm_display_mode *mode)
1025 {
1026         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1027
1028         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1029             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1030              (mode->hsync_end % 2) || (mode->htotal % 2)))
1031                 return MODE_H_ILLEGAL;
1032
1033         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1034                 return MODE_CLOCK_HIGH;
1035
1036         return MODE_OK;
1037 }
1038
1039 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1040         .atomic_check = vc4_hdmi_encoder_atomic_check,
1041         .mode_valid = vc4_hdmi_encoder_mode_valid,
1042         .disable = vc4_hdmi_encoder_disable,
1043         .enable = vc4_hdmi_encoder_enable,
1044 };
1045
1046 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1047 {
1048         int i;
1049         u32 channel_map = 0;
1050
1051         for (i = 0; i < 8; i++) {
1052                 if (channel_mask & BIT(i))
1053                         channel_map |= i << (3 * i);
1054         }
1055         return channel_map;
1056 }
1057
1058 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1059 {
1060         int i;
1061         u32 channel_map = 0;
1062
1063         for (i = 0; i < 8; i++) {
1064                 if (channel_mask & BIT(i))
1065                         channel_map |= i << (4 * i);
1066         }
1067         return channel_map;
1068 }
1069
1070 /* HDMI audio codec callbacks */
1071 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1072 {
1073         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1074         unsigned long n, m;
1075
1076         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1077                                     VC4_HD_MAI_SMP_N_MASK >>
1078                                     VC4_HD_MAI_SMP_N_SHIFT,
1079                                     (VC4_HD_MAI_SMP_M_MASK >>
1080                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1081                                     &n, &m);
1082
1083         HDMI_WRITE(HDMI_MAI_SMP,
1084                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1085                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1086 }
1087
1088 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1089 {
1090         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1091         struct drm_crtc *crtc = encoder->crtc;
1092         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1093         u32 samplerate = vc4_hdmi->audio.samplerate;
1094         u32 n, cts;
1095         u64 tmp;
1096
1097         n = 128 * samplerate / 1000;
1098         tmp = (u64)(mode->clock * 1000) * n;
1099         do_div(tmp, 128 * samplerate);
1100         cts = tmp;
1101
1102         HDMI_WRITE(HDMI_CRP_CFG,
1103                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1104                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1105
1106         /*
1107          * We could get slightly more accurate clocks in some cases by
1108          * providing a CTS_1 value.  The two CTS values are alternated
1109          * between based on the period fields
1110          */
1111         HDMI_WRITE(HDMI_CTS_0, cts);
1112         HDMI_WRITE(HDMI_CTS_1, cts);
1113 }
1114
1115 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1116 {
1117         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1118
1119         return snd_soc_card_get_drvdata(card);
1120 }
1121
1122 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
1123                                   struct snd_soc_dai *dai)
1124 {
1125         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1126         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1127         struct drm_connector *connector = &vc4_hdmi->connector;
1128         int ret;
1129
1130         if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
1131                 return -EINVAL;
1132
1133         vc4_hdmi->audio.substream = substream;
1134
1135         /*
1136          * If the HDMI encoder hasn't probed, or the encoder is
1137          * currently in DVI mode, treat the codec dai as missing.
1138          */
1139         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1140                                 VC4_HDMI_RAM_PACKET_ENABLE))
1141                 return -ENODEV;
1142
1143         ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
1144         if (ret)
1145                 return ret;
1146
1147         return 0;
1148 }
1149
1150 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1151 {
1152         return 0;
1153 }
1154
1155 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1156 {
1157         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1158         struct device *dev = &vc4_hdmi->pdev->dev;
1159         int ret;
1160
1161         vc4_hdmi->audio.streaming = false;
1162         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1163         if (ret)
1164                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1165
1166         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1167         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1168         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1169 }
1170
1171 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1172                                     struct snd_soc_dai *dai)
1173 {
1174         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1175
1176         if (substream != vc4_hdmi->audio.substream)
1177                 return;
1178
1179         vc4_hdmi_audio_reset(vc4_hdmi);
1180
1181         vc4_hdmi->audio.substream = NULL;
1182 }
1183
1184 /* HDMI audio codec callbacks */
1185 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1186                                     struct snd_pcm_hw_params *params,
1187                                     struct snd_soc_dai *dai)
1188 {
1189         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1190         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1191         struct device *dev = &vc4_hdmi->pdev->dev;
1192         u32 audio_packet_config, channel_mask;
1193         u32 channel_map;
1194
1195         if (substream != vc4_hdmi->audio.substream)
1196                 return -EINVAL;
1197
1198         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1199                 params_rate(params), params_width(params),
1200                 params_channels(params));
1201
1202         vc4_hdmi->audio.channels = params_channels(params);
1203         vc4_hdmi->audio.samplerate = params_rate(params);
1204
1205         HDMI_WRITE(HDMI_MAI_CTL,
1206                    VC4_HD_MAI_CTL_RESET |
1207                    VC4_HD_MAI_CTL_FLUSH |
1208                    VC4_HD_MAI_CTL_DLATE |
1209                    VC4_HD_MAI_CTL_ERRORE |
1210                    VC4_HD_MAI_CTL_ERRORF);
1211
1212         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1213
1214         /* The B frame identifier should match the value used by alsa-lib (8) */
1215         audio_packet_config =
1216                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1217                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1218                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1219
1220         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1221         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1222                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1223
1224         /* Set the MAI threshold.  This logic mimics the firmware's. */
1225         if (vc4_hdmi->audio.samplerate > 96000) {
1226                 HDMI_WRITE(HDMI_MAI_THR,
1227                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1228                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1229         } else if (vc4_hdmi->audio.samplerate > 48000) {
1230                 HDMI_WRITE(HDMI_MAI_THR,
1231                            VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1232                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1233         } else {
1234                 HDMI_WRITE(HDMI_MAI_THR,
1235                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1236                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1237                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1238                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1239         }
1240
1241         HDMI_WRITE(HDMI_MAI_CONFIG,
1242                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1243                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1244
1245         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1246         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1247         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1248         vc4_hdmi_set_n_cts(vc4_hdmi);
1249
1250         vc4_hdmi_set_audio_infoframe(encoder);
1251
1252         return 0;
1253 }
1254
1255 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1256                                   struct snd_soc_dai *dai)
1257 {
1258         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1259
1260         switch (cmd) {
1261         case SNDRV_PCM_TRIGGER_START:
1262                 vc4_hdmi->audio.streaming = true;
1263
1264                 if (vc4_hdmi->variant->phy_rng_enable)
1265                         vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1266
1267                 HDMI_WRITE(HDMI_MAI_CTL,
1268                            VC4_SET_FIELD(vc4_hdmi->audio.channels,
1269                                          VC4_HD_MAI_CTL_CHNUM) |
1270                            VC4_HD_MAI_CTL_ENABLE);
1271                 break;
1272         case SNDRV_PCM_TRIGGER_STOP:
1273                 HDMI_WRITE(HDMI_MAI_CTL,
1274                            VC4_HD_MAI_CTL_DLATE |
1275                            VC4_HD_MAI_CTL_ERRORE |
1276                            VC4_HD_MAI_CTL_ERRORF);
1277
1278                 if (vc4_hdmi->variant->phy_rng_disable)
1279                         vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1280
1281                 vc4_hdmi->audio.streaming = false;
1282
1283                 break;
1284         default:
1285                 break;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static inline struct vc4_hdmi *
1292 snd_component_to_hdmi(struct snd_soc_component *component)
1293 {
1294         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1295
1296         return snd_soc_card_get_drvdata(card);
1297 }
1298
1299 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1300                                        struct snd_ctl_elem_info *uinfo)
1301 {
1302         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1303         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1304         struct drm_connector *connector = &vc4_hdmi->connector;
1305
1306         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1307         uinfo->count = sizeof(connector->eld);
1308
1309         return 0;
1310 }
1311
1312 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1313                                       struct snd_ctl_elem_value *ucontrol)
1314 {
1315         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1316         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1317         struct drm_connector *connector = &vc4_hdmi->connector;
1318
1319         memcpy(ucontrol->value.bytes.data, connector->eld,
1320                sizeof(connector->eld));
1321
1322         return 0;
1323 }
1324
1325 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1326         {
1327                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1328                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1329                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1330                 .name = "ELD",
1331                 .info = vc4_hdmi_audio_eld_ctl_info,
1332                 .get = vc4_hdmi_audio_eld_ctl_get,
1333         },
1334 };
1335
1336 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1337         SND_SOC_DAPM_OUTPUT("TX"),
1338 };
1339
1340 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1341         { "TX", NULL, "Playback" },
1342 };
1343
1344 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1345         .name                   = "vc4-hdmi-codec-dai-component",
1346         .controls               = vc4_hdmi_audio_controls,
1347         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1348         .dapm_widgets           = vc4_hdmi_audio_widgets,
1349         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1350         .dapm_routes            = vc4_hdmi_audio_routes,
1351         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1352         .idle_bias_on           = 1,
1353         .use_pmdown_time        = 1,
1354         .endianness             = 1,
1355         .non_legacy_dai_naming  = 1,
1356 };
1357
1358 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1359         .startup = vc4_hdmi_audio_startup,
1360         .shutdown = vc4_hdmi_audio_shutdown,
1361         .hw_params = vc4_hdmi_audio_hw_params,
1362         .set_fmt = vc4_hdmi_audio_set_fmt,
1363         .trigger = vc4_hdmi_audio_trigger,
1364 };
1365
1366 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1367         .name = "vc4-hdmi-hifi",
1368         .playback = {
1369                 .stream_name = "Playback",
1370                 .channels_min = 2,
1371                 .channels_max = 8,
1372                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1373                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1374                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1375                          SNDRV_PCM_RATE_192000,
1376                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1377         },
1378 };
1379
1380 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1381         .name = "vc4-hdmi-cpu-dai-component",
1382 };
1383
1384 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1385 {
1386         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1387
1388         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1389
1390         return 0;
1391 }
1392
1393 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1394         .name = "vc4-hdmi-cpu-dai",
1395         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1396         .playback = {
1397                 .stream_name = "Playback",
1398                 .channels_min = 1,
1399                 .channels_max = 8,
1400                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1401                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1402                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1403                          SNDRV_PCM_RATE_192000,
1404                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1405         },
1406         .ops = &vc4_hdmi_audio_dai_ops,
1407 };
1408
1409 static const struct snd_dmaengine_pcm_config pcm_conf = {
1410         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1411         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1412 };
1413
1414 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1415 {
1416         const struct vc4_hdmi_register *mai_data =
1417                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1418         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1419         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1420         struct device *dev = &vc4_hdmi->pdev->dev;
1421         const __be32 *addr;
1422         int index;
1423         int ret;
1424
1425         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1426                 dev_warn(dev,
1427                          "'dmas' DT property is missing, no HDMI audio\n");
1428                 return 0;
1429         }
1430
1431         if (mai_data->reg != VC4_HD) {
1432                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1433                 return -EINVAL;
1434         }
1435
1436         /*
1437          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1438          * the bus address specified in the DT, because the physical address
1439          * (the one returned by platform_get_resource()) is not appropriate
1440          * for DMA transfers.
1441          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1442          */
1443         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1444         /* Before BCM2711, we don't have a named register range */
1445         if (index < 0)
1446                 index = 1;
1447
1448         addr = of_get_address(dev->of_node, index, NULL, NULL);
1449
1450         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1451         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1452         vc4_hdmi->audio.dma_data.maxburst = 2;
1453
1454         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1455         if (ret) {
1456                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1457                 return ret;
1458         }
1459
1460         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1461                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1462         if (ret) {
1463                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1464                 return ret;
1465         }
1466
1467         /* register component and codec dai */
1468         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1469                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1470         if (ret) {
1471                 dev_err(dev, "Could not register component: %d\n", ret);
1472                 return ret;
1473         }
1474
1475         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1476         dai_link->codecs        = &vc4_hdmi->audio.codec;
1477         dai_link->platforms     = &vc4_hdmi->audio.platform;
1478
1479         dai_link->num_cpus      = 1;
1480         dai_link->num_codecs    = 1;
1481         dai_link->num_platforms = 1;
1482
1483         dai_link->name = "MAI";
1484         dai_link->stream_name = "MAI PCM";
1485         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1486         dai_link->cpus->dai_name = dev_name(dev);
1487         dai_link->codecs->name = dev_name(dev);
1488         dai_link->platforms->name = dev_name(dev);
1489
1490         card->dai_link = dai_link;
1491         card->num_links = 1;
1492         card->name = vc4_hdmi->variant->card_name;
1493         card->driver_name = "vc4-hdmi";
1494         card->dev = dev;
1495         card->owner = THIS_MODULE;
1496
1497         /*
1498          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1499          * stores a pointer to the snd card object in dev->driver_data. This
1500          * means we cannot use it for something else. The hdmi back-pointer is
1501          * now stored in card->drvdata and should be retrieved with
1502          * snd_soc_card_get_drvdata() if needed.
1503          */
1504         snd_soc_card_set_drvdata(card, vc4_hdmi);
1505         ret = devm_snd_soc_register_card(dev, card);
1506         if (ret)
1507                 dev_err(dev, "Could not register sound card: %d\n", ret);
1508
1509         return ret;
1510
1511 }
1512
1513 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1514 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1515 {
1516         struct vc4_hdmi *vc4_hdmi = priv;
1517
1518         if (vc4_hdmi->cec_rx_msg.len)
1519                 cec_received_msg(vc4_hdmi->cec_adap,
1520                                  &vc4_hdmi->cec_rx_msg);
1521
1522         return IRQ_HANDLED;
1523 }
1524
1525 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1526 {
1527         struct vc4_hdmi *vc4_hdmi = priv;
1528
1529         if (vc4_hdmi->cec_tx_ok) {
1530                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1531                                   0, 0, 0, 0);
1532         } else {
1533                 /*
1534                  * This CEC implementation makes 1 retry, so if we
1535                  * get a NACK, then that means it made 2 attempts.
1536                  */
1537                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1538                                   0, 2, 0, 0);
1539         }
1540         return IRQ_HANDLED;
1541 }
1542
1543 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1544 {
1545         struct vc4_hdmi *vc4_hdmi = priv;
1546         irqreturn_t ret;
1547
1548         if (vc4_hdmi->cec_irq_was_rx)
1549                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1550         else
1551                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1552
1553         return ret;
1554 }
1555
1556 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1557 {
1558         struct drm_device *dev = vc4_hdmi->connector.dev;
1559         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1560         unsigned int i;
1561
1562         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1563                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1564
1565         if (msg->len > 16) {
1566                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1567                 return;
1568         }
1569
1570         for (i = 0; i < msg->len; i += 4) {
1571                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1572
1573                 msg->msg[i] = val & 0xff;
1574                 msg->msg[i + 1] = (val >> 8) & 0xff;
1575                 msg->msg[i + 2] = (val >> 16) & 0xff;
1576                 msg->msg[i + 3] = (val >> 24) & 0xff;
1577         }
1578 }
1579
1580 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1581 {
1582         struct vc4_hdmi *vc4_hdmi = priv;
1583         u32 cntrl1;
1584
1585         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1586         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1587         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1588         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1589
1590         return IRQ_WAKE_THREAD;
1591 }
1592
1593 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1594 {
1595         struct vc4_hdmi *vc4_hdmi = priv;
1596         u32 cntrl1;
1597
1598         vc4_hdmi->cec_rx_msg.len = 0;
1599         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1600         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1601         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1602         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1603         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1604
1605         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1606
1607         return IRQ_WAKE_THREAD;
1608 }
1609
1610 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1611 {
1612         struct vc4_hdmi *vc4_hdmi = priv;
1613         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1614         irqreturn_t ret;
1615         u32 cntrl5;
1616
1617         if (!(stat & VC4_HDMI_CPU_CEC))
1618                 return IRQ_NONE;
1619
1620         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1621         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1622         if (vc4_hdmi->cec_irq_was_rx)
1623                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1624         else
1625                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1626
1627         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1628         return ret;
1629 }
1630
1631 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1632 {
1633         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1634         /* clock period in microseconds */
1635         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1636         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1637
1638         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1639                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1640                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1641         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1642                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1643
1644         if (enable) {
1645                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1646                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1647                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1648                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1649                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1650                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1651                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1652                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1653                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1654                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1655                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1656                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1657                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1658                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1659                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1660                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1661                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1662                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1663                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1664
1665                 if (!vc4_hdmi->variant->external_irq_controller)
1666                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1667         } else {
1668                 if (!vc4_hdmi->variant->external_irq_controller)
1669                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1670                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1671                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1672         }
1673         return 0;
1674 }
1675
1676 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1677 {
1678         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1679
1680         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1681                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1682                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1683         return 0;
1684 }
1685
1686 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1687                                       u32 signal_free_time, struct cec_msg *msg)
1688 {
1689         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1690         struct drm_device *dev = vc4_hdmi->connector.dev;
1691         u32 val;
1692         unsigned int i;
1693
1694         if (msg->len > 16) {
1695                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1696                 return -ENOMEM;
1697         }
1698
1699         for (i = 0; i < msg->len; i += 4)
1700                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1701                            (msg->msg[i]) |
1702                            (msg->msg[i + 1] << 8) |
1703                            (msg->msg[i + 2] << 16) |
1704                            (msg->msg[i + 3] << 24));
1705
1706         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1707         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1708         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1709         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1710         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1711         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1712
1713         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1714         return 0;
1715 }
1716
1717 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1718         .adap_enable = vc4_hdmi_cec_adap_enable,
1719         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1720         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1721 };
1722
1723 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1724 {
1725         struct cec_connector_info conn_info;
1726         struct platform_device *pdev = vc4_hdmi->pdev;
1727         struct device *dev = &pdev->dev;
1728         u32 value;
1729         int ret;
1730
1731         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1732                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1733                 return 0;
1734         }
1735
1736         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1737                                                   vc4_hdmi, "vc4",
1738                                                   CEC_CAP_DEFAULTS |
1739                                                   CEC_CAP_CONNECTOR_INFO, 1);
1740         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1741         if (ret < 0)
1742                 return ret;
1743
1744         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1745         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1746
1747         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1748         /* Set the logical address to Unregistered */
1749         value |= VC4_HDMI_CEC_ADDR_MASK;
1750         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1751
1752         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1753
1754         if (vc4_hdmi->variant->external_irq_controller) {
1755                 ret = devm_request_threaded_irq(&pdev->dev,
1756                                                 platform_get_irq_byname(pdev, "cec-rx"),
1757                                                 vc4_cec_irq_handler_rx_bare,
1758                                                 vc4_cec_irq_handler_rx_thread, 0,
1759                                                 "vc4 hdmi cec rx", vc4_hdmi);
1760                 if (ret)
1761                         goto err_delete_cec_adap;
1762
1763                 ret = devm_request_threaded_irq(&pdev->dev,
1764                                                 platform_get_irq_byname(pdev, "cec-tx"),
1765                                                 vc4_cec_irq_handler_tx_bare,
1766                                                 vc4_cec_irq_handler_tx_thread, 0,
1767                                                 "vc4 hdmi cec tx", vc4_hdmi);
1768                 if (ret)
1769                         goto err_delete_cec_adap;
1770         } else {
1771                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1772
1773                 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1774                                                 vc4_cec_irq_handler,
1775                                                 vc4_cec_irq_handler_thread, 0,
1776                                                 "vc4 hdmi cec", vc4_hdmi);
1777                 if (ret)
1778                         goto err_delete_cec_adap;
1779         }
1780
1781         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1782         if (ret < 0)
1783                 goto err_delete_cec_adap;
1784
1785         return 0;
1786
1787 err_delete_cec_adap:
1788         cec_delete_adapter(vc4_hdmi->cec_adap);
1789
1790         return ret;
1791 }
1792
1793 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1794 {
1795         cec_unregister_adapter(vc4_hdmi->cec_adap);
1796 }
1797 #else
1798 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1799 {
1800         return 0;
1801 }
1802
1803 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1804
1805 #endif
1806
1807 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1808                                  struct debugfs_regset32 *regset,
1809                                  enum vc4_hdmi_regs reg)
1810 {
1811         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1812         struct debugfs_reg32 *regs, *new_regs;
1813         unsigned int count = 0;
1814         unsigned int i;
1815
1816         regs = kcalloc(variant->num_registers, sizeof(*regs),
1817                        GFP_KERNEL);
1818         if (!regs)
1819                 return -ENOMEM;
1820
1821         for (i = 0; i < variant->num_registers; i++) {
1822                 const struct vc4_hdmi_register *field = &variant->registers[i];
1823
1824                 if (field->reg != reg)
1825                         continue;
1826
1827                 regs[count].name = field->name;
1828                 regs[count].offset = field->offset;
1829                 count++;
1830         }
1831
1832         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1833         if (!new_regs)
1834                 return -ENOMEM;
1835
1836         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1837         regset->regs = new_regs;
1838         regset->nregs = count;
1839
1840         return 0;
1841 }
1842
1843 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1844 {
1845         struct platform_device *pdev = vc4_hdmi->pdev;
1846         struct device *dev = &pdev->dev;
1847         int ret;
1848
1849         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1850         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1851                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1852
1853         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1854         if (IS_ERR(vc4_hdmi->hd_regs))
1855                 return PTR_ERR(vc4_hdmi->hd_regs);
1856
1857         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1858         if (ret)
1859                 return ret;
1860
1861         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1862         if (ret)
1863                 return ret;
1864
1865         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1866         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1867                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1868                 if (ret != -EPROBE_DEFER)
1869                         DRM_ERROR("Failed to get pixel clock\n");
1870                 return ret;
1871         }
1872
1873         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1874         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1875                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1876                 return PTR_ERR(vc4_hdmi->hsm_clock);
1877         }
1878         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1879         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
1880
1881         return 0;
1882 }
1883
1884 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1885 {
1886         struct platform_device *pdev = vc4_hdmi->pdev;
1887         struct device *dev = &pdev->dev;
1888         struct resource *res;
1889
1890         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1891         if (!res)
1892                 return -ENODEV;
1893
1894         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1895                                                resource_size(res));
1896         if (!vc4_hdmi->hdmicore_regs)
1897                 return -ENOMEM;
1898
1899         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1900         if (!res)
1901                 return -ENODEV;
1902
1903         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1904         if (!vc4_hdmi->hd_regs)
1905                 return -ENOMEM;
1906
1907         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1908         if (!res)
1909                 return -ENODEV;
1910
1911         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1912         if (!vc4_hdmi->cec_regs)
1913                 return -ENOMEM;
1914
1915         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1916         if (!res)
1917                 return -ENODEV;
1918
1919         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1920         if (!vc4_hdmi->csc_regs)
1921                 return -ENOMEM;
1922
1923         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1924         if (!res)
1925                 return -ENODEV;
1926
1927         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1928         if (!vc4_hdmi->dvp_regs)
1929                 return -ENOMEM;
1930
1931         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1932         if (!res)
1933                 return -ENODEV;
1934
1935         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1936         if (!vc4_hdmi->phy_regs)
1937                 return -ENOMEM;
1938
1939         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1940         if (!res)
1941                 return -ENODEV;
1942
1943         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1944         if (!vc4_hdmi->ram_regs)
1945                 return -ENOMEM;
1946
1947         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1948         if (!res)
1949                 return -ENODEV;
1950
1951         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1952         if (!vc4_hdmi->rm_regs)
1953                 return -ENOMEM;
1954
1955         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1956         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1957                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1958                 return PTR_ERR(vc4_hdmi->hsm_clock);
1959         }
1960
1961         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1962         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1963                 DRM_ERROR("Failed to get pixel bvb clock\n");
1964                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1965         }
1966
1967         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1968         if (IS_ERR(vc4_hdmi->audio_clock)) {
1969                 DRM_ERROR("Failed to get audio clock\n");
1970                 return PTR_ERR(vc4_hdmi->audio_clock);
1971         }
1972
1973         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
1974         if (IS_ERR(vc4_hdmi->cec_clock)) {
1975                 DRM_ERROR("Failed to get CEC clock\n");
1976                 return PTR_ERR(vc4_hdmi->cec_clock);
1977         }
1978
1979         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1980         if (IS_ERR(vc4_hdmi->reset)) {
1981                 DRM_ERROR("Failed to get HDMI reset line\n");
1982                 return PTR_ERR(vc4_hdmi->reset);
1983         }
1984
1985         return 0;
1986 }
1987
1988 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1989 {
1990         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1991         struct platform_device *pdev = to_platform_device(dev);
1992         struct drm_device *drm = dev_get_drvdata(master);
1993         struct vc4_hdmi *vc4_hdmi;
1994         struct drm_encoder *encoder;
1995         struct device_node *ddc_node;
1996         u32 value;
1997         int ret;
1998
1999         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2000         if (!vc4_hdmi)
2001                 return -ENOMEM;
2002
2003         dev_set_drvdata(dev, vc4_hdmi);
2004         encoder = &vc4_hdmi->encoder.base.base;
2005         vc4_hdmi->encoder.base.type = variant->encoder_type;
2006         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2007         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2008         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2009         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2010         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2011         vc4_hdmi->pdev = pdev;
2012         vc4_hdmi->variant = variant;
2013
2014         ret = variant->init_resources(vc4_hdmi);
2015         if (ret)
2016                 return ret;
2017
2018         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2019         if (!ddc_node) {
2020                 DRM_ERROR("Failed to find ddc node in device tree\n");
2021                 return -ENODEV;
2022         }
2023
2024         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2025         of_node_put(ddc_node);
2026         if (!vc4_hdmi->ddc) {
2027                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2028                 return -EPROBE_DEFER;
2029         }
2030
2031         /* Only use the GPIO HPD pin if present in the DT, otherwise
2032          * we'll use the HDMI core's register.
2033          */
2034         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
2035                 enum of_gpio_flags hpd_gpio_flags;
2036
2037                 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2038                                                              "hpd-gpios", 0,
2039                                                              &hpd_gpio_flags);
2040                 if (vc4_hdmi->hpd_gpio < 0) {
2041                         ret = vc4_hdmi->hpd_gpio;
2042                         goto err_unprepare_hsm;
2043                 }
2044
2045                 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
2046         }
2047
2048         vc4_hdmi->disable_wifi_frequencies =
2049                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2050
2051         if (vc4_hdmi->variant->reset)
2052                 vc4_hdmi->variant->reset(vc4_hdmi);
2053
2054         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2055              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2056             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2057                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2058                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2059                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2060         }
2061
2062         pm_runtime_enable(dev);
2063
2064         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2065         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2066
2067         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2068         if (ret)
2069                 goto err_destroy_encoder;
2070
2071         ret = vc4_hdmi_cec_init(vc4_hdmi);
2072         if (ret)
2073                 goto err_destroy_conn;
2074
2075         ret = vc4_hdmi_audio_init(vc4_hdmi);
2076         if (ret)
2077                 goto err_free_cec;
2078
2079         vc4_debugfs_add_file(drm, variant->debugfs_name,
2080                              vc4_hdmi_debugfs_regs,
2081                              vc4_hdmi);
2082
2083         return 0;
2084
2085 err_free_cec:
2086         vc4_hdmi_cec_exit(vc4_hdmi);
2087 err_destroy_conn:
2088         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2089 err_destroy_encoder:
2090         drm_encoder_cleanup(encoder);
2091 err_unprepare_hsm:
2092         pm_runtime_disable(dev);
2093         put_device(&vc4_hdmi->ddc->dev);
2094
2095         return ret;
2096 }
2097
2098 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2099                             void *data)
2100 {
2101         struct vc4_hdmi *vc4_hdmi;
2102
2103         /*
2104          * ASoC makes it a bit hard to retrieve a pointer to the
2105          * vc4_hdmi structure. Registering the card will overwrite our
2106          * device drvdata with a pointer to the snd_soc_card structure,
2107          * which can then be used to retrieve whatever drvdata we want
2108          * to associate.
2109          *
2110          * However, that doesn't fly in the case where we wouldn't
2111          * register an ASoC card (because of an old DT that is missing
2112          * the dmas properties for example), then the card isn't
2113          * registered and the device drvdata wouldn't be set.
2114          *
2115          * We can deal with both cases by making sure a snd_soc_card
2116          * pointer and a vc4_hdmi structure are pointing to the same
2117          * memory address, so we can treat them indistinctly without any
2118          * issue.
2119          */
2120         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2121         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2122         vc4_hdmi = dev_get_drvdata(dev);
2123
2124         kfree(vc4_hdmi->hdmi_regset.regs);
2125         kfree(vc4_hdmi->hd_regset.regs);
2126
2127         vc4_hdmi_cec_exit(vc4_hdmi);
2128         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2129         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2130
2131         pm_runtime_disable(dev);
2132
2133         put_device(&vc4_hdmi->ddc->dev);
2134 }
2135
2136 static const struct component_ops vc4_hdmi_ops = {
2137         .bind   = vc4_hdmi_bind,
2138         .unbind = vc4_hdmi_unbind,
2139 };
2140
2141 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2142 {
2143         return component_add(&pdev->dev, &vc4_hdmi_ops);
2144 }
2145
2146 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2147 {
2148         component_del(&pdev->dev, &vc4_hdmi_ops);
2149         return 0;
2150 }
2151
2152 static const struct vc4_hdmi_variant bcm2835_variant = {
2153         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2154         .debugfs_name           = "hdmi_regs",
2155         .card_name              = "vc4-hdmi",
2156         .max_pixel_clock        = 162000000,
2157         .registers              = vc4_hdmi_fields,
2158         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2159
2160         .init_resources         = vc4_hdmi_init_resources,
2161         .csc_setup              = vc4_hdmi_csc_setup,
2162         .reset                  = vc4_hdmi_reset,
2163         .set_timings            = vc4_hdmi_set_timings,
2164         .phy_init               = vc4_hdmi_phy_init,
2165         .phy_disable            = vc4_hdmi_phy_disable,
2166         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2167         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2168         .channel_map            = vc4_hdmi_channel_map,
2169         .supports_hdr           = false,
2170 };
2171
2172 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2173         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2174         .debugfs_name           = "hdmi0_regs",
2175         .card_name              = "vc4-hdmi-0",
2176         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2177         .registers              = vc5_hdmi_hdmi0_fields,
2178         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2179         .phy_lane_mapping       = {
2180                 PHY_LANE_0,
2181                 PHY_LANE_1,
2182                 PHY_LANE_2,
2183                 PHY_LANE_CK,
2184         },
2185         .unsupported_odd_h_timings      = true,
2186         .external_irq_controller        = true,
2187
2188         .init_resources         = vc5_hdmi_init_resources,
2189         .csc_setup              = vc5_hdmi_csc_setup,
2190         .reset                  = vc5_hdmi_reset,
2191         .set_timings            = vc5_hdmi_set_timings,
2192         .phy_init               = vc5_hdmi_phy_init,
2193         .phy_disable            = vc5_hdmi_phy_disable,
2194         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2195         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2196         .channel_map            = vc5_hdmi_channel_map,
2197         .supports_hdr           = true,
2198 };
2199
2200 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2201         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2202         .debugfs_name           = "hdmi1_regs",
2203         .card_name              = "vc4-hdmi-1",
2204         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2205         .registers              = vc5_hdmi_hdmi1_fields,
2206         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2207         .phy_lane_mapping       = {
2208                 PHY_LANE_1,
2209                 PHY_LANE_0,
2210                 PHY_LANE_CK,
2211                 PHY_LANE_2,
2212         },
2213         .unsupported_odd_h_timings      = true,
2214         .external_irq_controller        = true,
2215
2216         .init_resources         = vc5_hdmi_init_resources,
2217         .csc_setup              = vc5_hdmi_csc_setup,
2218         .reset                  = vc5_hdmi_reset,
2219         .set_timings            = vc5_hdmi_set_timings,
2220         .phy_init               = vc5_hdmi_phy_init,
2221         .phy_disable            = vc5_hdmi_phy_disable,
2222         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2223         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2224         .channel_map            = vc5_hdmi_channel_map,
2225         .supports_hdr           = true,
2226 };
2227
2228 static const struct of_device_id vc4_hdmi_dt_match[] = {
2229         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2230         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2231         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2232         {}
2233 };
2234
2235 struct platform_driver vc4_hdmi_driver = {
2236         .probe = vc4_hdmi_dev_probe,
2237         .remove = vc4_hdmi_dev_remove,
2238         .driver = {
2239                 .name = "vc4_hdmi",
2240                 .of_match_table = vc4_hdmi_dt_match,
2241         },
2242 };