1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_scdc_helper.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_drv.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_simple_kms_helper.h>
40 #include <linux/clk.h>
41 #include <linux/component.h>
42 #include <linux/gpio/consumer.h>
43 #include <linux/i2c.h>
44 #include <linux/of_address.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
57 #include "vc4_hdmi_regs.h"
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
104 # define VC4_HD_M_SW_RST BIT(2)
105 # define VC4_HD_M_ENABLE BIT(0)
107 #define HSM_MIN_CLOCK_FREQ 120000000
108 #define CEC_CLOCK_FREQ 40000
110 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
112 static const char * const output_format_str[] = {
113 [VC4_HDMI_OUTPUT_RGB] = "RGB",
114 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
115 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
116 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
119 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
121 if (fmt >= ARRAY_SIZE(output_format_str))
124 return output_format_str[fmt];
127 static unsigned long long
128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
129 unsigned int bpc, enum vc4_hdmi_output_format fmt);
131 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
133 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
135 lockdep_assert_held(&vc4_hdmi->mutex);
137 if (!display->is_hdmi)
140 if (!display->hdmi.scdc.supported ||
141 !display->hdmi.scdc.scrambling.supported)
147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
149 enum vc4_hdmi_output_format fmt)
151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
153 return clock > HDMI_14_MAX_TMDS_CLK;
156 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
157 const struct drm_display_mode *mode)
159 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
161 return !display->is_hdmi ||
162 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
165 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
167 struct drm_debugfs_entry *entry = m->private;
168 struct vc4_hdmi *vc4_hdmi = entry->file.data;
169 struct drm_device *drm = vc4_hdmi->connector.dev;
170 struct drm_printer p = drm_seq_file_printer(m);
173 if (!drm_dev_enter(drm, &idx))
176 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
177 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
178 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
179 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
180 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
181 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
182 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
183 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
190 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
192 struct drm_device *drm = vc4_hdmi->connector.dev;
197 * We can be called by our bind callback, when the
198 * connector->dev pointer might not be initialised yet.
200 if (drm && !drm_dev_enter(drm, &idx))
203 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
205 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
207 HDMI_WRITE(HDMI_M_CTL, 0);
209 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
211 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
212 VC4_HDMI_SW_RESET_HDMI |
213 VC4_HDMI_SW_RESET_FORMAT_DETECT);
215 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
217 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
223 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
225 struct drm_device *drm = vc4_hdmi->connector.dev;
230 * We can be called by our bind callback, when the
231 * connector->dev pointer might not be initialised yet.
233 if (drm && !drm_dev_enter(drm, &idx))
236 reset_control_reset(vc4_hdmi->reset);
238 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
240 HDMI_WRITE(HDMI_DVP_CTL, 0);
242 HDMI_WRITE(HDMI_CLOCK_STOP,
243 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
245 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
251 #ifdef CONFIG_DRM_VC4_HDMI_CEC
252 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
254 struct drm_device *drm = vc4_hdmi->connector.dev;
255 unsigned long cec_rate;
262 * This function is called by our runtime_resume implementation
263 * and thus at bind time, when we haven't registered our
264 * connector yet and thus don't have a pointer to the DRM
267 if (drm && !drm_dev_enter(drm, &idx))
270 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
272 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
274 value = HDMI_READ(HDMI_CEC_CNTRL_1);
275 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
278 * Set the clock divider: the hsm_clock rate and this divider
279 * setting will give a 40 kHz CEC clock.
281 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
282 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
283 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
285 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
291 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
294 static int reset_pipe(struct drm_crtc *crtc,
295 struct drm_modeset_acquire_ctx *ctx)
297 struct drm_atomic_state *state;
298 struct drm_crtc_state *crtc_state;
301 state = drm_atomic_state_alloc(crtc->dev);
305 state->acquire_ctx = ctx;
307 crtc_state = drm_atomic_get_crtc_state(state, crtc);
308 if (IS_ERR(crtc_state)) {
309 ret = PTR_ERR(crtc_state);
313 crtc_state->connectors_changed = true;
315 ret = drm_atomic_commit(state);
317 drm_atomic_state_put(state);
322 static int vc4_hdmi_reset_link(struct drm_connector *connector,
323 struct drm_modeset_acquire_ctx *ctx)
325 struct drm_device *drm;
326 struct vc4_hdmi *vc4_hdmi;
327 struct drm_connector_state *conn_state;
328 struct drm_crtc_state *crtc_state;
329 struct drm_crtc *crtc;
330 bool scrambling_needed;
337 drm = connector->dev;
338 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
342 conn_state = connector->state;
343 crtc = conn_state->crtc;
347 ret = drm_modeset_lock(&crtc->mutex, ctx);
351 crtc_state = crtc->state;
352 if (!crtc_state->active)
355 vc4_hdmi = connector_to_vc4_hdmi(connector);
356 mutex_lock(&vc4_hdmi->mutex);
358 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
359 mutex_unlock(&vc4_hdmi->mutex);
363 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
364 vc4_hdmi->output_bpc,
365 vc4_hdmi->output_format);
366 if (!scrambling_needed) {
367 mutex_unlock(&vc4_hdmi->mutex);
371 if (conn_state->commit &&
372 !try_wait_for_completion(&conn_state->commit->hw_done)) {
373 mutex_unlock(&vc4_hdmi->mutex);
377 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
379 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
380 mutex_unlock(&vc4_hdmi->mutex);
384 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
385 mutex_unlock(&vc4_hdmi->mutex);
389 mutex_unlock(&vc4_hdmi->mutex);
392 * HDMI 2.0 says that one should not send scrambled data
393 * prior to configuring the sink scrambling, and that
394 * TMDS clock/data transmission should be suspended when
395 * changing the TMDS clock rate in the sink. So let's
396 * just do a full modeset here, even though some sinks
397 * would be perfectly happy if were to just reconfigure
398 * the SCDC settings on the fly.
400 return reset_pipe(crtc, ctx);
403 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
404 struct drm_modeset_acquire_ctx *ctx,
405 enum drm_connector_status status)
407 struct drm_connector *connector = &vc4_hdmi->connector;
412 * NOTE: This function should really be called with
413 * vc4_hdmi->mutex held, but doing so results in reentrancy
414 * issues since cec_s_phys_addr_from_edid might call
415 * .adap_enable, which leads to that funtion being called with
418 * A similar situation occurs with vc4_hdmi_reset_link() that
419 * will call into our KMS hooks if the scrambling was enabled.
421 * Concurrency isn't an issue at the moment since we don't share
422 * any state with any of the other frameworks so we can ignore
426 if (status == connector_status_disconnected) {
427 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
431 edid = drm_get_edid(connector, vc4_hdmi->ddc);
435 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
439 ret = vc4_hdmi_reset_link(connector, ctx);
440 if (ret == -EDEADLK) {
441 drm_modeset_backoff(ctx);
449 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
450 struct drm_modeset_acquire_ctx *ctx,
453 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
454 enum drm_connector_status status = connector_status_disconnected;
457 * NOTE: This function should really take vc4_hdmi->mutex, but
458 * doing so results in reentrancy issues since
459 * vc4_hdmi_handle_hotplug() can call into other functions that
460 * would take the mutex while it's held here.
462 * Concurrency isn't an issue at the moment since we don't share
463 * any state with any of the other frameworks so we can ignore
467 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
469 if (vc4_hdmi->hpd_gpio) {
470 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
471 status = connector_status_connected;
473 if (vc4_hdmi->variant->hp_detect &&
474 vc4_hdmi->variant->hp_detect(vc4_hdmi))
475 status = connector_status_connected;
478 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
479 pm_runtime_put(&vc4_hdmi->pdev->dev);
484 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
486 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
487 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
492 * NOTE: This function should really take vc4_hdmi->mutex, but
493 * doing so results in reentrancy issues since
494 * cec_s_phys_addr_from_edid might call .adap_enable, which
495 * leads to that funtion being called with our mutex held.
497 * Concurrency isn't an issue at the moment since we don't share
498 * any state with any of the other frameworks so we can ignore
502 edid = drm_get_edid(connector, vc4_hdmi->ddc);
503 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
507 drm_connector_update_edid_property(connector, edid);
508 ret = drm_add_edid_modes(connector, edid);
511 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
512 struct drm_device *drm = connector->dev;
513 const struct drm_display_mode *mode;
515 list_for_each_entry(mode, &connector->probed_modes, head) {
516 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
517 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
518 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
526 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
527 struct drm_atomic_state *state)
529 struct drm_connector_state *old_state =
530 drm_atomic_get_old_connector_state(state, connector);
531 struct drm_connector_state *new_state =
532 drm_atomic_get_new_connector_state(state, connector);
533 struct drm_crtc *crtc = new_state->crtc;
538 if (old_state->colorspace != new_state->colorspace ||
539 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
540 struct drm_crtc_state *crtc_state;
542 crtc_state = drm_atomic_get_crtc_state(state, crtc);
543 if (IS_ERR(crtc_state))
544 return PTR_ERR(crtc_state);
546 crtc_state->mode_changed = true;
552 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
554 struct vc4_hdmi_connector_state *old_state =
555 conn_state_to_vc4_hdmi_conn_state(connector->state);
556 struct vc4_hdmi_connector_state *new_state =
557 kzalloc(sizeof(*new_state), GFP_KERNEL);
559 if (connector->state)
560 __drm_atomic_helper_connector_destroy_state(connector->state);
563 __drm_atomic_helper_connector_reset(connector, &new_state->base);
568 new_state->base.max_bpc = 8;
569 new_state->base.max_requested_bpc = 8;
570 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
571 drm_atomic_helper_connector_tv_margins_reset(connector);
574 static struct drm_connector_state *
575 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
577 struct drm_connector_state *conn_state = connector->state;
578 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
579 struct vc4_hdmi_connector_state *new_state;
581 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
585 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
586 new_state->output_bpc = vc4_state->output_bpc;
587 new_state->output_format = vc4_state->output_format;
588 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
590 return &new_state->base;
593 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
594 .fill_modes = drm_helper_probe_single_connector_modes,
595 .reset = vc4_hdmi_connector_reset,
596 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
597 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
600 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
601 .detect_ctx = vc4_hdmi_connector_detect_ctx,
602 .get_modes = vc4_hdmi_connector_get_modes,
603 .atomic_check = vc4_hdmi_connector_atomic_check,
606 static int vc4_hdmi_connector_init(struct drm_device *dev,
607 struct vc4_hdmi *vc4_hdmi)
609 struct drm_connector *connector = &vc4_hdmi->connector;
610 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
613 ret = drmm_connector_init(dev, connector,
614 &vc4_hdmi_connector_funcs,
615 DRM_MODE_CONNECTOR_HDMIA,
620 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
623 * Some of the properties below require access to state, like bpc.
624 * Allocate some default initial connector state with our reset helper.
626 if (connector->funcs->reset)
627 connector->funcs->reset(connector);
629 /* Create and attach TV margin props to this connector. */
630 ret = drm_mode_create_tv_margin_properties(dev);
634 ret = drm_mode_create_hdmi_colorspace_property(connector);
638 drm_connector_attach_colorspace_property(connector);
639 drm_connector_attach_tv_margin_properties(connector);
640 drm_connector_attach_max_bpc_property(connector, 8, 12);
642 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
643 DRM_CONNECTOR_POLL_DISCONNECT);
645 connector->interlace_allowed = 1;
646 connector->doublescan_allowed = 0;
647 connector->stereo_allowed = 1;
649 if (vc4_hdmi->variant->supports_hdr)
650 drm_connector_attach_hdr_output_metadata_property(connector);
652 drm_connector_attach_encoder(connector, encoder);
657 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
658 enum hdmi_infoframe_type type,
661 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
662 struct drm_device *drm = vc4_hdmi->connector.dev;
663 u32 packet_id = type - 0x80;
668 if (!drm_dev_enter(drm, &idx))
671 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
672 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
673 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
674 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
677 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
678 BIT(packet_id)), 100);
685 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
686 union hdmi_infoframe *frame)
688 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
689 struct drm_device *drm = vc4_hdmi->connector.dev;
690 u32 packet_id = frame->any.type - 0x80;
691 const struct vc4_hdmi_register *ram_packet_start =
692 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
693 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
694 u32 packet_reg_next = ram_packet_start->offset +
695 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
696 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
697 ram_packet_start->reg);
698 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
704 if (!drm_dev_enter(drm, &idx))
707 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
708 VC4_HDMI_RAM_PACKET_ENABLE),
709 "Packet RAM has to be on to store the packet.");
711 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
715 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
717 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
721 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
723 for (i = 0; i < len; i += 7) {
724 writel(buffer[i + 0] << 0 |
730 writel(buffer[i + 3] << 0 |
732 buffer[i + 5] << 16 |
739 * clear remainder of packet ram as it's included in the
740 * infoframe and triggers a checksum error on hdmi analyser
742 for (; packet_reg < packet_reg_next; packet_reg += 4)
743 writel(0, base + packet_reg);
745 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
746 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
748 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
750 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
751 BIT(packet_id)), 100);
753 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
759 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
760 enum vc4_hdmi_output_format fmt)
763 case VC4_HDMI_OUTPUT_RGB:
764 frame->colorspace = HDMI_COLORSPACE_RGB;
767 case VC4_HDMI_OUTPUT_YUV420:
768 frame->colorspace = HDMI_COLORSPACE_YUV420;
771 case VC4_HDMI_OUTPUT_YUV422:
772 frame->colorspace = HDMI_COLORSPACE_YUV422;
775 case VC4_HDMI_OUTPUT_YUV444:
776 frame->colorspace = HDMI_COLORSPACE_YUV444;
784 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
786 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
787 struct drm_connector *connector = &vc4_hdmi->connector;
788 struct drm_connector_state *cstate = connector->state;
789 struct vc4_hdmi_connector_state *vc4_state =
790 conn_state_to_vc4_hdmi_conn_state(cstate);
791 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
792 union hdmi_infoframe frame;
795 lockdep_assert_held(&vc4_hdmi->mutex);
797 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
800 DRM_ERROR("couldn't fill AVI infoframe\n");
804 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
806 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
807 HDMI_QUANTIZATION_RANGE_FULL :
808 HDMI_QUANTIZATION_RANGE_LIMITED);
809 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
810 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
811 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
813 vc4_hdmi_write_infoframe(encoder, &frame);
816 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
818 union hdmi_infoframe frame;
821 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
823 DRM_ERROR("couldn't fill SPD infoframe\n");
827 frame.spd.sdi = HDMI_SPD_SDI_PC;
829 vc4_hdmi_write_infoframe(encoder, &frame);
832 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
834 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
835 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
836 union hdmi_infoframe frame;
838 memcpy(&frame.audio, audio, sizeof(*audio));
840 if (vc4_hdmi->packet_ram_enabled)
841 vc4_hdmi_write_infoframe(encoder, &frame);
844 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
846 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
847 struct drm_connector *connector = &vc4_hdmi->connector;
848 struct drm_connector_state *conn_state = connector->state;
849 union hdmi_infoframe frame;
851 lockdep_assert_held(&vc4_hdmi->mutex);
853 if (!vc4_hdmi->variant->supports_hdr)
856 if (!conn_state->hdr_output_metadata)
859 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
862 vc4_hdmi_write_infoframe(encoder, &frame);
865 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
867 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
869 lockdep_assert_held(&vc4_hdmi->mutex);
871 vc4_hdmi_set_avi_infoframe(encoder);
872 vc4_hdmi_set_spd_infoframe(encoder);
874 * If audio was streaming, then we need to reenabled the audio
875 * infoframe here during encoder_enable.
877 if (vc4_hdmi->audio.streaming)
878 vc4_hdmi_set_audio_infoframe(encoder);
880 vc4_hdmi_set_hdr_infoframe(encoder);
883 #define SCRAMBLING_POLLING_DELAY_MS 1000
885 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
887 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
888 struct drm_device *drm = vc4_hdmi->connector.dev;
889 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
893 lockdep_assert_held(&vc4_hdmi->mutex);
895 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
898 if (!vc4_hdmi_mode_needs_scrambling(mode,
899 vc4_hdmi->output_bpc,
900 vc4_hdmi->output_format))
903 if (!drm_dev_enter(drm, &idx))
906 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
907 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
909 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
910 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
911 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
912 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
916 vc4_hdmi->scdc_enabled = true;
918 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
919 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
922 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
924 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
925 struct drm_device *drm = vc4_hdmi->connector.dev;
929 lockdep_assert_held(&vc4_hdmi->mutex);
931 if (!vc4_hdmi->scdc_enabled)
934 vc4_hdmi->scdc_enabled = false;
936 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
937 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
939 if (!drm_dev_enter(drm, &idx))
942 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
943 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
944 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
945 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
947 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
948 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
953 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
955 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
959 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
962 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
963 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
965 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
966 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
969 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
970 struct drm_atomic_state *state)
972 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
973 struct drm_device *drm = vc4_hdmi->connector.dev;
977 mutex_lock(&vc4_hdmi->mutex);
979 vc4_hdmi->packet_ram_enabled = false;
981 if (!drm_dev_enter(drm, &idx))
984 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
986 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
988 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
990 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
994 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
995 HDMI_WRITE(HDMI_VID_CTL,
996 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
997 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
999 vc4_hdmi_disable_scrambling(encoder);
1004 mutex_unlock(&vc4_hdmi->mutex);
1007 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1008 struct drm_atomic_state *state)
1010 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1011 struct drm_device *drm = vc4_hdmi->connector.dev;
1012 unsigned long flags;
1016 mutex_lock(&vc4_hdmi->mutex);
1018 if (!drm_dev_enter(drm, &idx))
1021 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1022 HDMI_WRITE(HDMI_VID_CTL,
1023 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1024 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1026 if (vc4_hdmi->variant->phy_disable)
1027 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1029 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1030 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1032 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1034 DRM_ERROR("Failed to release power domain: %d\n", ret);
1039 mutex_unlock(&vc4_hdmi->mutex);
1042 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1043 struct drm_connector_state *state,
1044 const struct drm_display_mode *mode)
1046 struct drm_device *drm = vc4_hdmi->connector.dev;
1047 unsigned long flags;
1051 if (!drm_dev_enter(drm, &idx))
1054 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1056 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1057 VC4_HD_CSC_CTL_ORDER);
1059 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1060 /* CEA VICs other than #1 requre limited range RGB
1061 * output unless overridden by an AVI infoframe.
1062 * Apply a colorspace conversion to squash 0-255 down
1063 * to 16-235. The matrix here is:
1070 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1071 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1072 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1073 VC4_HD_CSC_CTL_MODE);
1075 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1076 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1077 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1078 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1079 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1080 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1083 /* The RGB order applies even when CSC is disabled. */
1084 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1086 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1092 * If we need to output Full Range RGB, then use the unity matrix
1098 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1100 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1101 { 0x2000, 0x0000, 0x0000, 0x0000 },
1102 { 0x0000, 0x2000, 0x0000, 0x0000 },
1103 { 0x0000, 0x0000, 0x2000, 0x0000 },
1107 * CEA VICs other than #1 require limited range RGB output unless
1108 * overridden by an AVI infoframe. Apply a colorspace conversion to
1109 * squash 0-255 down to 16-235. The matrix here is:
1115 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1117 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1118 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1119 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1120 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1124 * Conversion between Full Range RGB and Full Range YUV422 using the
1128 * [ 0.181906 0.611804 0.061758 16 ]
1129 * [ -0.100268 -0.337232 0.437500 128 ]
1130 * [ 0.437500 -0.397386 -0.040114 128 ]
1132 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1134 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1135 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1136 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1137 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1141 * Conversion between Full Range RGB and Full Range YUV444 using the
1144 * [ -0.100268 -0.337232 0.437500 128 ]
1145 * [ 0.437500 -0.397386 -0.040114 128 ]
1146 * [ 0.181906 0.611804 0.061758 16 ]
1148 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1150 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1151 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1152 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1153 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1156 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1157 const u16 coeffs[3][4])
1159 lockdep_assert_held(&vc4_hdmi->hw_lock);
1161 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1162 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1163 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1164 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1165 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1166 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1169 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1170 struct drm_connector_state *state,
1171 const struct drm_display_mode *mode)
1173 struct drm_device *drm = vc4_hdmi->connector.dev;
1174 struct vc4_hdmi_connector_state *vc4_state =
1175 conn_state_to_vc4_hdmi_conn_state(state);
1176 unsigned long flags;
1178 u32 if_xbar = 0x543210;
1179 u32 csc_chan_ctl = 0;
1180 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1181 VC5_MT_CP_CSC_CTL_MODE);
1184 if (!drm_dev_enter(drm, &idx))
1187 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1189 switch (vc4_state->output_format) {
1190 case VC4_HDMI_OUTPUT_YUV444:
1191 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1194 case VC4_HDMI_OUTPUT_YUV422:
1195 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1196 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1197 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1198 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1200 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1201 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1203 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1204 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1206 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1209 case VC4_HDMI_OUTPUT_RGB:
1212 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1213 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1215 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1222 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1223 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1224 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1225 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1232 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1233 struct drm_connector_state *state,
1234 const struct drm_display_mode *mode)
1236 struct drm_device *drm = vc4_hdmi->connector.dev;
1237 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1238 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1239 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1240 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1241 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1242 VC4_HDMI_VERTA_VSP) |
1243 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1244 VC4_HDMI_VERTA_VFP) |
1245 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1246 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1247 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1249 VC4_HDMI_VERTB_VBP));
1250 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1251 VC4_SET_FIELD(mode->crtc_vtotal -
1252 mode->crtc_vsync_end,
1253 VC4_HDMI_VERTB_VBP));
1254 unsigned long flags;
1258 if (!drm_dev_enter(drm, &idx))
1261 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1263 HDMI_WRITE(HDMI_HORZA,
1264 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1265 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1266 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1267 VC4_HDMI_HORZA_HAP));
1269 HDMI_WRITE(HDMI_HORZB,
1270 VC4_SET_FIELD((mode->htotal -
1271 mode->hsync_end) * pixel_rep,
1272 VC4_HDMI_HORZB_HBP) |
1273 VC4_SET_FIELD((mode->hsync_end -
1274 mode->hsync_start) * pixel_rep,
1275 VC4_HDMI_HORZB_HSP) |
1276 VC4_SET_FIELD((mode->hsync_start -
1277 mode->hdisplay) * pixel_rep,
1278 VC4_HDMI_HORZB_HFP));
1280 HDMI_WRITE(HDMI_VERTA0, verta);
1281 HDMI_WRITE(HDMI_VERTA1, verta);
1283 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1284 HDMI_WRITE(HDMI_VERTB1, vertb);
1286 reg = HDMI_READ(HDMI_MISC_CONTROL);
1287 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1288 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1289 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1291 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1296 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1297 struct drm_connector_state *state,
1298 const struct drm_display_mode *mode)
1300 struct drm_device *drm = vc4_hdmi->connector.dev;
1301 const struct vc4_hdmi_connector_state *vc4_state =
1302 conn_state_to_vc4_hdmi_conn_state(state);
1303 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1304 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1305 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1306 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1307 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1308 VC5_HDMI_VERTA_VSP) |
1309 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1310 VC5_HDMI_VERTA_VFP) |
1311 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1312 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1313 VC5_HDMI_VERTB_VSPO) |
1314 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1316 VC4_HDMI_VERTB_VBP));
1317 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1318 VC4_SET_FIELD(mode->crtc_vtotal -
1319 mode->crtc_vsync_end,
1320 VC4_HDMI_VERTB_VBP));
1321 unsigned long flags;
1326 if (!drm_dev_enter(drm, &idx))
1329 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1331 HDMI_WRITE(HDMI_HORZA,
1332 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1333 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1334 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1335 VC5_HDMI_HORZA_HAP) |
1336 VC4_SET_FIELD((mode->hsync_start -
1337 mode->hdisplay) * pixel_rep,
1338 VC5_HDMI_HORZA_HFP));
1340 HDMI_WRITE(HDMI_HORZB,
1341 VC4_SET_FIELD((mode->htotal -
1342 mode->hsync_end) * pixel_rep,
1343 VC5_HDMI_HORZB_HBP) |
1344 VC4_SET_FIELD((mode->hsync_end -
1345 mode->hsync_start) * pixel_rep,
1346 VC5_HDMI_HORZB_HSP));
1348 HDMI_WRITE(HDMI_VERTA0, verta);
1349 HDMI_WRITE(HDMI_VERTA1, verta);
1351 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1352 HDMI_WRITE(HDMI_VERTB1, vertb);
1354 switch (vc4_state->output_bpc) {
1368 * YCC422 is always 36-bit and not considered deep colour so
1369 * doesn't signal in GCP.
1371 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1375 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1376 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1377 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1378 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1379 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1380 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1382 reg = HDMI_READ(HDMI_GCP_WORD_1);
1383 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1384 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1385 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1386 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1387 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1389 reg = HDMI_READ(HDMI_GCP_CONFIG);
1390 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1391 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1393 reg = HDMI_READ(HDMI_MISC_CONTROL);
1394 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1395 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1396 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1398 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1400 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1405 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1407 struct drm_device *drm = vc4_hdmi->connector.dev;
1408 unsigned long flags;
1413 if (!drm_dev_enter(drm, &idx))
1416 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1418 drift = HDMI_READ(HDMI_FIFO_CTL);
1419 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1421 HDMI_WRITE(HDMI_FIFO_CTL,
1422 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1423 HDMI_WRITE(HDMI_FIFO_CTL,
1424 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1426 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1428 usleep_range(1000, 1100);
1430 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1432 HDMI_WRITE(HDMI_FIFO_CTL,
1433 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1434 HDMI_WRITE(HDMI_FIFO_CTL,
1435 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1437 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1439 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1440 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1441 WARN_ONCE(ret, "Timeout waiting for "
1442 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1447 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1448 struct drm_atomic_state *state)
1450 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1451 struct drm_device *drm = vc4_hdmi->connector.dev;
1452 struct drm_connector *connector = &vc4_hdmi->connector;
1453 struct drm_connector_state *conn_state =
1454 drm_atomic_get_new_connector_state(state, connector);
1455 struct vc4_hdmi_connector_state *vc4_conn_state =
1456 conn_state_to_vc4_hdmi_conn_state(conn_state);
1457 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1458 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1459 unsigned long bvb_rate, hsm_rate;
1460 unsigned long flags;
1464 mutex_lock(&vc4_hdmi->mutex);
1466 if (!drm_dev_enter(drm, &idx))
1469 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1471 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1476 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1477 * be faster than pixel clock, infinitesimally faster, tested in
1478 * simulation. Otherwise, exact value is unimportant for HDMI
1479 * operation." This conflicts with bcm2835's vc4 documentation, which
1480 * states HSM's clock has to be at least 108% of the pixel clock.
1482 * Real life tests reveal that vc4's firmware statement holds up, and
1483 * users are able to use pixel clocks closer to HSM's, namely for
1484 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1485 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1488 * Additionally, the AXI clock needs to be at least 25% of
1489 * pixel clock, but HSM ends up being the limiting factor.
1491 hsm_rate = max_t(unsigned long,
1493 (tmds_char_rate / 100) * 101);
1494 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1496 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1497 goto err_put_runtime_pm;
1500 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1502 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1503 goto err_put_runtime_pm;
1506 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1508 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1509 goto err_put_runtime_pm;
1513 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1515 if (tmds_char_rate > 297000000)
1516 bvb_rate = 300000000;
1517 else if (tmds_char_rate > 148500000)
1518 bvb_rate = 150000000;
1520 bvb_rate = 75000000;
1522 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1524 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1525 goto err_disable_pixel_clock;
1528 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1530 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1531 goto err_disable_pixel_clock;
1534 if (vc4_hdmi->variant->phy_init)
1535 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1537 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1539 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1540 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1541 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1542 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1544 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1546 if (vc4_hdmi->variant->set_timings)
1547 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1551 mutex_unlock(&vc4_hdmi->mutex);
1555 err_disable_pixel_clock:
1556 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1558 pm_runtime_put(&vc4_hdmi->pdev->dev);
1562 mutex_unlock(&vc4_hdmi->mutex);
1566 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1567 struct drm_atomic_state *state)
1569 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1570 struct drm_device *drm = vc4_hdmi->connector.dev;
1571 struct drm_connector *connector = &vc4_hdmi->connector;
1572 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1573 struct drm_connector_state *conn_state =
1574 drm_atomic_get_new_connector_state(state, connector);
1575 unsigned long flags;
1578 mutex_lock(&vc4_hdmi->mutex);
1580 if (!drm_dev_enter(drm, &idx))
1583 if (vc4_hdmi->variant->csc_setup)
1584 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1586 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1587 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1588 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1593 mutex_unlock(&vc4_hdmi->mutex);
1596 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1597 struct drm_atomic_state *state)
1599 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1600 struct drm_device *drm = vc4_hdmi->connector.dev;
1601 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1602 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1603 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1604 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1605 unsigned long flags;
1609 mutex_lock(&vc4_hdmi->mutex);
1611 if (!drm_dev_enter(drm, &idx))
1614 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1616 HDMI_WRITE(HDMI_VID_CTL,
1617 VC4_HD_VID_CTL_ENABLE |
1618 VC4_HD_VID_CTL_CLRRGB |
1619 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1620 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1621 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1622 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1624 HDMI_WRITE(HDMI_VID_CTL,
1625 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1627 if (display->is_hdmi) {
1628 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1629 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1630 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1632 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1634 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1635 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1636 WARN_ONCE(ret, "Timeout waiting for "
1637 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1639 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1640 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1641 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1642 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1643 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1644 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1646 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1648 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1649 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1650 WARN_ONCE(ret, "Timeout waiting for "
1651 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1654 if (display->is_hdmi) {
1655 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1657 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1658 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1660 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1661 VC4_HDMI_RAM_PACKET_ENABLE);
1663 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1664 vc4_hdmi->packet_ram_enabled = true;
1666 vc4_hdmi_set_infoframes(encoder);
1669 vc4_hdmi_recenter_fifo(vc4_hdmi);
1670 vc4_hdmi_enable_scrambling(encoder);
1675 mutex_unlock(&vc4_hdmi->mutex);
1678 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1679 struct drm_crtc_state *crtc_state,
1680 struct drm_connector_state *conn_state)
1682 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1683 struct vc4_hdmi_connector_state *vc4_state =
1684 conn_state_to_vc4_hdmi_conn_state(conn_state);
1686 mutex_lock(&vc4_hdmi->mutex);
1687 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1688 &crtc_state->adjusted_mode);
1689 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1690 vc4_hdmi->output_format = vc4_state->output_format;
1691 mutex_unlock(&vc4_hdmi->mutex);
1695 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1696 const struct drm_display_info *info,
1697 const struct drm_display_mode *mode,
1698 unsigned int format, unsigned int bpc)
1700 struct drm_device *dev = vc4_hdmi->connector.dev;
1701 u8 vic = drm_match_cea_mode(mode);
1703 if (vic == 1 && bpc != 8) {
1704 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1708 if (!info->is_hdmi &&
1709 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1710 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1715 case VC4_HDMI_OUTPUT_RGB:
1716 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1718 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1721 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1722 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1726 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1727 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1731 drm_dbg(dev, "RGB format supported in that configuration.\n");
1735 case VC4_HDMI_OUTPUT_YUV422:
1736 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1738 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1739 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1744 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1748 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1752 case VC4_HDMI_OUTPUT_YUV444:
1753 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1755 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1756 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1760 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1761 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1765 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1766 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1770 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1778 static enum drm_mode_status
1779 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1780 const struct drm_display_mode *mode,
1781 unsigned long long clock)
1783 const struct drm_connector *connector = &vc4_hdmi->connector;
1784 const struct drm_display_info *info = &connector->display_info;
1785 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1787 if (clock > vc4_hdmi->variant->max_pixel_clock)
1788 return MODE_CLOCK_HIGH;
1790 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1791 return MODE_CLOCK_HIGH;
1793 /* 4096x2160@60 is not reliable without overclocking core */
1794 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1795 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1796 drm_mode_vrefresh(mode) >= 50)
1797 return MODE_CLOCK_HIGH;
1799 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1800 return MODE_CLOCK_HIGH;
1805 static unsigned long long
1806 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1808 enum vc4_hdmi_output_format fmt)
1810 unsigned long long clock = mode->clock * 1000ULL;
1812 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1815 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1818 clock = clock * bpc;
1825 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1826 struct vc4_hdmi_connector_state *vc4_state,
1827 const struct drm_display_mode *mode,
1828 unsigned int bpc, unsigned int fmt)
1830 unsigned long long clock;
1832 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1833 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
1836 vc4_state->tmds_char_rate = clock;
1842 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1843 struct vc4_hdmi_connector_state *vc4_state,
1844 const struct drm_display_mode *mode,
1847 struct drm_device *dev = vc4_hdmi->connector.dev;
1848 const struct drm_connector *connector = &vc4_hdmi->connector;
1849 const struct drm_display_info *info = &connector->display_info;
1850 unsigned int format;
1852 drm_dbg(dev, "Trying with an RGB output\n");
1854 format = VC4_HDMI_OUTPUT_RGB;
1855 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1858 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1861 vc4_state->output_format = format;
1866 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1868 format = VC4_HDMI_OUTPUT_YUV422;
1869 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1872 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1875 vc4_state->output_format = format;
1880 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1886 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1887 struct vc4_hdmi_connector_state *vc4_state,
1888 const struct drm_display_mode *mode)
1890 struct drm_device *dev = vc4_hdmi->connector.dev;
1891 struct drm_connector_state *conn_state = &vc4_state->base;
1892 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1896 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1897 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1899 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1904 vc4_state->output_bpc = bpc;
1907 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1908 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1909 vc4_state->output_bpc,
1910 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1911 vc4_state->tmds_char_rate);
1919 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1920 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1922 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1923 struct drm_crtc_state *crtc_state,
1924 struct drm_connector_state *conn_state)
1926 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1927 struct drm_connector *connector = &vc4_hdmi->connector;
1928 struct drm_connector_state *old_conn_state =
1929 drm_atomic_get_old_connector_state(conn_state->state, connector);
1930 struct vc4_hdmi_connector_state *old_vc4_state =
1931 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1932 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1933 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1934 unsigned long long tmds_char_rate = mode->clock * 1000;
1935 unsigned long long tmds_bit_rate;
1938 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1939 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1940 /* Only try to fixup DBLCLK modes to get 480i and 576i
1942 * A generic solution for all modes with odd horizontal
1943 * timing values seems impossible based on trying to
1944 * solve it for 1366x768 monitors.
1946 if ((mode->hsync_start - mode->hdisplay) & 1)
1947 mode->hsync_start--;
1948 if ((mode->hsync_end - mode->hsync_start) & 1)
1952 /* Now check whether we still have odd values remaining */
1953 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1954 (mode->hsync_end % 2) || (mode->htotal % 2))
1959 * The 1440p@60 pixel rate is in the same range than the first
1960 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1961 * bandwidth). Slightly lower the frequency to bring it out of
1964 tmds_bit_rate = tmds_char_rate * 10;
1965 if (vc4_hdmi->disable_wifi_frequencies &&
1966 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1967 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1968 mode->clock = 238560;
1969 tmds_char_rate = mode->clock * 1000;
1972 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1976 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1977 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1978 vc4_state->output_format != old_vc4_state->output_format)
1979 crtc_state->mode_changed = true;
1984 static enum drm_mode_status
1985 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1986 const struct drm_display_mode *mode)
1988 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1990 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1991 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1992 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1993 (mode->hsync_end % 2) || (mode->htotal % 2)))
1994 return MODE_H_ILLEGAL;
1996 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
1999 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2000 .atomic_check = vc4_hdmi_encoder_atomic_check,
2001 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2002 .mode_valid = vc4_hdmi_encoder_mode_valid,
2005 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2007 struct drm_device *drm = encoder->dev;
2008 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2009 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2011 drm_debugfs_add_file(drm, variant->debugfs_name,
2012 vc4_hdmi_debugfs_regs, vc4_hdmi);
2017 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2018 .late_register = vc4_hdmi_late_register,
2021 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2024 u32 channel_map = 0;
2026 for (i = 0; i < 8; i++) {
2027 if (channel_mask & BIT(i))
2028 channel_map |= i << (3 * i);
2033 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2036 u32 channel_map = 0;
2038 for (i = 0; i < 8; i++) {
2039 if (channel_mask & BIT(i))
2040 channel_map |= i << (4 * i);
2045 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2047 struct drm_device *drm = vc4_hdmi->connector.dev;
2048 unsigned long flags;
2052 if (!drm_dev_enter(drm, &idx))
2055 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2056 hotplug = HDMI_READ(HDMI_HOTPLUG);
2057 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2061 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2064 /* HDMI audio codec callbacks */
2065 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2066 unsigned int samplerate)
2068 struct drm_device *drm = vc4_hdmi->connector.dev;
2070 unsigned long flags;
2074 if (!drm_dev_enter(drm, &idx))
2077 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2078 rational_best_approximation(hsm_clock, samplerate,
2079 VC4_HD_MAI_SMP_N_MASK >>
2080 VC4_HD_MAI_SMP_N_SHIFT,
2081 (VC4_HD_MAI_SMP_M_MASK >>
2082 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2085 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2086 HDMI_WRITE(HDMI_MAI_SMP,
2087 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2088 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2089 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2094 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2096 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2100 lockdep_assert_held(&vc4_hdmi->mutex);
2101 lockdep_assert_held(&vc4_hdmi->hw_lock);
2103 n = 128 * samplerate / 1000;
2104 tmp = (u64)(mode->clock * 1000) * n;
2105 do_div(tmp, 128 * samplerate);
2108 HDMI_WRITE(HDMI_CRP_CFG,
2109 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2110 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2113 * We could get slightly more accurate clocks in some cases by
2114 * providing a CTS_1 value. The two CTS values are alternated
2115 * between based on the period fields
2117 HDMI_WRITE(HDMI_CTS_0, cts);
2118 HDMI_WRITE(HDMI_CTS_1, cts);
2121 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2123 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2125 return snd_soc_card_get_drvdata(card);
2128 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2130 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2132 lockdep_assert_held(&vc4_hdmi->mutex);
2135 * If the encoder is currently in DVI mode, treat the codec DAI
2138 if (!display->is_hdmi)
2144 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2146 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2147 struct drm_device *drm = vc4_hdmi->connector.dev;
2148 unsigned long flags;
2152 mutex_lock(&vc4_hdmi->mutex);
2154 if (!drm_dev_enter(drm, &idx)) {
2159 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2164 vc4_hdmi->audio.streaming = true;
2166 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2167 HDMI_WRITE(HDMI_MAI_CTL,
2168 VC4_HD_MAI_CTL_RESET |
2169 VC4_HD_MAI_CTL_FLUSH |
2170 VC4_HD_MAI_CTL_DLATE |
2171 VC4_HD_MAI_CTL_ERRORE |
2172 VC4_HD_MAI_CTL_ERRORF);
2173 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2175 if (vc4_hdmi->variant->phy_rng_enable)
2176 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2181 mutex_unlock(&vc4_hdmi->mutex);
2186 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2188 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2189 struct device *dev = &vc4_hdmi->pdev->dev;
2190 unsigned long flags;
2193 lockdep_assert_held(&vc4_hdmi->mutex);
2195 vc4_hdmi->audio.streaming = false;
2196 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2198 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2202 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2203 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2204 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2206 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2209 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2211 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2212 struct drm_device *drm = vc4_hdmi->connector.dev;
2213 unsigned long flags;
2216 mutex_lock(&vc4_hdmi->mutex);
2218 if (!drm_dev_enter(drm, &idx))
2221 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2223 HDMI_WRITE(HDMI_MAI_CTL,
2224 VC4_HD_MAI_CTL_DLATE |
2225 VC4_HD_MAI_CTL_ERRORE |
2226 VC4_HD_MAI_CTL_ERRORF);
2228 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2230 if (vc4_hdmi->variant->phy_rng_disable)
2231 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2233 vc4_hdmi->audio.streaming = false;
2234 vc4_hdmi_audio_reset(vc4_hdmi);
2239 mutex_unlock(&vc4_hdmi->mutex);
2242 static int sample_rate_to_mai_fmt(int samplerate)
2244 switch (samplerate) {
2246 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2248 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2250 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2252 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2254 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2256 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2258 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2260 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2262 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2264 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2266 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2268 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2270 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2272 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2274 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2276 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2280 /* HDMI audio codec callbacks */
2281 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2282 struct hdmi_codec_daifmt *daifmt,
2283 struct hdmi_codec_params *params)
2285 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2286 struct drm_device *drm = vc4_hdmi->connector.dev;
2287 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2288 unsigned int sample_rate = params->sample_rate;
2289 unsigned int channels = params->channels;
2290 unsigned long flags;
2291 u32 audio_packet_config, channel_mask;
2293 u32 mai_audio_format;
2294 u32 mai_sample_rate;
2298 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2299 sample_rate, params->sample_width, channels);
2301 mutex_lock(&vc4_hdmi->mutex);
2303 if (!drm_dev_enter(drm, &idx)) {
2308 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2313 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2315 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2316 HDMI_WRITE(HDMI_MAI_CTL,
2317 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2318 VC4_HD_MAI_CTL_WHOLSMP |
2319 VC4_HD_MAI_CTL_CHALIGN |
2320 VC4_HD_MAI_CTL_ENABLE);
2322 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2323 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2324 params->channels == 8)
2325 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2327 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2328 HDMI_WRITE(HDMI_MAI_FMT,
2329 VC4_SET_FIELD(mai_sample_rate,
2330 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2331 VC4_SET_FIELD(mai_audio_format,
2332 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2334 /* The B frame identifier should match the value used by alsa-lib (8) */
2335 audio_packet_config =
2336 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2337 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2338 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2340 channel_mask = GENMASK(channels - 1, 0);
2341 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2342 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2344 /* Set the MAI threshold */
2345 HDMI_WRITE(HDMI_MAI_THR,
2346 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2347 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2348 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2349 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2351 HDMI_WRITE(HDMI_MAI_CONFIG,
2352 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2353 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2354 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2356 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2357 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2358 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2360 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2362 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2364 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2365 vc4_hdmi_set_audio_infoframe(encoder);
2370 mutex_unlock(&vc4_hdmi->mutex);
2375 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2376 .name = "vc4-hdmi-cpu-dai-component",
2377 .legacy_dai_naming = 1,
2380 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2382 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2384 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2389 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2390 .name = "vc4-hdmi-cpu-dai",
2391 .probe = vc4_hdmi_audio_cpu_dai_probe,
2393 .stream_name = "Playback",
2396 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2397 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2398 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2399 SNDRV_PCM_RATE_192000,
2400 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2404 static const struct snd_dmaengine_pcm_config pcm_conf = {
2405 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2406 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2409 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2410 uint8_t *buf, size_t len)
2412 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2413 struct drm_connector *connector = &vc4_hdmi->connector;
2415 mutex_lock(&vc4_hdmi->mutex);
2416 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2417 mutex_unlock(&vc4_hdmi->mutex);
2422 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2423 .get_eld = vc4_hdmi_audio_get_eld,
2424 .prepare = vc4_hdmi_audio_prepare,
2425 .audio_shutdown = vc4_hdmi_audio_shutdown,
2426 .audio_startup = vc4_hdmi_audio_startup,
2429 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2430 .ops = &vc4_hdmi_codec_ops,
2431 .max_i2s_channels = 8,
2435 static void vc4_hdmi_audio_codec_release(void *ptr)
2437 struct vc4_hdmi *vc4_hdmi = ptr;
2439 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2440 vc4_hdmi->audio.codec_pdev = NULL;
2443 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2445 const struct vc4_hdmi_register *mai_data =
2446 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2447 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2448 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2449 struct device *dev = &vc4_hdmi->pdev->dev;
2450 struct platform_device *codec_pdev;
2456 * ASoC makes it a bit hard to retrieve a pointer to the
2457 * vc4_hdmi structure. Registering the card will overwrite our
2458 * device drvdata with a pointer to the snd_soc_card structure,
2459 * which can then be used to retrieve whatever drvdata we want
2462 * However, that doesn't fly in the case where we wouldn't
2463 * register an ASoC card (because of an old DT that is missing
2464 * the dmas properties for example), then the card isn't
2465 * registered and the device drvdata wouldn't be set.
2467 * We can deal with both cases by making sure a snd_soc_card
2468 * pointer and a vc4_hdmi structure are pointing to the same
2469 * memory address, so we can treat them indistinctly without any
2472 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2473 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2475 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2477 "'dmas' DT property is missing or empty, no HDMI audio\n");
2481 if (mai_data->reg != VC4_HD) {
2482 WARN_ONCE(true, "MAI isn't in the HD block\n");
2487 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2488 * the bus address specified in the DT, because the physical address
2489 * (the one returned by platform_get_resource()) is not appropriate
2490 * for DMA transfers.
2491 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2493 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2494 /* Before BCM2711, we don't have a named register range */
2498 addr = of_get_address(dev->of_node, index, NULL, NULL);
2500 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2501 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2502 vc4_hdmi->audio.dma_data.maxburst = 2;
2505 * NOTE: Strictly speaking, we should probably use a DRM-managed
2506 * registration there to avoid removing all the audio components
2507 * by the time the driver doesn't have any user anymore.
2509 * However, the ASoC core uses a number of devm_kzalloc calls
2510 * when registering, even when using non-device-managed
2511 * functions (such as in snd_soc_register_component()).
2513 * If we call snd_soc_unregister_component() in a DRM-managed
2514 * action, the device-managed actions have already been executed
2515 * and thus we would access memory that has been freed.
2517 * Using device-managed hooks here probably leaves us open to a
2518 * bunch of issues if userspace still has a handle on the ALSA
2519 * device when the device is removed. However, this is mitigated
2520 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2521 * path to prevent the access to the device resources if it
2522 * isn't there anymore.
2524 * Then, the vc4_hdmi structure is DRM-managed and thus only
2525 * freed whenever the last user has closed the DRM device file.
2526 * It should thus outlive ALSA in most situations.
2528 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2530 dev_err(dev, "Could not register PCM component: %d\n", ret);
2534 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2535 &vc4_hdmi_audio_cpu_dai_drv, 1);
2537 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2541 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2542 PLATFORM_DEVID_AUTO,
2543 &vc4_hdmi_codec_pdata,
2544 sizeof(vc4_hdmi_codec_pdata));
2545 if (IS_ERR(codec_pdev)) {
2546 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2547 return PTR_ERR(codec_pdev);
2549 vc4_hdmi->audio.codec_pdev = codec_pdev;
2551 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2555 dai_link->cpus = &vc4_hdmi->audio.cpu;
2556 dai_link->codecs = &vc4_hdmi->audio.codec;
2557 dai_link->platforms = &vc4_hdmi->audio.platform;
2559 dai_link->num_cpus = 1;
2560 dai_link->num_codecs = 1;
2561 dai_link->num_platforms = 1;
2563 dai_link->name = "MAI";
2564 dai_link->stream_name = "MAI PCM";
2565 dai_link->codecs->dai_name = "i2s-hifi";
2566 dai_link->cpus->dai_name = dev_name(dev);
2567 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2568 dai_link->platforms->name = dev_name(dev);
2570 card->dai_link = dai_link;
2571 card->num_links = 1;
2572 card->name = vc4_hdmi->variant->card_name;
2573 card->driver_name = "vc4-hdmi";
2575 card->owner = THIS_MODULE;
2578 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2579 * stores a pointer to the snd card object in dev->driver_data. This
2580 * means we cannot use it for something else. The hdmi back-pointer is
2581 * now stored in card->drvdata and should be retrieved with
2582 * snd_soc_card_get_drvdata() if needed.
2584 snd_soc_card_set_drvdata(card, vc4_hdmi);
2585 ret = devm_snd_soc_register_card(dev, card);
2587 dev_err_probe(dev, ret, "Could not register sound card\n");
2593 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2595 struct vc4_hdmi *vc4_hdmi = priv;
2596 struct drm_connector *connector = &vc4_hdmi->connector;
2597 struct drm_device *dev = connector->dev;
2599 if (dev && dev->registered)
2600 drm_connector_helper_hpd_irq_event(connector);
2605 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2607 struct drm_connector *connector = &vc4_hdmi->connector;
2608 struct platform_device *pdev = vc4_hdmi->pdev;
2611 if (vc4_hdmi->variant->external_irq_controller) {
2612 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2613 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2615 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2617 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2618 "vc4 hdmi hpd connected", vc4_hdmi);
2622 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2624 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2625 "vc4 hdmi hpd disconnected", vc4_hdmi);
2629 connector->polled = DRM_CONNECTOR_POLL_HPD;
2635 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2636 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2638 struct vc4_hdmi *vc4_hdmi = priv;
2640 if (vc4_hdmi->cec_rx_msg.len)
2641 cec_received_msg(vc4_hdmi->cec_adap,
2642 &vc4_hdmi->cec_rx_msg);
2647 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2649 struct vc4_hdmi *vc4_hdmi = priv;
2651 if (vc4_hdmi->cec_tx_ok) {
2652 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2656 * This CEC implementation makes 1 retry, so if we
2657 * get a NACK, then that means it made 2 attempts.
2659 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2665 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2667 struct vc4_hdmi *vc4_hdmi = priv;
2670 if (vc4_hdmi->cec_irq_was_rx)
2671 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2673 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2678 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2680 struct drm_device *dev = vc4_hdmi->connector.dev;
2681 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2684 lockdep_assert_held(&vc4_hdmi->hw_lock);
2686 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2687 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2689 if (msg->len > 16) {
2690 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2694 for (i = 0; i < msg->len; i += 4) {
2695 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2697 msg->msg[i] = val & 0xff;
2698 msg->msg[i + 1] = (val >> 8) & 0xff;
2699 msg->msg[i + 2] = (val >> 16) & 0xff;
2700 msg->msg[i + 3] = (val >> 24) & 0xff;
2704 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2709 * We don't need to protect the register access using
2710 * drm_dev_enter() there because the interrupt handler lifetime
2711 * is tied to the device itself, and not to the DRM device.
2713 * So when the device will be gone, one of the first thing we
2714 * will be doing will be to unregister the interrupt handler,
2715 * and then unregister the DRM device. drm_dev_enter() would
2716 * thus always succeed if we are here.
2719 lockdep_assert_held(&vc4_hdmi->hw_lock);
2721 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2722 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2723 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2724 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2726 return IRQ_WAKE_THREAD;
2729 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2731 struct vc4_hdmi *vc4_hdmi = priv;
2734 spin_lock(&vc4_hdmi->hw_lock);
2735 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2736 spin_unlock(&vc4_hdmi->hw_lock);
2741 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2745 lockdep_assert_held(&vc4_hdmi->hw_lock);
2748 * We don't need to protect the register access using
2749 * drm_dev_enter() there because the interrupt handler lifetime
2750 * is tied to the device itself, and not to the DRM device.
2752 * So when the device will be gone, one of the first thing we
2753 * will be doing will be to unregister the interrupt handler,
2754 * and then unregister the DRM device. drm_dev_enter() would
2755 * thus always succeed if we are here.
2758 vc4_hdmi->cec_rx_msg.len = 0;
2759 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2760 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2761 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2762 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2763 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2765 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2767 return IRQ_WAKE_THREAD;
2770 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2772 struct vc4_hdmi *vc4_hdmi = priv;
2775 spin_lock(&vc4_hdmi->hw_lock);
2776 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2777 spin_unlock(&vc4_hdmi->hw_lock);
2782 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2784 struct vc4_hdmi *vc4_hdmi = priv;
2785 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2790 * We don't need to protect the register access using
2791 * drm_dev_enter() there because the interrupt handler lifetime
2792 * is tied to the device itself, and not to the DRM device.
2794 * So when the device will be gone, one of the first thing we
2795 * will be doing will be to unregister the interrupt handler,
2796 * and then unregister the DRM device. drm_dev_enter() would
2797 * thus always succeed if we are here.
2800 if (!(stat & VC4_HDMI_CPU_CEC))
2803 spin_lock(&vc4_hdmi->hw_lock);
2804 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2805 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2806 if (vc4_hdmi->cec_irq_was_rx)
2807 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2809 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2811 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2812 spin_unlock(&vc4_hdmi->hw_lock);
2817 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2819 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2820 struct drm_device *drm = vc4_hdmi->connector.dev;
2821 /* clock period in microseconds */
2822 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2823 unsigned long flags;
2828 if (!drm_dev_enter(drm, &idx))
2830 * We can't return an error code, because the CEC
2831 * framework will emit WARN_ON messages at unbind
2836 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2842 mutex_lock(&vc4_hdmi->mutex);
2844 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2846 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2847 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2848 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2849 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2850 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2851 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2853 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2854 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2855 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2856 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2857 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2858 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2859 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2860 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2861 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2862 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2863 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2864 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2865 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2866 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2867 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2868 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2869 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2870 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2871 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2873 if (!vc4_hdmi->variant->external_irq_controller)
2874 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2876 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2878 mutex_unlock(&vc4_hdmi->mutex);
2884 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2886 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2887 struct drm_device *drm = vc4_hdmi->connector.dev;
2888 unsigned long flags;
2891 if (!drm_dev_enter(drm, &idx))
2893 * We can't return an error code, because the CEC
2894 * framework will emit WARN_ON messages at unbind
2899 mutex_lock(&vc4_hdmi->mutex);
2901 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2903 if (!vc4_hdmi->variant->external_irq_controller)
2904 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2906 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2907 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2909 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2911 mutex_unlock(&vc4_hdmi->mutex);
2913 pm_runtime_put(&vc4_hdmi->pdev->dev);
2920 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2923 return vc4_hdmi_cec_enable(adap);
2925 return vc4_hdmi_cec_disable(adap);
2928 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2930 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2931 struct drm_device *drm = vc4_hdmi->connector.dev;
2932 unsigned long flags;
2935 if (!drm_dev_enter(drm, &idx))
2937 * We can't return an error code, because the CEC
2938 * framework will emit WARN_ON messages at unbind
2943 mutex_lock(&vc4_hdmi->mutex);
2944 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2945 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2946 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2947 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2948 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2949 mutex_unlock(&vc4_hdmi->mutex);
2956 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2957 u32 signal_free_time, struct cec_msg *msg)
2959 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2960 struct drm_device *dev = vc4_hdmi->connector.dev;
2961 unsigned long flags;
2966 if (!drm_dev_enter(dev, &idx))
2969 if (msg->len > 16) {
2970 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2975 mutex_lock(&vc4_hdmi->mutex);
2977 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2979 for (i = 0; i < msg->len; i += 4)
2980 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2982 (msg->msg[i + 1] << 8) |
2983 (msg->msg[i + 2] << 16) |
2984 (msg->msg[i + 3] << 24));
2986 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2987 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2988 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2989 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2990 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2991 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2993 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2995 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2996 mutex_unlock(&vc4_hdmi->mutex);
3002 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3003 .adap_enable = vc4_hdmi_cec_adap_enable,
3004 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3005 .adap_transmit = vc4_hdmi_cec_adap_transmit,
3008 static void vc4_hdmi_cec_release(void *ptr)
3010 struct vc4_hdmi *vc4_hdmi = ptr;
3012 cec_unregister_adapter(vc4_hdmi->cec_adap);
3013 vc4_hdmi->cec_adap = NULL;
3016 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3018 struct cec_connector_info conn_info;
3019 struct platform_device *pdev = vc4_hdmi->pdev;
3020 struct device *dev = &pdev->dev;
3023 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3024 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3028 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3030 vc4_hdmi->variant->card_name,
3032 CEC_CAP_CONNECTOR_INFO, 1);
3033 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3037 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3038 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3040 if (vc4_hdmi->variant->external_irq_controller) {
3041 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3042 vc4_cec_irq_handler_rx_bare,
3043 vc4_cec_irq_handler_rx_thread, 0,
3044 "vc4 hdmi cec rx", vc4_hdmi);
3046 goto err_delete_cec_adap;
3048 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3049 vc4_cec_irq_handler_tx_bare,
3050 vc4_cec_irq_handler_tx_thread, 0,
3051 "vc4 hdmi cec tx", vc4_hdmi);
3053 goto err_delete_cec_adap;
3055 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3056 vc4_cec_irq_handler,
3057 vc4_cec_irq_handler_thread, 0,
3058 "vc4 hdmi cec", vc4_hdmi);
3060 goto err_delete_cec_adap;
3063 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3065 goto err_delete_cec_adap;
3068 * NOTE: Strictly speaking, we should probably use a DRM-managed
3069 * registration there to avoid removing the CEC adapter by the
3070 * time the DRM driver doesn't have any user anymore.
3072 * However, the CEC framework already cleans up the CEC adapter
3073 * only when the last user has closed its file descriptor, so we
3074 * don't need to handle it in DRM.
3076 * By the time the device-managed hook is executed, we will give
3077 * up our reference to the CEC adapter and therefore don't
3078 * really care when it's actually freed.
3080 * There's still a problematic sequence: if we unregister our
3081 * CEC adapter, but the userspace keeps a handle on the CEC
3082 * adapter but not the DRM device for some reason. In such a
3083 * case, our vc4_hdmi structure will be freed, but the
3084 * cec_adapter structure will have a dangling pointer to what
3085 * used to be our HDMI controller. If we get a CEC call at that
3086 * moment, we could end up with a use-after-free. Fortunately,
3087 * the CEC framework already handles this too, by calling
3088 * cec_is_registered() in cec_ioctl() and cec_poll().
3090 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3096 err_delete_cec_adap:
3097 cec_delete_adapter(vc4_hdmi->cec_adap);
3102 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3108 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3110 struct debugfs_reg32 *regs = ptr;
3115 static int vc4_hdmi_build_regset(struct drm_device *drm,
3116 struct vc4_hdmi *vc4_hdmi,
3117 struct debugfs_regset32 *regset,
3118 enum vc4_hdmi_regs reg)
3120 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3121 struct debugfs_reg32 *regs, *new_regs;
3122 unsigned int count = 0;
3126 regs = kcalloc(variant->num_registers, sizeof(*regs),
3131 for (i = 0; i < variant->num_registers; i++) {
3132 const struct vc4_hdmi_register *field = &variant->registers[i];
3134 if (field->reg != reg)
3137 regs[count].name = field->name;
3138 regs[count].offset = field->offset;
3142 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3146 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3147 regset->regs = new_regs;
3148 regset->nregs = count;
3150 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3157 static int vc4_hdmi_init_resources(struct drm_device *drm,
3158 struct vc4_hdmi *vc4_hdmi)
3160 struct platform_device *pdev = vc4_hdmi->pdev;
3161 struct device *dev = &pdev->dev;
3164 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3165 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3166 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3168 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3169 if (IS_ERR(vc4_hdmi->hd_regs))
3170 return PTR_ERR(vc4_hdmi->hd_regs);
3172 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3176 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3180 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3181 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3182 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3183 if (ret != -EPROBE_DEFER)
3184 DRM_ERROR("Failed to get pixel clock\n");
3188 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3189 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3190 DRM_ERROR("Failed to get HDMI state machine clock\n");
3191 return PTR_ERR(vc4_hdmi->hsm_clock);
3193 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3194 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3199 static int vc5_hdmi_init_resources(struct drm_device *drm,
3200 struct vc4_hdmi *vc4_hdmi)
3202 struct platform_device *pdev = vc4_hdmi->pdev;
3203 struct device *dev = &pdev->dev;
3204 struct resource *res;
3207 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3211 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3212 resource_size(res));
3213 if (!vc4_hdmi->hdmicore_regs)
3216 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3220 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3221 if (!vc4_hdmi->hd_regs)
3224 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3228 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3229 if (!vc4_hdmi->cec_regs)
3232 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3236 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3237 if (!vc4_hdmi->csc_regs)
3240 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3244 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3245 if (!vc4_hdmi->dvp_regs)
3248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3252 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3253 if (!vc4_hdmi->phy_regs)
3256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3260 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3261 if (!vc4_hdmi->ram_regs)
3264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3268 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3269 if (!vc4_hdmi->rm_regs)
3272 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3273 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3274 DRM_ERROR("Failed to get HDMI state machine clock\n");
3275 return PTR_ERR(vc4_hdmi->hsm_clock);
3278 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3279 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3280 DRM_ERROR("Failed to get pixel bvb clock\n");
3281 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3284 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3285 if (IS_ERR(vc4_hdmi->audio_clock)) {
3286 DRM_ERROR("Failed to get audio clock\n");
3287 return PTR_ERR(vc4_hdmi->audio_clock);
3290 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3291 if (IS_ERR(vc4_hdmi->cec_clock)) {
3292 DRM_ERROR("Failed to get CEC clock\n");
3293 return PTR_ERR(vc4_hdmi->cec_clock);
3296 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3297 if (IS_ERR(vc4_hdmi->reset)) {
3298 DRM_ERROR("Failed to get HDMI reset line\n");
3299 return PTR_ERR(vc4_hdmi->reset);
3302 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3306 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3310 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3314 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3318 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3322 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3326 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3330 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3337 static int vc4_hdmi_runtime_suspend(struct device *dev)
3339 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3341 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3346 static int vc4_hdmi_runtime_resume(struct device *dev)
3348 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3349 unsigned long __maybe_unused flags;
3350 u32 __maybe_unused value;
3354 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3359 * Whenever the RaspberryPi boots without an HDMI monitor
3360 * plugged in, the firmware won't have initialized the HSM clock
3361 * rate and it will be reported as 0.
3363 * If we try to access a register of the controller in such a
3364 * case, it will lead to a silent CPU stall. Let's make sure we
3365 * prevent such a case.
3367 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3370 goto err_disable_clk;
3373 if (vc4_hdmi->variant->reset)
3374 vc4_hdmi->variant->reset(vc4_hdmi);
3376 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3377 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3378 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3379 /* Set the logical address to Unregistered */
3380 value |= VC4_HDMI_CEC_ADDR_MASK;
3381 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3382 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3384 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3386 if (!vc4_hdmi->variant->external_irq_controller) {
3387 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3388 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3389 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3396 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3400 static void vc4_hdmi_put_ddc_device(void *ptr)
3402 struct vc4_hdmi *vc4_hdmi = ptr;
3404 put_device(&vc4_hdmi->ddc->dev);
3407 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3409 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3410 struct platform_device *pdev = to_platform_device(dev);
3411 struct drm_device *drm = dev_get_drvdata(master);
3412 struct vc4_hdmi *vc4_hdmi;
3413 struct drm_encoder *encoder;
3414 struct device_node *ddc_node;
3417 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3421 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3425 spin_lock_init(&vc4_hdmi->hw_lock);
3426 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3428 dev_set_drvdata(dev, vc4_hdmi);
3429 encoder = &vc4_hdmi->encoder.base;
3430 vc4_hdmi->encoder.type = variant->encoder_type;
3431 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3432 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3433 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3434 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3435 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3436 vc4_hdmi->pdev = pdev;
3437 vc4_hdmi->variant = variant;
3440 * Since we don't know the state of the controller and its
3441 * display (if any), let's assume it's always enabled.
3442 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3443 * sure it's disabled, and avoid any inconsistency.
3445 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3446 vc4_hdmi->scdc_enabled = true;
3448 ret = variant->init_resources(drm, vc4_hdmi);
3452 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3454 DRM_ERROR("Failed to find ddc node in device tree\n");
3458 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3459 of_node_put(ddc_node);
3460 if (!vc4_hdmi->ddc) {
3461 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3462 return -EPROBE_DEFER;
3465 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3469 /* Only use the GPIO HPD pin if present in the DT, otherwise
3470 * we'll use the HDMI core's register.
3472 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3473 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3474 return PTR_ERR(vc4_hdmi->hpd_gpio);
3477 vc4_hdmi->disable_wifi_frequencies =
3478 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3480 ret = devm_pm_runtime_enable(dev);
3485 * We need to have the device powered up at this point to call
3486 * our reset hook and for the CEC init.
3488 ret = pm_runtime_resume_and_get(dev);
3492 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3493 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3494 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3495 clk_prepare_enable(vc4_hdmi->pixel_clock);
3496 clk_prepare_enable(vc4_hdmi->hsm_clock);
3497 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3500 ret = drmm_encoder_init(drm, encoder,
3501 &vc4_hdmi_encoder_funcs,
3502 DRM_MODE_ENCODER_TMDS,
3505 goto err_put_runtime_pm;
3507 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3509 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3511 goto err_put_runtime_pm;
3513 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3515 goto err_put_runtime_pm;
3517 ret = vc4_hdmi_cec_init(vc4_hdmi);
3519 goto err_put_runtime_pm;
3521 ret = vc4_hdmi_audio_init(vc4_hdmi);
3523 goto err_put_runtime_pm;
3525 pm_runtime_put_sync(dev);
3530 pm_runtime_put_sync(dev);
3535 static const struct component_ops vc4_hdmi_ops = {
3536 .bind = vc4_hdmi_bind,
3539 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3541 return component_add(&pdev->dev, &vc4_hdmi_ops);
3544 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3546 component_del(&pdev->dev, &vc4_hdmi_ops);
3550 static const struct vc4_hdmi_variant bcm2835_variant = {
3551 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3552 .debugfs_name = "hdmi_regs",
3553 .card_name = "vc4-hdmi",
3554 .max_pixel_clock = 162000000,
3555 .registers = vc4_hdmi_fields,
3556 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3558 .init_resources = vc4_hdmi_init_resources,
3559 .csc_setup = vc4_hdmi_csc_setup,
3560 .reset = vc4_hdmi_reset,
3561 .set_timings = vc4_hdmi_set_timings,
3562 .phy_init = vc4_hdmi_phy_init,
3563 .phy_disable = vc4_hdmi_phy_disable,
3564 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3565 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3566 .channel_map = vc4_hdmi_channel_map,
3567 .supports_hdr = false,
3570 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3571 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3572 .debugfs_name = "hdmi0_regs",
3573 .card_name = "vc4-hdmi-0",
3574 .max_pixel_clock = 600000000,
3575 .registers = vc5_hdmi_hdmi0_fields,
3576 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3577 .phy_lane_mapping = {
3583 .unsupported_odd_h_timings = true,
3584 .external_irq_controller = true,
3586 .init_resources = vc5_hdmi_init_resources,
3587 .csc_setup = vc5_hdmi_csc_setup,
3588 .reset = vc5_hdmi_reset,
3589 .set_timings = vc5_hdmi_set_timings,
3590 .phy_init = vc5_hdmi_phy_init,
3591 .phy_disable = vc5_hdmi_phy_disable,
3592 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3593 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3594 .channel_map = vc5_hdmi_channel_map,
3595 .supports_hdr = true,
3596 .hp_detect = vc5_hdmi_hp_detect,
3599 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3600 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3601 .debugfs_name = "hdmi1_regs",
3602 .card_name = "vc4-hdmi-1",
3603 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3604 .registers = vc5_hdmi_hdmi1_fields,
3605 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3606 .phy_lane_mapping = {
3612 .unsupported_odd_h_timings = true,
3613 .external_irq_controller = true,
3615 .init_resources = vc5_hdmi_init_resources,
3616 .csc_setup = vc5_hdmi_csc_setup,
3617 .reset = vc5_hdmi_reset,
3618 .set_timings = vc5_hdmi_set_timings,
3619 .phy_init = vc5_hdmi_phy_init,
3620 .phy_disable = vc5_hdmi_phy_disable,
3621 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3622 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3623 .channel_map = vc5_hdmi_channel_map,
3624 .supports_hdr = true,
3625 .hp_detect = vc5_hdmi_hp_detect,
3628 static const struct of_device_id vc4_hdmi_dt_match[] = {
3629 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3630 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3631 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3635 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3636 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3637 vc4_hdmi_runtime_resume,
3641 struct platform_driver vc4_hdmi_driver = {
3642 .probe = vc4_hdmi_dev_probe,
3643 .remove = vc4_hdmi_dev_remove,
3646 .of_match_table = vc4_hdmi_dt_match,
3647 .pm = &vc4_hdmi_pm_ops,