2 * Copyright (C) 2016 Broadcom
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * DOC: VC4 DSI0/DSI1 module
20 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
21 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
24 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
25 * while the compute module brings both DSI0 and DSI1 out.
27 * This driver has been tested for DSI1 video-mode display only
28 * currently, with most of the information necessary for DSI0
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_mipi_dsi.h>
35 #include <drm/drm_of.h>
36 #include <drm/drm_panel.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/clk.h>
39 #include <linux/clk-provider.h>
40 #include <linux/completion.h>
41 #include <linux/component.h>
42 #include <linux/dmaengine.h>
43 #include <linux/i2c.h>
45 #include <linux/of_address.h>
46 #include <linux/of_platform.h>
47 #include <linux/pm_runtime.h>
51 #define DSI_CMD_FIFO_DEPTH 16
52 #define DSI_PIX_FIFO_DEPTH 256
53 #define DSI_PIX_FIFO_WIDTH 4
55 #define DSI0_CTRL 0x00
57 /* Command packet control. */
58 #define DSI0_TXPKT1C 0x04 /* AKA PKTC */
59 #define DSI1_TXPKT1C 0x04
60 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
61 # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
62 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
63 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
65 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
66 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
67 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
68 # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
69 /* Primary display where cmdfifo provides part of the payload and
70 * pixelvalve the rest.
72 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
73 /* Secondary display where cmdfifo provides part of the payload and
76 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
78 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
79 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
81 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
82 # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
83 /* Command only. Uses TXPKT1H and DISPLAY_NO */
84 # define DSI_TXPKT1C_CMD_CTRL_TX 0
85 /* Command with BTA for either ack or read data. */
86 # define DSI_TXPKT1C_CMD_CTRL_RX 1
87 /* Trigger according to TRIG_CMD */
88 # define DSI_TXPKT1C_CMD_CTRL_TRIG 2
89 /* BTA alone for getting error status after a command, or a TE trigger
90 * without a previous command.
92 # define DSI_TXPKT1C_CMD_CTRL_BTA 3
94 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
95 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
96 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
97 # define DSI_TXPKT1C_CMD_EN BIT(0)
99 /* Command packet header. */
100 #define DSI0_TXPKT1H 0x08 /* AKA PKTH */
101 #define DSI1_TXPKT1H 0x08
102 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
103 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
104 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
105 # define DSI_TXPKT1H_BC_PARAM_SHIFT 8
106 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
107 # define DSI_TXPKT1H_BC_DT_SHIFT 0
109 #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
110 #define DSI1_RXPKT1H 0x14
111 # define DSI_RXPKT1H_CRC_ERR BIT(31)
112 # define DSI_RXPKT1H_DET_ERR BIT(30)
113 # define DSI_RXPKT1H_ECC_ERR BIT(29)
114 # define DSI_RXPKT1H_COR_ERR BIT(28)
115 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
116 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
117 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
118 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
119 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
120 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
121 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
122 # define DSI_RXPKT1H_SHORT_1_SHIFT 16
123 # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
124 # define DSI_RXPKT1H_SHORT_0_SHIFT 8
125 # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
126 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
128 #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
129 #define DSI1_RXPKT2H 0x18
130 # define DSI_RXPKT1H_DET_ERR BIT(30)
131 # define DSI_RXPKT1H_ECC_ERR BIT(29)
132 # define DSI_RXPKT1H_COR_ERR BIT(28)
133 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
134 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
135 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
136 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
137 # define DSI_RXPKT1H_DT_SHIFT 0
139 #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
140 #define DSI1_TXPKT_CMD_FIFO 0x1c
142 #define DSI0_DISP0_CTRL 0x18
143 # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
144 # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
145 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
146 # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
147 # define DSI_DISP0_LP_STOP_DISABLE 0
148 # define DSI_DISP0_LP_STOP_PERLINE 1
149 # define DSI_DISP0_LP_STOP_PERFRAME 2
151 /* Transmit RGB pixels and null packets only during HACTIVE, instead
152 * of going to LP-STOP.
154 # define DSI_DISP_HACTIVE_NULL BIT(10)
155 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
156 # define DSI_DISP_VBLP_CTRL BIT(9)
157 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
158 # define DSI_DISP_HFP_CTRL BIT(8)
159 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
160 # define DSI_DISP_HBP_CTRL BIT(7)
161 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
162 # define DSI_DISP0_CHANNEL_SHIFT 5
163 /* Enables end events for HSYNC/VSYNC, not just start events. */
164 # define DSI_DISP0_ST_END BIT(4)
165 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
166 # define DSI_DISP0_PFORMAT_SHIFT 2
167 # define DSI_PFORMAT_RGB565 0
168 # define DSI_PFORMAT_RGB666_PACKED 1
169 # define DSI_PFORMAT_RGB666 2
170 # define DSI_PFORMAT_RGB888 3
171 /* Default is VIDEO mode. */
172 # define DSI_DISP0_COMMAND_MODE BIT(1)
173 # define DSI_DISP0_ENABLE BIT(0)
175 #define DSI0_DISP1_CTRL 0x1c
176 #define DSI1_DISP1_CTRL 0x2c
177 /* Format of the data written to TXPKT_PIX_FIFO. */
178 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
179 # define DSI_DISP1_PFORMAT_SHIFT 1
180 # define DSI_DISP1_PFORMAT_16BIT 0
181 # define DSI_DISP1_PFORMAT_24BIT 1
182 # define DSI_DISP1_PFORMAT_32BIT_LE 2
183 # define DSI_DISP1_PFORMAT_32BIT_BE 3
185 /* DISP1 is always command mode. */
186 # define DSI_DISP1_ENABLE BIT(0)
188 #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
190 #define DSI0_INT_STAT 0x24
191 #define DSI0_INT_EN 0x28
192 # define DSI1_INT_PHY_D3_ULPS BIT(30)
193 # define DSI1_INT_PHY_D3_STOP BIT(29)
194 # define DSI1_INT_PHY_D2_ULPS BIT(28)
195 # define DSI1_INT_PHY_D2_STOP BIT(27)
196 # define DSI1_INT_PHY_D1_ULPS BIT(26)
197 # define DSI1_INT_PHY_D1_STOP BIT(25)
198 # define DSI1_INT_PHY_D0_ULPS BIT(24)
199 # define DSI1_INT_PHY_D0_STOP BIT(23)
200 # define DSI1_INT_FIFO_ERR BIT(22)
201 # define DSI1_INT_PHY_DIR_RTF BIT(21)
202 # define DSI1_INT_PHY_RXLPDT BIT(20)
203 # define DSI1_INT_PHY_RXTRIG BIT(19)
204 # define DSI1_INT_PHY_D0_LPDT BIT(18)
205 # define DSI1_INT_PHY_DIR_FTR BIT(17)
207 /* Signaled when the clock lane enters the given state. */
208 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
209 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
210 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
212 /* Signaled on timeouts */
213 # define DSI1_INT_PR_TO BIT(13)
214 # define DSI1_INT_TA_TO BIT(12)
215 # define DSI1_INT_LPRX_TO BIT(11)
216 # define DSI1_INT_HSTX_TO BIT(10)
218 /* Contention on a line when trying to drive the line low */
219 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
220 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
222 /* Control error: incorrect line state sequence on data lane 0. */
223 # define DSI1_INT_ERR_CONTROL BIT(7)
224 /* LPDT synchronization error (bits received not a multiple of 8. */
226 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
227 /* Signaled after receiving an error packet from the display in
228 * response to a read.
230 # define DSI1_INT_RXPKT2 BIT(5)
231 /* Signaled after receiving a packet. The header and optional short
232 * response will be in RXPKT1H, and a long response will be in the
235 # define DSI1_INT_RXPKT1 BIT(4)
236 # define DSI1_INT_TXPKT2_DONE BIT(3)
237 # define DSI1_INT_TXPKT2_END BIT(2)
238 /* Signaled after all repeats of TXPKT1 are transferred. */
239 # define DSI1_INT_TXPKT1_DONE BIT(1)
240 /* Signaled after each TXPKT1 repeat is scheduled. */
241 # define DSI1_INT_TXPKT1_END BIT(0)
243 #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
244 DSI1_INT_ERR_CONTROL | \
245 DSI1_INT_ERR_CONT_LP0 | \
246 DSI1_INT_ERR_CONT_LP1 | \
252 #define DSI0_STAT 0x2c
253 #define DSI0_HSTX_TO_CNT 0x30
254 #define DSI0_LPRX_TO_CNT 0x34
255 #define DSI0_TA_TO_CNT 0x38
256 #define DSI0_PR_TO_CNT 0x3c
257 #define DSI0_PHYC 0x40
258 # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
259 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
260 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
261 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
262 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
263 # define DSI1_PHYC_CLANE_ULPS BIT(17)
264 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
265 # define DSI_PHYC_DLANE3_ULPS BIT(13)
266 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
267 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
268 # define DSI0_PHYC_CLANE_ULPS BIT(9)
269 # define DSI_PHYC_DLANE2_ULPS BIT(9)
270 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
271 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
272 # define DSI_PHYC_DLANE1_ULPS BIT(5)
273 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
274 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
275 # define DSI_PHYC_DLANE0_ULPS BIT(1)
276 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
278 #define DSI0_HS_CLT0 0x44
279 #define DSI0_HS_CLT1 0x48
280 #define DSI0_HS_CLT2 0x4c
281 #define DSI0_HS_DLT3 0x50
282 #define DSI0_HS_DLT4 0x54
283 #define DSI0_HS_DLT5 0x58
284 #define DSI0_HS_DLT6 0x5c
285 #define DSI0_HS_DLT7 0x60
287 #define DSI0_PHY_AFEC0 0x64
288 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
289 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
290 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
291 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
292 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
293 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
294 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
295 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
296 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
297 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
298 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
299 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
300 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
301 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
302 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
303 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
304 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
305 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
306 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
307 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
308 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
309 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
310 # define DSI1_PHY_AFEC0_RESET BIT(13)
311 # define DSI1_PHY_AFEC0_PD BIT(12)
312 # define DSI0_PHY_AFEC0_RESET BIT(11)
313 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
314 # define DSI0_PHY_AFEC0_PD BIT(10)
315 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
316 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
317 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
318 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
319 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
320 # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
321 # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
322 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
323 # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
325 #define DSI0_PHY_AFEC1 0x68
326 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
327 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
328 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
329 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
330 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
331 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
333 #define DSI0_TST_SEL 0x6c
334 #define DSI0_TST_MON 0x70
336 # define DSI_ID_VALUE 0x00647369
338 #define DSI1_CTRL 0x00
339 # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
340 # define DSI_CTRL_HS_CLKC_SHIFT 14
341 # define DSI_CTRL_HS_CLKC_BYTE 0
342 # define DSI_CTRL_HS_CLKC_DDR2 1
343 # define DSI_CTRL_HS_CLKC_DDR 2
345 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
346 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
347 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
348 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
349 # define DSI_CTRL_CAL_BYTE BIT(9)
350 # define DSI_CTRL_INV_BYTE BIT(8)
351 # define DSI_CTRL_CLR_LDF BIT(7)
352 # define DSI0_CTRL_CLR_PBCF BIT(6)
353 # define DSI1_CTRL_CLR_RXF BIT(6)
354 # define DSI0_CTRL_CLR_CPBCF BIT(5)
355 # define DSI1_CTRL_CLR_PDF BIT(5)
356 # define DSI0_CTRL_CLR_PDF BIT(4)
357 # define DSI1_CTRL_CLR_CDF BIT(4)
358 # define DSI0_CTRL_CLR_CDF BIT(3)
359 # define DSI0_CTRL_CTRL2 BIT(2)
360 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
361 # define DSI0_CTRL_CTRL1 BIT(1)
362 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
363 # define DSI0_CTRL_CTRL0 BIT(0)
364 # define DSI1_CTRL_EN BIT(0)
365 # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
366 DSI0_CTRL_CLR_PBCF | \
367 DSI0_CTRL_CLR_CPBCF | \
368 DSI0_CTRL_CLR_PDF | \
370 # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
371 DSI1_CTRL_CLR_RXF | \
372 DSI1_CTRL_CLR_PDF | \
375 #define DSI1_TXPKT2C 0x0c
376 #define DSI1_TXPKT2H 0x10
377 #define DSI1_TXPKT_PIX_FIFO 0x20
378 #define DSI1_RXPKT_FIFO 0x24
379 #define DSI1_DISP0_CTRL 0x28
380 #define DSI1_INT_STAT 0x30
381 #define DSI1_INT_EN 0x34
382 /* State reporting bits. These mostly behave like INT_STAT, where
383 * writing a 1 clears the bit.
385 #define DSI1_STAT 0x38
386 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
387 # define DSI1_STAT_PHY_D3_STOP BIT(30)
388 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
389 # define DSI1_STAT_PHY_D2_STOP BIT(28)
390 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
391 # define DSI1_STAT_PHY_D1_STOP BIT(26)
392 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
393 # define DSI1_STAT_PHY_D0_STOP BIT(24)
394 # define DSI1_STAT_FIFO_ERR BIT(23)
395 # define DSI1_STAT_PHY_RXLPDT BIT(22)
396 # define DSI1_STAT_PHY_RXTRIG BIT(21)
397 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
398 /* Set when in forward direction */
399 # define DSI1_STAT_PHY_DIR BIT(19)
400 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
401 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
402 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
403 # define DSI1_STAT_PR_TO BIT(15)
404 # define DSI1_STAT_TA_TO BIT(14)
405 # define DSI1_STAT_LPRX_TO BIT(13)
406 # define DSI1_STAT_HSTX_TO BIT(12)
407 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
408 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
409 # define DSI1_STAT_ERR_CONTROL BIT(9)
410 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
411 # define DSI1_STAT_RXPKT2 BIT(7)
412 # define DSI1_STAT_RXPKT1 BIT(6)
413 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
414 # define DSI1_STAT_TXPKT2_DONE BIT(4)
415 # define DSI1_STAT_TXPKT2_END BIT(3)
416 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
417 # define DSI1_STAT_TXPKT1_DONE BIT(1)
418 # define DSI1_STAT_TXPKT1_END BIT(0)
420 #define DSI1_HSTX_TO_CNT 0x3c
421 #define DSI1_LPRX_TO_CNT 0x40
422 #define DSI1_TA_TO_CNT 0x44
423 #define DSI1_PR_TO_CNT 0x48
424 #define DSI1_PHYC 0x4c
426 #define DSI1_HS_CLT0 0x50
427 # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
428 # define DSI_HS_CLT0_CZERO_SHIFT 18
429 # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
430 # define DSI_HS_CLT0_CPRE_SHIFT 9
431 # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
432 # define DSI_HS_CLT0_CPREP_SHIFT 0
434 #define DSI1_HS_CLT1 0x54
435 # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
436 # define DSI_HS_CLT1_CTRAIL_SHIFT 9
437 # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
438 # define DSI_HS_CLT1_CPOST_SHIFT 0
440 #define DSI1_HS_CLT2 0x58
441 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
442 # define DSI_HS_CLT2_WUP_SHIFT 0
444 #define DSI1_HS_DLT3 0x5c
445 # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
446 # define DSI_HS_DLT3_EXIT_SHIFT 18
447 # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
448 # define DSI_HS_DLT3_ZERO_SHIFT 9
449 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
450 # define DSI_HS_DLT3_PRE_SHIFT 0
452 #define DSI1_HS_DLT4 0x60
453 # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
454 # define DSI_HS_DLT4_ANLAT_SHIFT 18
455 # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
456 # define DSI_HS_DLT4_TRAIL_SHIFT 9
457 # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
458 # define DSI_HS_DLT4_LPX_SHIFT 0
460 #define DSI1_HS_DLT5 0x64
461 # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
462 # define DSI_HS_DLT5_INIT_SHIFT 0
464 #define DSI1_HS_DLT6 0x68
465 # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
466 # define DSI_HS_DLT6_TA_GET_SHIFT 24
467 # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
468 # define DSI_HS_DLT6_TA_SURE_SHIFT 16
469 # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
470 # define DSI_HS_DLT6_TA_GO_SHIFT 8
471 # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
472 # define DSI_HS_DLT6_LP_LPX_SHIFT 0
474 #define DSI1_HS_DLT7 0x6c
475 # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
476 # define DSI_HS_DLT7_LP_WUP_SHIFT 0
478 #define DSI1_PHY_AFEC0 0x70
480 #define DSI1_PHY_AFEC1 0x74
481 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
482 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
483 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
484 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
485 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
486 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
487 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
488 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
489 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
490 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
492 #define DSI1_TST_SEL 0x78
493 #define DSI1_TST_MON 0x7c
494 #define DSI1_PHY_TST1 0x80
495 #define DSI1_PHY_TST2 0x84
496 #define DSI1_PHY_FIFO_STAT 0x88
497 /* Actually, all registers in the range that aren't otherwise claimed
498 * will return the ID.
502 /* General DSI hardware state. */
504 struct platform_device *pdev;
506 struct mipi_dsi_host dsi_host;
507 struct drm_encoder *encoder;
508 struct drm_bridge *bridge;
512 struct dma_chan *reg_dma_chan;
513 dma_addr_t reg_dma_paddr;
515 dma_addr_t reg_paddr;
517 /* Whether we're on bcm2835's DSI0 or DSI1. */
520 /* DSI channel for the panel we're connected to. */
527 /* Input clock from CPRMAN to the digital PHY, for the DSI
530 struct clk *escape_clock;
532 /* Input clock to the analog PHY, used to generate the DSI bit
535 struct clk *pll_phy_clock;
537 /* HS Clocks generated within the DSI analog PHY. */
538 struct clk_fixed_factor phy_clocks[3];
540 struct clk_hw_onecell_data *clk_onecell;
542 /* Pixel clock output to the pixelvalve, generated from the HS
545 struct clk *pixel_clock;
547 struct completion xfer_completion;
551 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
554 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
556 struct dma_chan *chan = dsi->reg_dma_chan;
557 struct dma_async_tx_descriptor *tx;
561 /* DSI0 should be able to write normally. */
563 writel(val, dsi->regs + offset);
567 *dsi->reg_dma_mem = val;
569 tx = chan->device->device_prep_dma_memcpy(chan,
570 dsi->reg_paddr + offset,
574 DRM_ERROR("Failed to set up DMA register write\n");
578 cookie = tx->tx_submit(tx);
579 ret = dma_submit_error(cookie);
581 DRM_ERROR("Failed to submit DMA: %d\n", ret);
584 ret = dma_sync_wait(chan, cookie);
586 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
589 #define DSI_READ(offset) readl(dsi->regs + (offset))
590 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
591 #define DSI_PORT_READ(offset) \
592 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
593 #define DSI_PORT_WRITE(offset, val) \
594 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
595 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
597 /* VC4 DSI encoder KMS struct */
598 struct vc4_dsi_encoder {
599 struct vc4_encoder base;
603 static inline struct vc4_dsi_encoder *
604 to_vc4_dsi_encoder(struct drm_encoder *encoder)
606 return container_of(encoder, struct vc4_dsi_encoder, base.base);
609 #define DSI_REG(reg) { reg, #reg }
610 static const struct {
616 DSI_REG(DSI0_HSTX_TO_CNT),
617 DSI_REG(DSI0_LPRX_TO_CNT),
618 DSI_REG(DSI0_TA_TO_CNT),
619 DSI_REG(DSI0_PR_TO_CNT),
620 DSI_REG(DSI0_DISP0_CTRL),
621 DSI_REG(DSI0_DISP1_CTRL),
622 DSI_REG(DSI0_INT_STAT),
623 DSI_REG(DSI0_INT_EN),
625 DSI_REG(DSI0_HS_CLT0),
626 DSI_REG(DSI0_HS_CLT1),
627 DSI_REG(DSI0_HS_CLT2),
628 DSI_REG(DSI0_HS_DLT3),
629 DSI_REG(DSI0_HS_DLT4),
630 DSI_REG(DSI0_HS_DLT5),
631 DSI_REG(DSI0_HS_DLT6),
632 DSI_REG(DSI0_HS_DLT7),
633 DSI_REG(DSI0_PHY_AFEC0),
634 DSI_REG(DSI0_PHY_AFEC1),
638 static const struct {
644 DSI_REG(DSI1_HSTX_TO_CNT),
645 DSI_REG(DSI1_LPRX_TO_CNT),
646 DSI_REG(DSI1_TA_TO_CNT),
647 DSI_REG(DSI1_PR_TO_CNT),
648 DSI_REG(DSI1_DISP0_CTRL),
649 DSI_REG(DSI1_DISP1_CTRL),
650 DSI_REG(DSI1_INT_STAT),
651 DSI_REG(DSI1_INT_EN),
653 DSI_REG(DSI1_HS_CLT0),
654 DSI_REG(DSI1_HS_CLT1),
655 DSI_REG(DSI1_HS_CLT2),
656 DSI_REG(DSI1_HS_DLT3),
657 DSI_REG(DSI1_HS_DLT4),
658 DSI_REG(DSI1_HS_DLT5),
659 DSI_REG(DSI1_HS_DLT6),
660 DSI_REG(DSI1_HS_DLT7),
661 DSI_REG(DSI1_PHY_AFEC0),
662 DSI_REG(DSI1_PHY_AFEC1),
666 static void vc4_dsi_dump_regs(struct vc4_dsi *dsi)
670 if (dsi->port == 0) {
671 for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {
672 DRM_INFO("0x%04x (%s): 0x%08x\n",
673 dsi0_regs[i].reg, dsi0_regs[i].name,
674 DSI_READ(dsi0_regs[i].reg));
677 for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {
678 DRM_INFO("0x%04x (%s): 0x%08x\n",
679 dsi1_regs[i].reg, dsi1_regs[i].name,
680 DSI_READ(dsi1_regs[i].reg));
685 #ifdef CONFIG_DEBUG_FS
686 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused)
688 struct drm_info_node *node = (struct drm_info_node *)m->private;
689 struct drm_device *drm = node->minor->dev;
690 struct vc4_dev *vc4 = to_vc4_dev(drm);
691 int dsi_index = (uintptr_t)node->info_ent->data;
692 struct vc4_dsi *dsi = (dsi_index == 1 ? vc4->dsi1 : NULL);
698 if (dsi->port == 0) {
699 for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {
700 seq_printf(m, "0x%04x (%s): 0x%08x\n",
701 dsi0_regs[i].reg, dsi0_regs[i].name,
702 DSI_READ(dsi0_regs[i].reg));
705 for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {
706 seq_printf(m, "0x%04x (%s): 0x%08x\n",
707 dsi1_regs[i].reg, dsi1_regs[i].name,
708 DSI_READ(dsi1_regs[i].reg));
716 static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder)
718 drm_encoder_cleanup(encoder);
721 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
722 .destroy = vc4_dsi_encoder_destroy,
725 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
727 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
730 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
732 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
734 DSI_PORT_WRITE(PHY_AFEC0, afec0);
737 /* Enters or exits Ultra Low Power State. */
738 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
740 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
741 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
742 DSI_PHYC_DLANE0_ULPS |
743 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
744 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
745 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
746 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
747 DSI1_STAT_PHY_D0_ULPS |
748 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
749 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
750 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
751 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
752 DSI1_STAT_PHY_D0_STOP |
753 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
754 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
755 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
757 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
758 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
760 if (ulps == ulps_currently_enabled)
763 DSI_PORT_WRITE(STAT, stat_ulps);
764 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
765 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
767 dev_warn(&dsi->pdev->dev,
768 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
769 DSI_PORT_READ(STAT));
770 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
771 vc4_dsi_latch_ulps(dsi, false);
775 /* The DSI module can't be disabled while the module is
776 * generating ULPS state. So, to be able to disable the
777 * module, we have the AFE latch the ULPS state and continue
778 * on to having the module enter STOP.
780 vc4_dsi_latch_ulps(dsi, ulps);
782 DSI_PORT_WRITE(STAT, stat_stop);
783 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
784 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
786 dev_warn(&dsi->pdev->dev,
787 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
788 DSI_PORT_READ(STAT));
789 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
795 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
797 /* The HS timings have to be rounded up to a multiple of 8
798 * because we're using the byte clock.
800 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
803 /* ESC always runs at 100Mhz. */
804 #define ESC_TIME_NS 10
807 dsi_esc_timing(u32 ns)
809 return DIV_ROUND_UP(ns, ESC_TIME_NS);
812 static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
814 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
815 struct vc4_dsi *dsi = vc4_encoder->dsi;
816 struct device *dev = &dsi->pdev->dev;
818 drm_bridge_disable(dsi->bridge);
819 vc4_dsi_ulps(dsi, true);
820 drm_bridge_post_disable(dsi->bridge);
822 clk_disable_unprepare(dsi->pll_phy_clock);
823 clk_disable_unprepare(dsi->escape_clock);
824 clk_disable_unprepare(dsi->pixel_clock);
829 /* Extends the mode's blank intervals to handle BCM2835's integer-only
832 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
833 * driver since most peripherals are hanging off of the PLLD_PER
834 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
835 * the pixel clock), only has an integer divider off of DSI.
837 * To get our panel mode to refresh at the expected 60Hz, we need to
838 * extend the horizontal blank time. This means we drive a
839 * higher-than-expected clock rate to the panel, but that's what the
842 static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
843 const struct drm_display_mode *mode,
844 struct drm_display_mode *adjusted_mode)
846 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
847 struct vc4_dsi *dsi = vc4_encoder->dsi;
848 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
849 unsigned long parent_rate = clk_get_rate(phy_parent);
850 unsigned long pixel_clock_hz = mode->clock * 1000;
851 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
854 /* Find what divider gets us a faster clock than the requested
857 for (divider = 1; divider < 8; divider++) {
858 if (parent_rate / divider < pll_clock) {
864 /* Now that we've picked a PLL divider, calculate back to its
867 pll_clock = parent_rate / divider;
868 pixel_clock_hz = pll_clock / dsi->divider;
870 adjusted_mode->clock = pixel_clock_hz / 1000;
872 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
873 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
875 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
876 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
881 static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
883 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
884 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
885 struct vc4_dsi *dsi = vc4_encoder->dsi;
886 struct device *dev = &dsi->pdev->dev;
887 bool debug_dump_regs = false;
888 unsigned long hs_clock;
890 /* Minimum LP state duration in escape clock cycles. */
891 u32 lpx = dsi_esc_timing(60);
892 unsigned long pixel_clock_hz = mode->clock * 1000;
893 unsigned long dsip_clock;
894 unsigned long phy_clock;
897 ret = pm_runtime_get_sync(dev);
899 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port);
903 if (debug_dump_regs) {
904 DRM_INFO("DSI regs before:\n");
905 vc4_dsi_dump_regs(dsi);
908 /* Round up the clk_set_rate() request slightly, since
909 * PLLD_DSI1 is an integer divider and its rate selection will
912 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
913 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
915 dev_err(&dsi->pdev->dev,
916 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
919 /* Reset the DSI and all its fifos. */
921 DSI_CTRL_SOFT_RESET_CFG |
922 DSI_PORT_BIT(CTRL_RESET_FIFOS));
925 DSI_CTRL_HSDT_EOT_DISABLE |
926 DSI_CTRL_RX_LPDT_EOT_DISABLE);
928 /* Clear all stat bits so we see what has happened during enable. */
929 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
931 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
932 if (dsi->port == 0) {
933 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
934 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
937 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
939 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
940 afec0 |= DSI0_PHY_AFEC0_RESET;
942 DSI_PORT_WRITE(PHY_AFEC0, afec0);
944 DSI_PORT_WRITE(PHY_AFEC1,
945 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
946 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
947 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
949 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
950 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
951 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
952 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
953 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
954 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
955 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
958 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
960 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
962 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
964 afec0 |= DSI1_PHY_AFEC0_RESET;
966 DSI_PORT_WRITE(PHY_AFEC0, afec0);
968 DSI_PORT_WRITE(PHY_AFEC1, 0);
970 /* AFEC reset hold time */
974 ret = clk_prepare_enable(dsi->escape_clock);
976 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
980 ret = clk_prepare_enable(dsi->pll_phy_clock);
982 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
986 hs_clock = clk_get_rate(dsi->pll_phy_clock);
988 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
989 * not the pixel clock rate. DSIxP take from the APHY's byte,
990 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
991 * that rate. Separately, a value derived from PIX_CLK_DIV
992 * and HS_CLKC is fed into the PV to divide down to the actual
993 * pixel clock for pushing pixels into DSI.
995 dsip_clock = phy_clock / 8;
996 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
998 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
1002 ret = clk_prepare_enable(dsi->pixel_clock);
1004 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1008 /* How many ns one DSI unit interval is. Note that the clock
1009 * is DDR, so there's an extra divide by 2.
1011 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1013 DSI_PORT_WRITE(HS_CLT0,
1014 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1015 DSI_HS_CLT0_CZERO) |
1016 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1018 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1019 DSI_HS_CLT0_CPREP));
1021 DSI_PORT_WRITE(HS_CLT1,
1022 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1023 DSI_HS_CLT1_CTRAIL) |
1024 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1025 DSI_HS_CLT1_CPOST));
1027 DSI_PORT_WRITE(HS_CLT2,
1028 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1031 DSI_PORT_WRITE(HS_DLT3,
1032 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1034 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1036 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1039 DSI_PORT_WRITE(HS_DLT4,
1040 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1042 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1043 dsi_hs_timing(ui_ns, 60, 4)),
1044 DSI_HS_DLT4_TRAIL) |
1045 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1047 /* T_INIT is how long STOP is driven after power-up to
1048 * indicate to the slave (also coming out of power-up) that
1049 * master init is complete, and should be greater than the
1050 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1051 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1052 * T_INIT,SLAVE, while allowing protocols on top of it to give
1053 * greater minimums. The vc4 firmware uses an extremely
1054 * conservative 5ms, and we maintain that here.
1056 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1057 5 * 1000 * 1000, 0),
1060 DSI_PORT_WRITE(HS_DLT6,
1061 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1062 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1063 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1064 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1066 DSI_PORT_WRITE(HS_DLT7,
1067 VC4_SET_FIELD(dsi_esc_timing(1000000),
1068 DSI_HS_DLT7_LP_WUP));
1070 DSI_PORT_WRITE(PHYC,
1071 DSI_PHYC_DLANE0_ENABLE |
1072 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1073 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1074 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1075 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1076 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1077 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1079 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1080 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1082 DSI_PORT_WRITE(CTRL,
1083 DSI_PORT_READ(CTRL) |
1086 /* HS timeout in HS clock cycles: disabled. */
1087 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1088 /* LP receive timeout in HS clocks. */
1089 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1090 /* Bus turnaround timeout */
1091 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1092 /* Display reset sequence timeout */
1093 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1095 /* Set up DISP1 for transferring long command payloads through
1098 DSI_PORT_WRITE(DISP1_CTRL,
1099 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1100 DSI_DISP1_PFORMAT) |
1103 /* Ungate the block. */
1105 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1107 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1109 /* Bring AFE out of reset. */
1110 if (dsi->port == 0) {
1112 DSI_PORT_WRITE(PHY_AFEC0,
1113 DSI_PORT_READ(PHY_AFEC0) &
1114 ~DSI1_PHY_AFEC0_RESET);
1117 vc4_dsi_ulps(dsi, false);
1119 drm_bridge_pre_enable(dsi->bridge);
1121 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1122 DSI_PORT_WRITE(DISP0_CTRL,
1123 VC4_SET_FIELD(dsi->divider,
1124 DSI_DISP0_PIX_CLK_DIV) |
1125 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1126 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1127 DSI_DISP0_LP_STOP_CTRL) |
1131 DSI_PORT_WRITE(DISP0_CTRL,
1132 DSI_DISP0_COMMAND_MODE |
1136 drm_bridge_enable(dsi->bridge);
1138 if (debug_dump_regs) {
1139 DRM_INFO("DSI regs after:\n");
1140 vc4_dsi_dump_regs(dsi);
1144 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1145 const struct mipi_dsi_msg *msg)
1147 struct vc4_dsi *dsi = host_to_dsi(host);
1148 struct mipi_dsi_packet packet;
1149 u32 pkth = 0, pktc = 0;
1151 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1152 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1154 mipi_dsi_create_packet(&packet, msg);
1156 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1157 pkth |= VC4_SET_FIELD(packet.header[1] |
1158 (packet.header[2] << 8),
1159 DSI_TXPKT1H_BC_PARAM);
1161 /* Divide data across the various FIFOs we have available.
1162 * The command FIFO takes byte-oriented data, but is of
1163 * limited size. The pixel FIFO (never actually used for
1164 * pixel data in reality) is word oriented, and substantially
1165 * larger. So, we use the pixel FIFO for most of the data,
1166 * sending the residual bytes in the command FIFO at the start.
1168 * With this arrangement, the command FIFO will never get full.
1170 if (packet.payload_length <= 16) {
1171 cmd_fifo_len = packet.payload_length;
1174 cmd_fifo_len = (packet.payload_length %
1175 DSI_PIX_FIFO_WIDTH);
1176 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1177 DSI_PIX_FIFO_WIDTH);
1180 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1182 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1186 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1187 DSI_TXPKT1C_CMD_CTRL);
1189 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1190 DSI_TXPKT1C_CMD_CTRL);
1193 for (i = 0; i < cmd_fifo_len; i++)
1194 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1195 for (i = 0; i < pix_fifo_len; i++) {
1196 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1198 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1205 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1206 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1208 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1210 /* Send one copy of the packet. Larger repeats are used for pixel
1211 * data in command mode.
1213 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1215 pktc |= DSI_TXPKT1C_CMD_EN;
1217 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1218 DSI_TXPKT1C_DISPLAY_NO);
1220 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1221 DSI_TXPKT1C_DISPLAY_NO);
1224 /* Enable the appropriate interrupt for the transfer completion. */
1225 dsi->xfer_result = 0;
1226 reinit_completion(&dsi->xfer_completion);
1227 DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1229 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1230 DSI1_INT_PHY_DIR_RTF));
1232 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1233 DSI1_INT_TXPKT1_DONE));
1236 /* Send the packet. */
1237 DSI_PORT_WRITE(TXPKT1H, pkth);
1238 DSI_PORT_WRITE(TXPKT1C, pktc);
1240 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1241 msecs_to_jiffies(1000))) {
1242 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1243 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1244 DSI_PORT_READ(INT_STAT));
1247 ret = dsi->xfer_result;
1250 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1253 goto reset_fifo_and_return;
1255 if (ret == 0 && msg->rx_len) {
1256 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1257 u8 *msg_rx = msg->rx_buf;
1259 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1260 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1261 DSI_RXPKT1H_BC_PARAM);
1263 if (rxlen != msg->rx_len) {
1264 DRM_ERROR("DSI returned %db, expecting %db\n",
1265 rxlen, (int)msg->rx_len);
1267 goto reset_fifo_and_return;
1270 for (i = 0; i < msg->rx_len; i++)
1271 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1273 /* FINISHME: Handle AWER */
1275 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1276 DSI_RXPKT1H_SHORT_0);
1277 if (msg->rx_len > 1) {
1278 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1279 DSI_RXPKT1H_SHORT_1);
1286 reset_fifo_and_return:
1287 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1289 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1291 DSI_PORT_WRITE(CTRL,
1292 DSI_PORT_READ(CTRL) |
1293 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1295 DSI_PORT_WRITE(TXPKT1C, 0);
1296 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1300 static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1301 struct mipi_dsi_device *device)
1303 struct vc4_dsi *dsi = host_to_dsi(host);
1305 dsi->lanes = device->lanes;
1306 dsi->channel = device->channel;
1307 dsi->mode_flags = device->mode_flags;
1309 switch (device->format) {
1310 case MIPI_DSI_FMT_RGB888:
1311 dsi->format = DSI_PFORMAT_RGB888;
1312 dsi->divider = 24 / dsi->lanes;
1314 case MIPI_DSI_FMT_RGB666:
1315 dsi->format = DSI_PFORMAT_RGB666;
1316 dsi->divider = 24 / dsi->lanes;
1318 case MIPI_DSI_FMT_RGB666_PACKED:
1319 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1320 dsi->divider = 18 / dsi->lanes;
1322 case MIPI_DSI_FMT_RGB565:
1323 dsi->format = DSI_PFORMAT_RGB565;
1324 dsi->divider = 16 / dsi->lanes;
1327 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1332 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1333 dev_err(&dsi->pdev->dev,
1334 "Only VIDEO mode panels supported currently.\n");
1341 static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1342 struct mipi_dsi_device *device)
1347 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1348 .attach = vc4_dsi_host_attach,
1349 .detach = vc4_dsi_host_detach,
1350 .transfer = vc4_dsi_host_transfer,
1353 static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1354 .disable = vc4_dsi_encoder_disable,
1355 .enable = vc4_dsi_encoder_enable,
1356 .mode_fixup = vc4_dsi_encoder_mode_fixup,
1359 static const struct of_device_id vc4_dsi_dt_match[] = {
1360 { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1364 static void dsi_handle_error(struct vc4_dsi *dsi,
1365 irqreturn_t *ret, u32 stat, u32 bit,
1371 DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1376 * Initial handler for port 1 where we need the reg_dma workaround.
1377 * The register DMA writes sleep, so we can't do it in the top half.
1378 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1379 * parent interrupt contrller until our interrupt thread is done.
1381 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1383 struct vc4_dsi *dsi = data;
1384 u32 stat = DSI_PORT_READ(INT_STAT);
1389 return IRQ_WAKE_THREAD;
1393 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1394 * 1 where we need the reg_dma workaround.
1396 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1398 struct vc4_dsi *dsi = data;
1399 u32 stat = DSI_PORT_READ(INT_STAT);
1400 irqreturn_t ret = IRQ_NONE;
1402 DSI_PORT_WRITE(INT_STAT, stat);
1404 dsi_handle_error(dsi, &ret, stat,
1405 DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1406 dsi_handle_error(dsi, &ret, stat,
1407 DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1408 dsi_handle_error(dsi, &ret, stat,
1409 DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1410 dsi_handle_error(dsi, &ret, stat,
1411 DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1412 dsi_handle_error(dsi, &ret, stat,
1413 DSI1_INT_HSTX_TO, "HSTX timeout");
1414 dsi_handle_error(dsi, &ret, stat,
1415 DSI1_INT_LPRX_TO, "LPRX timeout");
1416 dsi_handle_error(dsi, &ret, stat,
1417 DSI1_INT_TA_TO, "turnaround timeout");
1418 dsi_handle_error(dsi, &ret, stat,
1419 DSI1_INT_PR_TO, "peripheral reset timeout");
1421 if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1422 complete(&dsi->xfer_completion);
1424 } else if (stat & DSI1_INT_HSTX_TO) {
1425 complete(&dsi->xfer_completion);
1426 dsi->xfer_result = -ETIMEDOUT;
1434 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1435 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1439 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1441 struct device *dev = &dsi->pdev->dev;
1442 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1443 static const struct {
1444 const char *dsi0_name, *dsi1_name;
1447 { "dsi0_byte", "dsi1_byte", 8 },
1448 { "dsi0_ddr2", "dsi1_ddr2", 4 },
1449 { "dsi0_ddr", "dsi1_ddr", 2 },
1453 dsi->clk_onecell = devm_kzalloc(dev,
1454 sizeof(*dsi->clk_onecell) +
1455 ARRAY_SIZE(phy_clocks) *
1456 sizeof(struct clk_hw *),
1458 if (!dsi->clk_onecell)
1460 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1462 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1463 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1464 struct clk_init_data init;
1467 /* We just use core fixed factor clock ops for the PHY
1468 * clocks. The clocks are actually gated by the
1469 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1470 * setting if we use the DDR/DDR2 clocks. However,
1471 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1472 * setting both our parent DSI PLL's rate and this
1473 * clock's rate, so it knows if DDR/DDR2 are going to
1474 * be used and could enable the gates itself.
1477 fix->div = phy_clocks[i].div;
1478 fix->hw.init = &init;
1480 memset(&init, 0, sizeof(init));
1481 init.parent_names = &parent_name;
1482 init.num_parents = 1;
1484 init.name = phy_clocks[i].dsi1_name;
1486 init.name = phy_clocks[i].dsi0_name;
1487 init.ops = &clk_fixed_factor_ops;
1489 ret = devm_clk_hw_register(dev, &fix->hw);
1493 dsi->clk_onecell->hws[i] = &fix->hw;
1496 return of_clk_add_hw_provider(dev->of_node,
1497 of_clk_hw_onecell_get,
1501 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1503 struct platform_device *pdev = to_platform_device(dev);
1504 struct drm_device *drm = dev_get_drvdata(master);
1505 struct vc4_dev *vc4 = to_vc4_dev(drm);
1506 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1507 struct vc4_dsi_encoder *vc4_dsi_encoder;
1508 struct drm_panel *panel;
1509 const struct of_device_id *match;
1510 dma_cap_mask_t dma_mask;
1513 match = of_match_device(vc4_dsi_dt_match, dev);
1517 dsi->port = (uintptr_t)match->data;
1519 vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1521 if (!vc4_dsi_encoder)
1523 vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1524 vc4_dsi_encoder->dsi = dsi;
1525 dsi->encoder = &vc4_dsi_encoder->base.base;
1527 dsi->regs = vc4_ioremap_regs(pdev, 0);
1528 if (IS_ERR(dsi->regs))
1529 return PTR_ERR(dsi->regs);
1531 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1532 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1533 DSI_PORT_READ(ID), DSI_ID_VALUE);
1537 /* DSI1 has a broken AXI slave that doesn't respond to writes
1538 * from the ARM. It does handle writes from the DMA engine,
1539 * so set up a channel for talking to it.
1541 if (dsi->port == 1) {
1542 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1543 &dsi->reg_dma_paddr,
1545 if (!dsi->reg_dma_mem) {
1546 DRM_ERROR("Failed to get DMA memory\n");
1550 dma_cap_zero(dma_mask);
1551 dma_cap_set(DMA_MEMCPY, dma_mask);
1552 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1553 if (IS_ERR(dsi->reg_dma_chan)) {
1554 ret = PTR_ERR(dsi->reg_dma_chan);
1555 if (ret != -EPROBE_DEFER)
1556 DRM_ERROR("Failed to get DMA channel: %d\n",
1561 /* Get the physical address of the device's registers. The
1562 * struct resource for the regs gives us the bus address
1565 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1569 init_completion(&dsi->xfer_completion);
1570 /* At startup enable error-reporting interrupts and nothing else. */
1571 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1572 /* Clear any existing interrupt state. */
1573 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1575 if (dsi->reg_dma_mem)
1576 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1577 vc4_dsi_irq_defer_to_thread_handler,
1578 vc4_dsi_irq_handler,
1582 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1583 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1585 if (ret != -EPROBE_DEFER)
1586 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1590 dsi->escape_clock = devm_clk_get(dev, "escape");
1591 if (IS_ERR(dsi->escape_clock)) {
1592 ret = PTR_ERR(dsi->escape_clock);
1593 if (ret != -EPROBE_DEFER)
1594 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1598 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1599 if (IS_ERR(dsi->pll_phy_clock)) {
1600 ret = PTR_ERR(dsi->pll_phy_clock);
1601 if (ret != -EPROBE_DEFER)
1602 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1606 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1607 if (IS_ERR(dsi->pixel_clock)) {
1608 ret = PTR_ERR(dsi->pixel_clock);
1609 if (ret != -EPROBE_DEFER)
1610 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1614 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1615 &panel, &dsi->bridge);
1617 /* If the bridge or panel pointed by dev->of_node is not
1618 * enabled, just return 0 here so that we don't prevent the DRM
1619 * dev from being registered. Of course that means the DSI
1620 * encoder won't be exposed, but that's not a problem since
1621 * nothing is connected to it.
1630 dsi->bridge = devm_drm_panel_bridge_add(dev, panel,
1631 DRM_MODE_CONNECTOR_DSI);
1632 if (IS_ERR(dsi->bridge))
1633 return PTR_ERR(dsi->bridge);
1636 /* The esc clock rate is supposed to always be 100Mhz. */
1637 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1639 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1643 ret = vc4_dsi_init_phy_clocks(dsi);
1650 drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs,
1651 DRM_MODE_ENCODER_DSI, NULL);
1652 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1654 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL);
1656 dev_err(dev, "bridge attach failed: %d\n", ret);
1659 /* Disable the atomic helper calls into the bridge. We
1660 * manually call the bridge pre_enable / enable / etc. calls
1661 * from our driver, since we need to sequence them within the
1662 * encoder's enable/disable paths.
1664 dsi->encoder->bridge = NULL;
1666 pm_runtime_enable(dev);
1671 static void vc4_dsi_unbind(struct device *dev, struct device *master,
1674 struct drm_device *drm = dev_get_drvdata(master);
1675 struct vc4_dev *vc4 = to_vc4_dev(drm);
1676 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1679 pm_runtime_disable(dev);
1681 vc4_dsi_encoder_destroy(dsi->encoder);
1687 static const struct component_ops vc4_dsi_ops = {
1688 .bind = vc4_dsi_bind,
1689 .unbind = vc4_dsi_unbind,
1692 static int vc4_dsi_dev_probe(struct platform_device *pdev)
1694 struct device *dev = &pdev->dev;
1695 struct vc4_dsi *dsi;
1698 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1701 dev_set_drvdata(dev, dsi);
1705 /* Note, the initialization sequence for DSI and panels is
1706 * tricky. The component bind above won't get past its
1707 * -EPROBE_DEFER until the panel/bridge probes. The
1708 * panel/bridge will return -EPROBE_DEFER until it has a
1709 * mipi_dsi_host to register its device to. So, we register
1710 * the host during pdev probe time, so vc4 as a whole can then
1711 * -EPROBE_DEFER its component bind process until the panel
1712 * successfully attaches.
1714 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1715 dsi->dsi_host.dev = dev;
1716 mipi_dsi_host_register(&dsi->dsi_host);
1718 ret = component_add(&pdev->dev, &vc4_dsi_ops);
1720 mipi_dsi_host_unregister(&dsi->dsi_host);
1727 static int vc4_dsi_dev_remove(struct platform_device *pdev)
1729 struct device *dev = &pdev->dev;
1730 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1732 component_del(&pdev->dev, &vc4_dsi_ops);
1733 mipi_dsi_host_unregister(&dsi->dsi_host);
1738 struct platform_driver vc4_dsi_driver = {
1739 .probe = vc4_dsi_dev_probe,
1740 .remove = vc4_dsi_dev_remove,
1743 .of_match_table = vc4_dsi_dt_match,