1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Broadcom
7 * DOC: VC4 DSI0/DSI1 module
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/component.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/i2c.h>
29 #include <linux/of_address.h>
30 #include <linux/of_platform.h>
31 #include <linux/pm_runtime.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_bridge.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_mipi_dsi.h>
37 #include <drm/drm_of.h>
38 #include <drm/drm_panel.h>
39 #include <drm/drm_probe_helper.h>
44 #define DSI_CMD_FIFO_DEPTH 16
45 #define DSI_PIX_FIFO_DEPTH 256
46 #define DSI_PIX_FIFO_WIDTH 4
48 #define DSI0_CTRL 0x00
50 /* Command packet control. */
51 #define DSI0_TXPKT1C 0x04 /* AKA PKTC */
52 #define DSI1_TXPKT1C 0x04
53 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
54 # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
55 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
56 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
58 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
59 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
60 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
61 # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
62 /* Primary display where cmdfifo provides part of the payload and
63 * pixelvalve the rest.
65 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
66 /* Secondary display where cmdfifo provides part of the payload and
69 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
71 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
72 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
74 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
75 # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
76 /* Command only. Uses TXPKT1H and DISPLAY_NO */
77 # define DSI_TXPKT1C_CMD_CTRL_TX 0
78 /* Command with BTA for either ack or read data. */
79 # define DSI_TXPKT1C_CMD_CTRL_RX 1
80 /* Trigger according to TRIG_CMD */
81 # define DSI_TXPKT1C_CMD_CTRL_TRIG 2
82 /* BTA alone for getting error status after a command, or a TE trigger
83 * without a previous command.
85 # define DSI_TXPKT1C_CMD_CTRL_BTA 3
87 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
88 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
89 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
90 # define DSI_TXPKT1C_CMD_EN BIT(0)
92 /* Command packet header. */
93 #define DSI0_TXPKT1H 0x08 /* AKA PKTH */
94 #define DSI1_TXPKT1H 0x08
95 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
96 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
97 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
98 # define DSI_TXPKT1H_BC_PARAM_SHIFT 8
99 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
100 # define DSI_TXPKT1H_BC_DT_SHIFT 0
102 #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
103 #define DSI1_RXPKT1H 0x14
104 # define DSI_RXPKT1H_CRC_ERR BIT(31)
105 # define DSI_RXPKT1H_DET_ERR BIT(30)
106 # define DSI_RXPKT1H_ECC_ERR BIT(29)
107 # define DSI_RXPKT1H_COR_ERR BIT(28)
108 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
109 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
110 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
111 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
112 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
113 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
114 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
115 # define DSI_RXPKT1H_SHORT_1_SHIFT 16
116 # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
117 # define DSI_RXPKT1H_SHORT_0_SHIFT 8
118 # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
119 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
121 #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
122 #define DSI1_RXPKT2H 0x18
123 # define DSI_RXPKT1H_DET_ERR BIT(30)
124 # define DSI_RXPKT1H_ECC_ERR BIT(29)
125 # define DSI_RXPKT1H_COR_ERR BIT(28)
126 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
127 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
128 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
129 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
130 # define DSI_RXPKT1H_DT_SHIFT 0
132 #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
133 #define DSI1_TXPKT_CMD_FIFO 0x1c
135 #define DSI0_DISP0_CTRL 0x18
136 # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
137 # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
138 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
139 # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
140 # define DSI_DISP0_LP_STOP_DISABLE 0
141 # define DSI_DISP0_LP_STOP_PERLINE 1
142 # define DSI_DISP0_LP_STOP_PERFRAME 2
144 /* Transmit RGB pixels and null packets only during HACTIVE, instead
145 * of going to LP-STOP.
147 # define DSI_DISP_HACTIVE_NULL BIT(10)
148 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
149 # define DSI_DISP_VBLP_CTRL BIT(9)
150 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
151 # define DSI_DISP_HFP_CTRL BIT(8)
152 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
153 # define DSI_DISP_HBP_CTRL BIT(7)
154 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
155 # define DSI_DISP0_CHANNEL_SHIFT 5
156 /* Enables end events for HSYNC/VSYNC, not just start events. */
157 # define DSI_DISP0_ST_END BIT(4)
158 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
159 # define DSI_DISP0_PFORMAT_SHIFT 2
160 # define DSI_PFORMAT_RGB565 0
161 # define DSI_PFORMAT_RGB666_PACKED 1
162 # define DSI_PFORMAT_RGB666 2
163 # define DSI_PFORMAT_RGB888 3
164 /* Default is VIDEO mode. */
165 # define DSI_DISP0_COMMAND_MODE BIT(1)
166 # define DSI_DISP0_ENABLE BIT(0)
168 #define DSI0_DISP1_CTRL 0x1c
169 #define DSI1_DISP1_CTRL 0x2c
170 /* Format of the data written to TXPKT_PIX_FIFO. */
171 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
172 # define DSI_DISP1_PFORMAT_SHIFT 1
173 # define DSI_DISP1_PFORMAT_16BIT 0
174 # define DSI_DISP1_PFORMAT_24BIT 1
175 # define DSI_DISP1_PFORMAT_32BIT_LE 2
176 # define DSI_DISP1_PFORMAT_32BIT_BE 3
178 /* DISP1 is always command mode. */
179 # define DSI_DISP1_ENABLE BIT(0)
181 #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
183 #define DSI0_INT_STAT 0x24
184 #define DSI0_INT_EN 0x28
185 # define DSI1_INT_PHY_D3_ULPS BIT(30)
186 # define DSI1_INT_PHY_D3_STOP BIT(29)
187 # define DSI1_INT_PHY_D2_ULPS BIT(28)
188 # define DSI1_INT_PHY_D2_STOP BIT(27)
189 # define DSI1_INT_PHY_D1_ULPS BIT(26)
190 # define DSI1_INT_PHY_D1_STOP BIT(25)
191 # define DSI1_INT_PHY_D0_ULPS BIT(24)
192 # define DSI1_INT_PHY_D0_STOP BIT(23)
193 # define DSI1_INT_FIFO_ERR BIT(22)
194 # define DSI1_INT_PHY_DIR_RTF BIT(21)
195 # define DSI1_INT_PHY_RXLPDT BIT(20)
196 # define DSI1_INT_PHY_RXTRIG BIT(19)
197 # define DSI1_INT_PHY_D0_LPDT BIT(18)
198 # define DSI1_INT_PHY_DIR_FTR BIT(17)
200 /* Signaled when the clock lane enters the given state. */
201 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
202 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
203 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
205 /* Signaled on timeouts */
206 # define DSI1_INT_PR_TO BIT(13)
207 # define DSI1_INT_TA_TO BIT(12)
208 # define DSI1_INT_LPRX_TO BIT(11)
209 # define DSI1_INT_HSTX_TO BIT(10)
211 /* Contention on a line when trying to drive the line low */
212 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
213 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
215 /* Control error: incorrect line state sequence on data lane 0. */
216 # define DSI1_INT_ERR_CONTROL BIT(7)
217 /* LPDT synchronization error (bits received not a multiple of 8. */
219 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
220 /* Signaled after receiving an error packet from the display in
221 * response to a read.
223 # define DSI1_INT_RXPKT2 BIT(5)
224 /* Signaled after receiving a packet. The header and optional short
225 * response will be in RXPKT1H, and a long response will be in the
228 # define DSI1_INT_RXPKT1 BIT(4)
229 # define DSI1_INT_TXPKT2_DONE BIT(3)
230 # define DSI1_INT_TXPKT2_END BIT(2)
231 /* Signaled after all repeats of TXPKT1 are transferred. */
232 # define DSI1_INT_TXPKT1_DONE BIT(1)
233 /* Signaled after each TXPKT1 repeat is scheduled. */
234 # define DSI1_INT_TXPKT1_END BIT(0)
236 #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
237 DSI1_INT_ERR_CONTROL | \
238 DSI1_INT_ERR_CONT_LP0 | \
239 DSI1_INT_ERR_CONT_LP1 | \
245 #define DSI0_STAT 0x2c
246 #define DSI0_HSTX_TO_CNT 0x30
247 #define DSI0_LPRX_TO_CNT 0x34
248 #define DSI0_TA_TO_CNT 0x38
249 #define DSI0_PR_TO_CNT 0x3c
250 #define DSI0_PHYC 0x40
251 # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
252 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
253 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
254 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
255 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
256 # define DSI1_PHYC_CLANE_ULPS BIT(17)
257 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
258 # define DSI_PHYC_DLANE3_ULPS BIT(13)
259 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
260 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
261 # define DSI0_PHYC_CLANE_ULPS BIT(9)
262 # define DSI_PHYC_DLANE2_ULPS BIT(9)
263 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
264 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
265 # define DSI_PHYC_DLANE1_ULPS BIT(5)
266 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
267 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
268 # define DSI_PHYC_DLANE0_ULPS BIT(1)
269 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
271 #define DSI0_HS_CLT0 0x44
272 #define DSI0_HS_CLT1 0x48
273 #define DSI0_HS_CLT2 0x4c
274 #define DSI0_HS_DLT3 0x50
275 #define DSI0_HS_DLT4 0x54
276 #define DSI0_HS_DLT5 0x58
277 #define DSI0_HS_DLT6 0x5c
278 #define DSI0_HS_DLT7 0x60
280 #define DSI0_PHY_AFEC0 0x64
281 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
282 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
283 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
284 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
285 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
286 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
287 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
288 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
289 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
290 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
291 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
292 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
293 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
294 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
295 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
296 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
297 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
298 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
299 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
300 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
301 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
302 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
303 # define DSI1_PHY_AFEC0_RESET BIT(13)
304 # define DSI1_PHY_AFEC0_PD BIT(12)
305 # define DSI0_PHY_AFEC0_RESET BIT(11)
306 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
307 # define DSI0_PHY_AFEC0_PD BIT(10)
308 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
309 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
310 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
311 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
312 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
313 # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
314 # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
315 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
316 # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
318 #define DSI0_PHY_AFEC1 0x68
319 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
320 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
321 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
322 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
323 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
324 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
326 #define DSI0_TST_SEL 0x6c
327 #define DSI0_TST_MON 0x70
329 # define DSI_ID_VALUE 0x00647369
331 #define DSI1_CTRL 0x00
332 # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
333 # define DSI_CTRL_HS_CLKC_SHIFT 14
334 # define DSI_CTRL_HS_CLKC_BYTE 0
335 # define DSI_CTRL_HS_CLKC_DDR2 1
336 # define DSI_CTRL_HS_CLKC_DDR 2
338 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
339 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
340 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
341 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
342 # define DSI_CTRL_CAL_BYTE BIT(9)
343 # define DSI_CTRL_INV_BYTE BIT(8)
344 # define DSI_CTRL_CLR_LDF BIT(7)
345 # define DSI0_CTRL_CLR_PBCF BIT(6)
346 # define DSI1_CTRL_CLR_RXF BIT(6)
347 # define DSI0_CTRL_CLR_CPBCF BIT(5)
348 # define DSI1_CTRL_CLR_PDF BIT(5)
349 # define DSI0_CTRL_CLR_PDF BIT(4)
350 # define DSI1_CTRL_CLR_CDF BIT(4)
351 # define DSI0_CTRL_CLR_CDF BIT(3)
352 # define DSI0_CTRL_CTRL2 BIT(2)
353 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
354 # define DSI0_CTRL_CTRL1 BIT(1)
355 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
356 # define DSI0_CTRL_CTRL0 BIT(0)
357 # define DSI1_CTRL_EN BIT(0)
358 # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
359 DSI0_CTRL_CLR_PBCF | \
360 DSI0_CTRL_CLR_CPBCF | \
361 DSI0_CTRL_CLR_PDF | \
363 # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
364 DSI1_CTRL_CLR_RXF | \
365 DSI1_CTRL_CLR_PDF | \
368 #define DSI1_TXPKT2C 0x0c
369 #define DSI1_TXPKT2H 0x10
370 #define DSI1_TXPKT_PIX_FIFO 0x20
371 #define DSI1_RXPKT_FIFO 0x24
372 #define DSI1_DISP0_CTRL 0x28
373 #define DSI1_INT_STAT 0x30
374 #define DSI1_INT_EN 0x34
375 /* State reporting bits. These mostly behave like INT_STAT, where
376 * writing a 1 clears the bit.
378 #define DSI1_STAT 0x38
379 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
380 # define DSI1_STAT_PHY_D3_STOP BIT(30)
381 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
382 # define DSI1_STAT_PHY_D2_STOP BIT(28)
383 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
384 # define DSI1_STAT_PHY_D1_STOP BIT(26)
385 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
386 # define DSI1_STAT_PHY_D0_STOP BIT(24)
387 # define DSI1_STAT_FIFO_ERR BIT(23)
388 # define DSI1_STAT_PHY_RXLPDT BIT(22)
389 # define DSI1_STAT_PHY_RXTRIG BIT(21)
390 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
391 /* Set when in forward direction */
392 # define DSI1_STAT_PHY_DIR BIT(19)
393 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
394 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
395 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
396 # define DSI1_STAT_PR_TO BIT(15)
397 # define DSI1_STAT_TA_TO BIT(14)
398 # define DSI1_STAT_LPRX_TO BIT(13)
399 # define DSI1_STAT_HSTX_TO BIT(12)
400 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
401 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
402 # define DSI1_STAT_ERR_CONTROL BIT(9)
403 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
404 # define DSI1_STAT_RXPKT2 BIT(7)
405 # define DSI1_STAT_RXPKT1 BIT(6)
406 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
407 # define DSI1_STAT_TXPKT2_DONE BIT(4)
408 # define DSI1_STAT_TXPKT2_END BIT(3)
409 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
410 # define DSI1_STAT_TXPKT1_DONE BIT(1)
411 # define DSI1_STAT_TXPKT1_END BIT(0)
413 #define DSI1_HSTX_TO_CNT 0x3c
414 #define DSI1_LPRX_TO_CNT 0x40
415 #define DSI1_TA_TO_CNT 0x44
416 #define DSI1_PR_TO_CNT 0x48
417 #define DSI1_PHYC 0x4c
419 #define DSI1_HS_CLT0 0x50
420 # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
421 # define DSI_HS_CLT0_CZERO_SHIFT 18
422 # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
423 # define DSI_HS_CLT0_CPRE_SHIFT 9
424 # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
425 # define DSI_HS_CLT0_CPREP_SHIFT 0
427 #define DSI1_HS_CLT1 0x54
428 # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
429 # define DSI_HS_CLT1_CTRAIL_SHIFT 9
430 # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
431 # define DSI_HS_CLT1_CPOST_SHIFT 0
433 #define DSI1_HS_CLT2 0x58
434 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
435 # define DSI_HS_CLT2_WUP_SHIFT 0
437 #define DSI1_HS_DLT3 0x5c
438 # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
439 # define DSI_HS_DLT3_EXIT_SHIFT 18
440 # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
441 # define DSI_HS_DLT3_ZERO_SHIFT 9
442 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
443 # define DSI_HS_DLT3_PRE_SHIFT 0
445 #define DSI1_HS_DLT4 0x60
446 # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
447 # define DSI_HS_DLT4_ANLAT_SHIFT 18
448 # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
449 # define DSI_HS_DLT4_TRAIL_SHIFT 9
450 # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
451 # define DSI_HS_DLT4_LPX_SHIFT 0
453 #define DSI1_HS_DLT5 0x64
454 # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
455 # define DSI_HS_DLT5_INIT_SHIFT 0
457 #define DSI1_HS_DLT6 0x68
458 # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
459 # define DSI_HS_DLT6_TA_GET_SHIFT 24
460 # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
461 # define DSI_HS_DLT6_TA_SURE_SHIFT 16
462 # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
463 # define DSI_HS_DLT6_TA_GO_SHIFT 8
464 # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
465 # define DSI_HS_DLT6_LP_LPX_SHIFT 0
467 #define DSI1_HS_DLT7 0x6c
468 # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
469 # define DSI_HS_DLT7_LP_WUP_SHIFT 0
471 #define DSI1_PHY_AFEC0 0x70
473 #define DSI1_PHY_AFEC1 0x74
474 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
475 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
476 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
477 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
478 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
479 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
480 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
481 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
482 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
483 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
485 #define DSI1_TST_SEL 0x78
486 #define DSI1_TST_MON 0x7c
487 #define DSI1_PHY_TST1 0x80
488 #define DSI1_PHY_TST2 0x84
489 #define DSI1_PHY_FIFO_STAT 0x88
490 /* Actually, all registers in the range that aren't otherwise claimed
491 * will return the ID.
495 /* General DSI hardware state. */
497 struct platform_device *pdev;
499 struct mipi_dsi_host dsi_host;
500 struct drm_encoder *encoder;
501 struct drm_bridge *bridge;
505 struct dma_chan *reg_dma_chan;
506 dma_addr_t reg_dma_paddr;
508 dma_addr_t reg_paddr;
510 /* Whether we're on bcm2835's DSI0 or DSI1. */
513 /* DSI channel for the panel we're connected to. */
520 /* Input clock from CPRMAN to the digital PHY, for the DSI
523 struct clk *escape_clock;
525 /* Input clock to the analog PHY, used to generate the DSI bit
528 struct clk *pll_phy_clock;
530 /* HS Clocks generated within the DSI analog PHY. */
531 struct clk_fixed_factor phy_clocks[3];
533 struct clk_hw_onecell_data *clk_onecell;
535 /* Pixel clock output to the pixelvalve, generated from the HS
538 struct clk *pixel_clock;
540 struct completion xfer_completion;
543 struct debugfs_regset32 regset;
546 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
549 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
551 struct dma_chan *chan = dsi->reg_dma_chan;
552 struct dma_async_tx_descriptor *tx;
556 /* DSI0 should be able to write normally. */
558 writel(val, dsi->regs + offset);
562 *dsi->reg_dma_mem = val;
564 tx = chan->device->device_prep_dma_memcpy(chan,
565 dsi->reg_paddr + offset,
569 DRM_ERROR("Failed to set up DMA register write\n");
573 cookie = tx->tx_submit(tx);
574 ret = dma_submit_error(cookie);
576 DRM_ERROR("Failed to submit DMA: %d\n", ret);
579 ret = dma_sync_wait(chan, cookie);
581 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
584 #define DSI_READ(offset) readl(dsi->regs + (offset))
585 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
586 #define DSI_PORT_READ(offset) \
587 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
588 #define DSI_PORT_WRITE(offset, val) \
589 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
590 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
592 /* VC4 DSI encoder KMS struct */
593 struct vc4_dsi_encoder {
594 struct vc4_encoder base;
598 static inline struct vc4_dsi_encoder *
599 to_vc4_dsi_encoder(struct drm_encoder *encoder)
601 return container_of(encoder, struct vc4_dsi_encoder, base.base);
604 static const struct debugfs_reg32 dsi0_regs[] = {
605 VC4_REG32(DSI0_CTRL),
606 VC4_REG32(DSI0_STAT),
607 VC4_REG32(DSI0_HSTX_TO_CNT),
608 VC4_REG32(DSI0_LPRX_TO_CNT),
609 VC4_REG32(DSI0_TA_TO_CNT),
610 VC4_REG32(DSI0_PR_TO_CNT),
611 VC4_REG32(DSI0_DISP0_CTRL),
612 VC4_REG32(DSI0_DISP1_CTRL),
613 VC4_REG32(DSI0_INT_STAT),
614 VC4_REG32(DSI0_INT_EN),
615 VC4_REG32(DSI0_PHYC),
616 VC4_REG32(DSI0_HS_CLT0),
617 VC4_REG32(DSI0_HS_CLT1),
618 VC4_REG32(DSI0_HS_CLT2),
619 VC4_REG32(DSI0_HS_DLT3),
620 VC4_REG32(DSI0_HS_DLT4),
621 VC4_REG32(DSI0_HS_DLT5),
622 VC4_REG32(DSI0_HS_DLT6),
623 VC4_REG32(DSI0_HS_DLT7),
624 VC4_REG32(DSI0_PHY_AFEC0),
625 VC4_REG32(DSI0_PHY_AFEC1),
629 static const struct debugfs_reg32 dsi1_regs[] = {
630 VC4_REG32(DSI1_CTRL),
631 VC4_REG32(DSI1_STAT),
632 VC4_REG32(DSI1_HSTX_TO_CNT),
633 VC4_REG32(DSI1_LPRX_TO_CNT),
634 VC4_REG32(DSI1_TA_TO_CNT),
635 VC4_REG32(DSI1_PR_TO_CNT),
636 VC4_REG32(DSI1_DISP0_CTRL),
637 VC4_REG32(DSI1_DISP1_CTRL),
638 VC4_REG32(DSI1_INT_STAT),
639 VC4_REG32(DSI1_INT_EN),
640 VC4_REG32(DSI1_PHYC),
641 VC4_REG32(DSI1_HS_CLT0),
642 VC4_REG32(DSI1_HS_CLT1),
643 VC4_REG32(DSI1_HS_CLT2),
644 VC4_REG32(DSI1_HS_DLT3),
645 VC4_REG32(DSI1_HS_DLT4),
646 VC4_REG32(DSI1_HS_DLT5),
647 VC4_REG32(DSI1_HS_DLT6),
648 VC4_REG32(DSI1_HS_DLT7),
649 VC4_REG32(DSI1_PHY_AFEC0),
650 VC4_REG32(DSI1_PHY_AFEC1),
654 static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder)
656 drm_encoder_cleanup(encoder);
659 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
660 .destroy = vc4_dsi_encoder_destroy,
663 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
665 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
668 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
670 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
672 DSI_PORT_WRITE(PHY_AFEC0, afec0);
675 /* Enters or exits Ultra Low Power State. */
676 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
678 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
679 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
680 DSI_PHYC_DLANE0_ULPS |
681 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
682 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
683 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
684 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
685 DSI1_STAT_PHY_D0_ULPS |
686 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
687 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
688 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
689 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
690 DSI1_STAT_PHY_D0_STOP |
691 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
692 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
693 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
695 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
696 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
698 if (ulps == ulps_currently_enabled)
701 DSI_PORT_WRITE(STAT, stat_ulps);
702 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
703 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
705 dev_warn(&dsi->pdev->dev,
706 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
707 DSI_PORT_READ(STAT));
708 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
709 vc4_dsi_latch_ulps(dsi, false);
713 /* The DSI module can't be disabled while the module is
714 * generating ULPS state. So, to be able to disable the
715 * module, we have the AFE latch the ULPS state and continue
716 * on to having the module enter STOP.
718 vc4_dsi_latch_ulps(dsi, ulps);
720 DSI_PORT_WRITE(STAT, stat_stop);
721 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
722 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
724 dev_warn(&dsi->pdev->dev,
725 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
726 DSI_PORT_READ(STAT));
727 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
733 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
735 /* The HS timings have to be rounded up to a multiple of 8
736 * because we're using the byte clock.
738 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
741 /* ESC always runs at 100Mhz. */
742 #define ESC_TIME_NS 10
745 dsi_esc_timing(u32 ns)
747 return DIV_ROUND_UP(ns, ESC_TIME_NS);
750 static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
752 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
753 struct vc4_dsi *dsi = vc4_encoder->dsi;
754 struct device *dev = &dsi->pdev->dev;
756 drm_bridge_disable(dsi->bridge);
757 vc4_dsi_ulps(dsi, true);
758 drm_bridge_post_disable(dsi->bridge);
760 clk_disable_unprepare(dsi->pll_phy_clock);
761 clk_disable_unprepare(dsi->escape_clock);
762 clk_disable_unprepare(dsi->pixel_clock);
767 /* Extends the mode's blank intervals to handle BCM2835's integer-only
770 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
771 * driver since most peripherals are hanging off of the PLLD_PER
772 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
773 * the pixel clock), only has an integer divider off of DSI.
775 * To get our panel mode to refresh at the expected 60Hz, we need to
776 * extend the horizontal blank time. This means we drive a
777 * higher-than-expected clock rate to the panel, but that's what the
780 static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
781 const struct drm_display_mode *mode,
782 struct drm_display_mode *adjusted_mode)
784 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
785 struct vc4_dsi *dsi = vc4_encoder->dsi;
786 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
787 unsigned long parent_rate = clk_get_rate(phy_parent);
788 unsigned long pixel_clock_hz = mode->clock * 1000;
789 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
792 /* Find what divider gets us a faster clock than the requested
795 for (divider = 1; divider < 8; divider++) {
796 if (parent_rate / divider < pll_clock) {
802 /* Now that we've picked a PLL divider, calculate back to its
805 pll_clock = parent_rate / divider;
806 pixel_clock_hz = pll_clock / dsi->divider;
808 adjusted_mode->clock = pixel_clock_hz / 1000;
810 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
811 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
813 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
814 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
819 static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
821 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
822 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
823 struct vc4_dsi *dsi = vc4_encoder->dsi;
824 struct device *dev = &dsi->pdev->dev;
825 bool debug_dump_regs = false;
826 unsigned long hs_clock;
828 /* Minimum LP state duration in escape clock cycles. */
829 u32 lpx = dsi_esc_timing(60);
830 unsigned long pixel_clock_hz = mode->clock * 1000;
831 unsigned long dsip_clock;
832 unsigned long phy_clock;
835 ret = pm_runtime_get_sync(dev);
837 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port);
841 if (debug_dump_regs) {
842 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
843 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
844 drm_print_regset32(&p, &dsi->regset);
847 /* Round up the clk_set_rate() request slightly, since
848 * PLLD_DSI1 is an integer divider and its rate selection will
851 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
852 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
854 dev_err(&dsi->pdev->dev,
855 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
858 /* Reset the DSI and all its fifos. */
860 DSI_CTRL_SOFT_RESET_CFG |
861 DSI_PORT_BIT(CTRL_RESET_FIFOS));
864 DSI_CTRL_HSDT_EOT_DISABLE |
865 DSI_CTRL_RX_LPDT_EOT_DISABLE);
867 /* Clear all stat bits so we see what has happened during enable. */
868 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
870 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
871 if (dsi->port == 0) {
872 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
873 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
876 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
878 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
879 afec0 |= DSI0_PHY_AFEC0_RESET;
881 DSI_PORT_WRITE(PHY_AFEC0, afec0);
883 DSI_PORT_WRITE(PHY_AFEC1,
884 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
885 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
886 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
888 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
889 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
890 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
891 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
892 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
893 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
894 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
897 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
899 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
901 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
903 afec0 |= DSI1_PHY_AFEC0_RESET;
905 DSI_PORT_WRITE(PHY_AFEC0, afec0);
907 DSI_PORT_WRITE(PHY_AFEC1, 0);
909 /* AFEC reset hold time */
913 ret = clk_prepare_enable(dsi->escape_clock);
915 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
919 ret = clk_prepare_enable(dsi->pll_phy_clock);
921 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
925 hs_clock = clk_get_rate(dsi->pll_phy_clock);
927 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
928 * not the pixel clock rate. DSIxP take from the APHY's byte,
929 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
930 * that rate. Separately, a value derived from PIX_CLK_DIV
931 * and HS_CLKC is fed into the PV to divide down to the actual
932 * pixel clock for pushing pixels into DSI.
934 dsip_clock = phy_clock / 8;
935 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
937 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
941 ret = clk_prepare_enable(dsi->pixel_clock);
943 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
947 /* How many ns one DSI unit interval is. Note that the clock
948 * is DDR, so there's an extra divide by 2.
950 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
952 DSI_PORT_WRITE(HS_CLT0,
953 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
955 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
957 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
960 DSI_PORT_WRITE(HS_CLT1,
961 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
962 DSI_HS_CLT1_CTRAIL) |
963 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
966 DSI_PORT_WRITE(HS_CLT2,
967 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
970 DSI_PORT_WRITE(HS_DLT3,
971 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
973 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
975 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
978 DSI_PORT_WRITE(HS_DLT4,
979 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
981 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
982 dsi_hs_timing(ui_ns, 60, 4)),
984 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
986 /* T_INIT is how long STOP is driven after power-up to
987 * indicate to the slave (also coming out of power-up) that
988 * master init is complete, and should be greater than the
989 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
990 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
991 * T_INIT,SLAVE, while allowing protocols on top of it to give
992 * greater minimums. The vc4 firmware uses an extremely
993 * conservative 5ms, and we maintain that here.
995 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
999 DSI_PORT_WRITE(HS_DLT6,
1000 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1001 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1002 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1003 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1005 DSI_PORT_WRITE(HS_DLT7,
1006 VC4_SET_FIELD(dsi_esc_timing(1000000),
1007 DSI_HS_DLT7_LP_WUP));
1009 DSI_PORT_WRITE(PHYC,
1010 DSI_PHYC_DLANE0_ENABLE |
1011 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1012 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1013 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1014 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1015 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1016 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1018 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1019 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1021 DSI_PORT_WRITE(CTRL,
1022 DSI_PORT_READ(CTRL) |
1025 /* HS timeout in HS clock cycles: disabled. */
1026 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1027 /* LP receive timeout in HS clocks. */
1028 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1029 /* Bus turnaround timeout */
1030 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1031 /* Display reset sequence timeout */
1032 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1034 /* Set up DISP1 for transferring long command payloads through
1037 DSI_PORT_WRITE(DISP1_CTRL,
1038 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1039 DSI_DISP1_PFORMAT) |
1042 /* Ungate the block. */
1044 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1046 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1048 /* Bring AFE out of reset. */
1049 if (dsi->port == 0) {
1051 DSI_PORT_WRITE(PHY_AFEC0,
1052 DSI_PORT_READ(PHY_AFEC0) &
1053 ~DSI1_PHY_AFEC0_RESET);
1056 vc4_dsi_ulps(dsi, false);
1058 drm_bridge_pre_enable(dsi->bridge);
1060 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1061 DSI_PORT_WRITE(DISP0_CTRL,
1062 VC4_SET_FIELD(dsi->divider,
1063 DSI_DISP0_PIX_CLK_DIV) |
1064 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1065 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1066 DSI_DISP0_LP_STOP_CTRL) |
1070 DSI_PORT_WRITE(DISP0_CTRL,
1071 DSI_DISP0_COMMAND_MODE |
1075 drm_bridge_enable(dsi->bridge);
1077 if (debug_dump_regs) {
1078 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1079 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1080 drm_print_regset32(&p, &dsi->regset);
1084 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1085 const struct mipi_dsi_msg *msg)
1087 struct vc4_dsi *dsi = host_to_dsi(host);
1088 struct mipi_dsi_packet packet;
1089 u32 pkth = 0, pktc = 0;
1091 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1092 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1094 mipi_dsi_create_packet(&packet, msg);
1096 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1097 pkth |= VC4_SET_FIELD(packet.header[1] |
1098 (packet.header[2] << 8),
1099 DSI_TXPKT1H_BC_PARAM);
1101 /* Divide data across the various FIFOs we have available.
1102 * The command FIFO takes byte-oriented data, but is of
1103 * limited size. The pixel FIFO (never actually used for
1104 * pixel data in reality) is word oriented, and substantially
1105 * larger. So, we use the pixel FIFO for most of the data,
1106 * sending the residual bytes in the command FIFO at the start.
1108 * With this arrangement, the command FIFO will never get full.
1110 if (packet.payload_length <= 16) {
1111 cmd_fifo_len = packet.payload_length;
1114 cmd_fifo_len = (packet.payload_length %
1115 DSI_PIX_FIFO_WIDTH);
1116 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1117 DSI_PIX_FIFO_WIDTH);
1120 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1122 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1126 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1127 DSI_TXPKT1C_CMD_CTRL);
1129 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1130 DSI_TXPKT1C_CMD_CTRL);
1133 for (i = 0; i < cmd_fifo_len; i++)
1134 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1135 for (i = 0; i < pix_fifo_len; i++) {
1136 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1138 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1145 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1146 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1148 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1150 /* Send one copy of the packet. Larger repeats are used for pixel
1151 * data in command mode.
1153 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1155 pktc |= DSI_TXPKT1C_CMD_EN;
1157 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1158 DSI_TXPKT1C_DISPLAY_NO);
1160 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1161 DSI_TXPKT1C_DISPLAY_NO);
1164 /* Enable the appropriate interrupt for the transfer completion. */
1165 dsi->xfer_result = 0;
1166 reinit_completion(&dsi->xfer_completion);
1167 DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1169 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1170 DSI1_INT_PHY_DIR_RTF));
1172 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1173 DSI1_INT_TXPKT1_DONE));
1176 /* Send the packet. */
1177 DSI_PORT_WRITE(TXPKT1H, pkth);
1178 DSI_PORT_WRITE(TXPKT1C, pktc);
1180 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1181 msecs_to_jiffies(1000))) {
1182 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1183 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1184 DSI_PORT_READ(INT_STAT));
1187 ret = dsi->xfer_result;
1190 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1193 goto reset_fifo_and_return;
1195 if (ret == 0 && msg->rx_len) {
1196 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1197 u8 *msg_rx = msg->rx_buf;
1199 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1200 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1201 DSI_RXPKT1H_BC_PARAM);
1203 if (rxlen != msg->rx_len) {
1204 DRM_ERROR("DSI returned %db, expecting %db\n",
1205 rxlen, (int)msg->rx_len);
1207 goto reset_fifo_and_return;
1210 for (i = 0; i < msg->rx_len; i++)
1211 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1213 /* FINISHME: Handle AWER */
1215 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1216 DSI_RXPKT1H_SHORT_0);
1217 if (msg->rx_len > 1) {
1218 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1219 DSI_RXPKT1H_SHORT_1);
1226 reset_fifo_and_return:
1227 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1229 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1231 DSI_PORT_WRITE(CTRL,
1232 DSI_PORT_READ(CTRL) |
1233 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1235 DSI_PORT_WRITE(TXPKT1C, 0);
1236 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1240 static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1241 struct mipi_dsi_device *device)
1243 struct vc4_dsi *dsi = host_to_dsi(host);
1245 dsi->lanes = device->lanes;
1246 dsi->channel = device->channel;
1247 dsi->mode_flags = device->mode_flags;
1249 switch (device->format) {
1250 case MIPI_DSI_FMT_RGB888:
1251 dsi->format = DSI_PFORMAT_RGB888;
1252 dsi->divider = 24 / dsi->lanes;
1254 case MIPI_DSI_FMT_RGB666:
1255 dsi->format = DSI_PFORMAT_RGB666;
1256 dsi->divider = 24 / dsi->lanes;
1258 case MIPI_DSI_FMT_RGB666_PACKED:
1259 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1260 dsi->divider = 18 / dsi->lanes;
1262 case MIPI_DSI_FMT_RGB565:
1263 dsi->format = DSI_PFORMAT_RGB565;
1264 dsi->divider = 16 / dsi->lanes;
1267 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1272 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1273 dev_err(&dsi->pdev->dev,
1274 "Only VIDEO mode panels supported currently.\n");
1281 static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1282 struct mipi_dsi_device *device)
1287 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1288 .attach = vc4_dsi_host_attach,
1289 .detach = vc4_dsi_host_detach,
1290 .transfer = vc4_dsi_host_transfer,
1293 static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1294 .disable = vc4_dsi_encoder_disable,
1295 .enable = vc4_dsi_encoder_enable,
1296 .mode_fixup = vc4_dsi_encoder_mode_fixup,
1299 static const struct of_device_id vc4_dsi_dt_match[] = {
1300 { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1304 static void dsi_handle_error(struct vc4_dsi *dsi,
1305 irqreturn_t *ret, u32 stat, u32 bit,
1311 DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1316 * Initial handler for port 1 where we need the reg_dma workaround.
1317 * The register DMA writes sleep, so we can't do it in the top half.
1318 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1319 * parent interrupt contrller until our interrupt thread is done.
1321 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1323 struct vc4_dsi *dsi = data;
1324 u32 stat = DSI_PORT_READ(INT_STAT);
1329 return IRQ_WAKE_THREAD;
1333 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1334 * 1 where we need the reg_dma workaround.
1336 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1338 struct vc4_dsi *dsi = data;
1339 u32 stat = DSI_PORT_READ(INT_STAT);
1340 irqreturn_t ret = IRQ_NONE;
1342 DSI_PORT_WRITE(INT_STAT, stat);
1344 dsi_handle_error(dsi, &ret, stat,
1345 DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1346 dsi_handle_error(dsi, &ret, stat,
1347 DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1348 dsi_handle_error(dsi, &ret, stat,
1349 DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1350 dsi_handle_error(dsi, &ret, stat,
1351 DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1352 dsi_handle_error(dsi, &ret, stat,
1353 DSI1_INT_HSTX_TO, "HSTX timeout");
1354 dsi_handle_error(dsi, &ret, stat,
1355 DSI1_INT_LPRX_TO, "LPRX timeout");
1356 dsi_handle_error(dsi, &ret, stat,
1357 DSI1_INT_TA_TO, "turnaround timeout");
1358 dsi_handle_error(dsi, &ret, stat,
1359 DSI1_INT_PR_TO, "peripheral reset timeout");
1361 if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1362 complete(&dsi->xfer_completion);
1364 } else if (stat & DSI1_INT_HSTX_TO) {
1365 complete(&dsi->xfer_completion);
1366 dsi->xfer_result = -ETIMEDOUT;
1374 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1375 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1379 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1381 struct device *dev = &dsi->pdev->dev;
1382 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1383 static const struct {
1384 const char *dsi0_name, *dsi1_name;
1387 { "dsi0_byte", "dsi1_byte", 8 },
1388 { "dsi0_ddr2", "dsi1_ddr2", 4 },
1389 { "dsi0_ddr", "dsi1_ddr", 2 },
1393 dsi->clk_onecell = devm_kzalloc(dev,
1394 sizeof(*dsi->clk_onecell) +
1395 ARRAY_SIZE(phy_clocks) *
1396 sizeof(struct clk_hw *),
1398 if (!dsi->clk_onecell)
1400 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1402 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1403 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1404 struct clk_init_data init;
1407 /* We just use core fixed factor clock ops for the PHY
1408 * clocks. The clocks are actually gated by the
1409 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1410 * setting if we use the DDR/DDR2 clocks. However,
1411 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1412 * setting both our parent DSI PLL's rate and this
1413 * clock's rate, so it knows if DDR/DDR2 are going to
1414 * be used and could enable the gates itself.
1417 fix->div = phy_clocks[i].div;
1418 fix->hw.init = &init;
1420 memset(&init, 0, sizeof(init));
1421 init.parent_names = &parent_name;
1422 init.num_parents = 1;
1424 init.name = phy_clocks[i].dsi1_name;
1426 init.name = phy_clocks[i].dsi0_name;
1427 init.ops = &clk_fixed_factor_ops;
1429 ret = devm_clk_hw_register(dev, &fix->hw);
1433 dsi->clk_onecell->hws[i] = &fix->hw;
1436 return of_clk_add_hw_provider(dev->of_node,
1437 of_clk_hw_onecell_get,
1441 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1443 struct platform_device *pdev = to_platform_device(dev);
1444 struct drm_device *drm = dev_get_drvdata(master);
1445 struct vc4_dev *vc4 = to_vc4_dev(drm);
1446 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1447 struct vc4_dsi_encoder *vc4_dsi_encoder;
1448 struct drm_panel *panel;
1449 const struct of_device_id *match;
1450 dma_cap_mask_t dma_mask;
1453 match = of_match_device(vc4_dsi_dt_match, dev);
1457 dsi->port = (uintptr_t)match->data;
1459 vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1461 if (!vc4_dsi_encoder)
1463 vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1464 vc4_dsi_encoder->dsi = dsi;
1465 dsi->encoder = &vc4_dsi_encoder->base.base;
1467 dsi->regs = vc4_ioremap_regs(pdev, 0);
1468 if (IS_ERR(dsi->regs))
1469 return PTR_ERR(dsi->regs);
1471 dsi->regset.base = dsi->regs;
1472 if (dsi->port == 0) {
1473 dsi->regset.regs = dsi0_regs;
1474 dsi->regset.nregs = ARRAY_SIZE(dsi0_regs);
1476 dsi->regset.regs = dsi1_regs;
1477 dsi->regset.nregs = ARRAY_SIZE(dsi1_regs);
1480 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1481 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1482 DSI_PORT_READ(ID), DSI_ID_VALUE);
1486 /* DSI1 has a broken AXI slave that doesn't respond to writes
1487 * from the ARM. It does handle writes from the DMA engine,
1488 * so set up a channel for talking to it.
1490 if (dsi->port == 1) {
1491 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1492 &dsi->reg_dma_paddr,
1494 if (!dsi->reg_dma_mem) {
1495 DRM_ERROR("Failed to get DMA memory\n");
1499 dma_cap_zero(dma_mask);
1500 dma_cap_set(DMA_MEMCPY, dma_mask);
1501 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1502 if (IS_ERR(dsi->reg_dma_chan)) {
1503 ret = PTR_ERR(dsi->reg_dma_chan);
1504 if (ret != -EPROBE_DEFER)
1505 DRM_ERROR("Failed to get DMA channel: %d\n",
1510 /* Get the physical address of the device's registers. The
1511 * struct resource for the regs gives us the bus address
1514 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1518 init_completion(&dsi->xfer_completion);
1519 /* At startup enable error-reporting interrupts and nothing else. */
1520 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1521 /* Clear any existing interrupt state. */
1522 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1524 if (dsi->reg_dma_mem)
1525 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1526 vc4_dsi_irq_defer_to_thread_handler,
1527 vc4_dsi_irq_handler,
1531 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1532 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1534 if (ret != -EPROBE_DEFER)
1535 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1539 dsi->escape_clock = devm_clk_get(dev, "escape");
1540 if (IS_ERR(dsi->escape_clock)) {
1541 ret = PTR_ERR(dsi->escape_clock);
1542 if (ret != -EPROBE_DEFER)
1543 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1547 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1548 if (IS_ERR(dsi->pll_phy_clock)) {
1549 ret = PTR_ERR(dsi->pll_phy_clock);
1550 if (ret != -EPROBE_DEFER)
1551 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1555 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1556 if (IS_ERR(dsi->pixel_clock)) {
1557 ret = PTR_ERR(dsi->pixel_clock);
1558 if (ret != -EPROBE_DEFER)
1559 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1563 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1564 &panel, &dsi->bridge);
1566 /* If the bridge or panel pointed by dev->of_node is not
1567 * enabled, just return 0 here so that we don't prevent the DRM
1568 * dev from being registered. Of course that means the DSI
1569 * encoder won't be exposed, but that's not a problem since
1570 * nothing is connected to it.
1579 dsi->bridge = devm_drm_panel_bridge_add(dev, panel,
1580 DRM_MODE_CONNECTOR_DSI);
1581 if (IS_ERR(dsi->bridge))
1582 return PTR_ERR(dsi->bridge);
1585 /* The esc clock rate is supposed to always be 100Mhz. */
1586 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1588 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1592 ret = vc4_dsi_init_phy_clocks(dsi);
1599 drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs,
1600 DRM_MODE_ENCODER_DSI, NULL);
1601 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1603 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL);
1605 dev_err(dev, "bridge attach failed: %d\n", ret);
1608 /* Disable the atomic helper calls into the bridge. We
1609 * manually call the bridge pre_enable / enable / etc. calls
1610 * from our driver, since we need to sequence them within the
1611 * encoder's enable/disable paths.
1613 dsi->encoder->bridge = NULL;
1616 vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset);
1618 vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset);
1620 pm_runtime_enable(dev);
1625 static void vc4_dsi_unbind(struct device *dev, struct device *master,
1628 struct drm_device *drm = dev_get_drvdata(master);
1629 struct vc4_dev *vc4 = to_vc4_dev(drm);
1630 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1633 pm_runtime_disable(dev);
1635 vc4_dsi_encoder_destroy(dsi->encoder);
1641 static const struct component_ops vc4_dsi_ops = {
1642 .bind = vc4_dsi_bind,
1643 .unbind = vc4_dsi_unbind,
1646 static int vc4_dsi_dev_probe(struct platform_device *pdev)
1648 struct device *dev = &pdev->dev;
1649 struct vc4_dsi *dsi;
1652 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1655 dev_set_drvdata(dev, dsi);
1659 /* Note, the initialization sequence for DSI and panels is
1660 * tricky. The component bind above won't get past its
1661 * -EPROBE_DEFER until the panel/bridge probes. The
1662 * panel/bridge will return -EPROBE_DEFER until it has a
1663 * mipi_dsi_host to register its device to. So, we register
1664 * the host during pdev probe time, so vc4 as a whole can then
1665 * -EPROBE_DEFER its component bind process until the panel
1666 * successfully attaches.
1668 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1669 dsi->dsi_host.dev = dev;
1670 mipi_dsi_host_register(&dsi->dsi_host);
1672 ret = component_add(&pdev->dev, &vc4_dsi_ops);
1674 mipi_dsi_host_unregister(&dsi->dsi_host);
1681 static int vc4_dsi_dev_remove(struct platform_device *pdev)
1683 struct device *dev = &pdev->dev;
1684 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1686 component_del(&pdev->dev, &vc4_dsi_ops);
1687 mipi_dsi_host_unregister(&dsi->dsi_host);
1692 struct platform_driver vc4_dsi_driver = {
1693 .probe = vc4_dsi_dev_probe,
1694 .remove = vc4_dsi_dev_remove,
1697 .of_match_table = vc4_dsi_dt_match,