1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2018 Broadcom */
5 * DOC: Broadcom V3D scheduling
7 * The shared DRM GPU scheduler is used to coordinate submitting jobs
8 * to the hardware. Each DRM fd (roughly a client process) gets its
9 * own scheduler entity, which will process jobs in order. The GPU
10 * scheduler will round-robin between clients to submit the next job.
12 * For simplicity, and in order to keep latency low for interactive
13 * jobs when bulk background jobs are queued up, we submit a new job
14 * to the HW only when it has completed the last one, instead of
15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
16 * v3d_job_dependency() to manage the dependency between bin and
17 * render, instead of having the clients submit jobs with using the
18 * HW's semaphores to interlock between them.
21 #include <linux/kthread.h>
25 #include "v3d_trace.h"
27 static struct v3d_job *
28 to_v3d_job(struct drm_sched_job *sched_job)
30 return container_of(sched_job, struct v3d_job, base);
34 v3d_job_free(struct drm_sched_job *sched_job)
36 struct v3d_job *job = to_v3d_job(sched_job);
38 v3d_exec_put(job->exec);
42 * Returns the fences that the bin job depends on, one by one.
43 * v3d_job_run() won't be called until all of them have been signaled.
45 static struct dma_fence *
46 v3d_job_dependency(struct drm_sched_job *sched_job,
47 struct drm_sched_entity *s_entity)
49 struct v3d_job *job = to_v3d_job(sched_job);
50 struct v3d_exec_info *exec = job->exec;
51 enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
52 struct dma_fence *fence;
54 fence = job->in_fence;
60 if (q == V3D_RENDER) {
61 /* If we had a bin job, the render job definitely depends on
62 * it. We first have to wait for bin to be scheduled, so that
63 * its done_fence is created.
65 fence = exec->bin_done_fence;
67 exec->bin_done_fence = NULL;
72 /* XXX: Wait on a fence for switching the GMP if necessary,
79 static struct dma_fence *v3d_job_run(struct drm_sched_job *sched_job)
81 struct v3d_job *job = to_v3d_job(sched_job);
82 struct v3d_exec_info *exec = job->exec;
83 enum v3d_queue q = job == &exec->bin ? V3D_BIN : V3D_RENDER;
84 struct v3d_dev *v3d = exec->v3d;
85 struct drm_device *dev = &v3d->drm;
86 struct dma_fence *fence;
87 unsigned long irqflags;
89 if (unlikely(job->base.s_fence->finished.error))
92 /* Lock required around bin_job update vs
93 * v3d_overflow_mem_work().
95 spin_lock_irqsave(&v3d->job_lock, irqflags);
97 v3d->bin_job = job->exec;
99 /* Clear out the overflow allocation, so we don't
100 * reuse the overflow attached to a previous job.
102 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
104 v3d->render_job = job->exec;
106 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
108 /* Can we avoid this flush when q==RENDER? We need to be
109 * careful of scheduling, though -- imagine job0 rendering to
110 * texture and job1 reading, and them being executed as bin0,
111 * bin1, render0, render1, so that render1's flush at bin time
114 v3d_invalidate_caches(v3d);
116 fence = v3d_fence_create(v3d, q);
121 dma_fence_put(job->done_fence);
122 job->done_fence = dma_fence_get(fence);
124 trace_v3d_submit_cl(dev, q == V3D_RENDER, to_v3d_fence(fence)->seqno,
125 job->start, job->end);
129 V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, exec->qma);
130 V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, exec->qms);
133 V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
134 V3D_CLE_CT0QTS_ENABLE |
138 /* XXX: Set the QCFG */
141 /* Set the current and end address of the control list.
142 * Writing the end register is what starts the job.
144 V3D_CORE_WRITE(0, V3D_CLE_CTNQBA(q), job->start);
145 V3D_CORE_WRITE(0, V3D_CLE_CTNQEA(q), job->end);
151 v3d_job_timedout(struct drm_sched_job *sched_job)
153 struct v3d_job *job = to_v3d_job(sched_job);
154 struct v3d_exec_info *exec = job->exec;
155 struct v3d_dev *v3d = exec->v3d;
158 mutex_lock(&v3d->reset_lock);
160 /* block scheduler */
161 for (q = 0; q < V3D_MAX_QUEUES; q++) {
162 struct drm_gpu_scheduler *sched = &v3d->queue[q].sched;
164 kthread_park(sched->thread);
165 drm_sched_hw_job_reset(sched, (sched_job->sched == sched ?
169 /* get the GPU back into the init state */
172 /* Unblock schedulers and restart their jobs. */
173 for (q = 0; q < V3D_MAX_QUEUES; q++) {
174 drm_sched_job_recovery(&v3d->queue[q].sched);
175 kthread_unpark(v3d->queue[q].sched.thread);
178 mutex_unlock(&v3d->reset_lock);
181 static const struct drm_sched_backend_ops v3d_sched_ops = {
182 .dependency = v3d_job_dependency,
183 .run_job = v3d_job_run,
184 .timedout_job = v3d_job_timedout,
185 .free_job = v3d_job_free
189 v3d_sched_init(struct v3d_dev *v3d)
191 int hw_jobs_limit = 1;
192 int job_hang_limit = 0;
193 int hang_limit_ms = 500;
196 ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
198 hw_jobs_limit, job_hang_limit,
199 msecs_to_jiffies(hang_limit_ms),
202 dev_err(v3d->dev, "Failed to create bin scheduler: %d.", ret);
206 ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
208 hw_jobs_limit, job_hang_limit,
209 msecs_to_jiffies(hang_limit_ms),
212 dev_err(v3d->dev, "Failed to create render scheduler: %d.",
214 drm_sched_fini(&v3d->queue[V3D_BIN].sched);
222 v3d_sched_fini(struct v3d_dev *v3d)
226 for (q = 0; q < V3D_MAX_QUEUES; q++)
227 drm_sched_fini(&v3d->queue[q].sched);