1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
4 #include <linux/device.h>
5 #include <linux/dma-mapping.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/reset.h>
11 #include <linux/sched/signal.h>
12 #include <linux/uaccess.h>
14 #include <drm/drm_syncobj.h>
15 #include <uapi/drm/v3d_drm.h>
19 #include "v3d_trace.h"
22 v3d_init_core(struct v3d_dev *v3d, int core)
24 /* Set OVRTMUOUT, which means that the texture sampler uniform
25 * configuration's tmu output type field is used, instead of
26 * using the hardware default behavior based on the texture
27 * type. If you want the default behavior, you can still put
28 * "2" in the indirect texture state's output_type field.
31 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
33 /* Whenever we flush the L2T cache, we always want to flush
36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
37 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
40 /* Sets invariant state for the HW. */
42 v3d_init_hw_state(struct v3d_dev *v3d)
44 v3d_init_core(v3d, 0);
48 v3d_idle_axi(struct v3d_dev *v3d, int core)
50 V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
52 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
53 (V3D_GMP_STATUS_RD_COUNT_MASK |
54 V3D_GMP_STATUS_WR_COUNT_MASK |
55 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
56 DRM_ERROR("Failed to wait for safe GMP shutdown\n");
61 v3d_idle_gca(struct v3d_dev *v3d)
66 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
68 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
69 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
70 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
71 DRM_ERROR("Failed to wait for safe GCA shutdown\n");
76 v3d_reset_by_bridge(struct v3d_dev *v3d)
78 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
80 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
81 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
82 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
83 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
85 /* GFXH-1383: The SW_INIT may cause a stray write to address 0
86 * of the unit, so reset it to its power-on value here.
88 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
90 WARN_ON_ONCE(V3D_GET_FIELD(version,
91 V3D_TOP_GR_BRIDGE_MAJOR) != 7);
92 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
93 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
94 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
99 v3d_reset_v3d(struct v3d_dev *v3d)
102 reset_control_reset(v3d->reset);
104 v3d_reset_by_bridge(v3d);
106 v3d_init_hw_state(v3d);
110 v3d_reset(struct v3d_dev *v3d)
112 struct drm_device *dev = &v3d->drm;
114 DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n");
115 DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n",
116 V3D_CORE_READ(0, V3D_ERR_STAT));
117 trace_v3d_reset_begin(dev);
119 /* XXX: only needed for safe powerdown, not reset. */
121 v3d_idle_axi(v3d, 0);
126 v3d_mmu_set_page_table(v3d);
129 v3d_perfmon_stop(v3d, v3d->active_perfmon, false);
131 trace_v3d_reset_end(dev);
135 v3d_flush_l3(struct v3d_dev *v3d)
138 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
140 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
141 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
144 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
145 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
150 /* Invalidates the (read-only) L2C cache. This was the L2 cache for
151 * uniforms and instructions on V3D 3.2.
154 v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
159 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
164 /* Invalidates texture L2 cachelines */
166 v3d_flush_l2t(struct v3d_dev *v3d, int core)
168 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't
169 * need to wait for completion before dispatching the job --
170 * L2T accesses will be stalled until the flush has completed.
171 * However, we do need to make sure we don't try to trigger a
172 * new flush while the L2_CLEAN queue is trying to
173 * synchronously clean after a job.
175 mutex_lock(&v3d->cache_clean_lock);
176 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
177 V3D_L2TCACTL_L2TFLS |
178 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
179 mutex_unlock(&v3d->cache_clean_lock);
182 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
184 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has
185 * executed, we need to make sure that the clean is done before
186 * signaling job completion. So, we synchronously wait before
187 * returning, and we make sure that L2 invalidates don't happen in the
188 * meantime to confuse our are-we-done checks.
191 v3d_clean_caches(struct v3d_dev *v3d)
193 struct drm_device *dev = &v3d->drm;
196 trace_v3d_cache_clean_begin(dev);
198 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
199 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
200 V3D_L2TCACTL_TMUWCF), 100)) {
201 DRM_ERROR("Timeout waiting for TMU write combiner flush\n");
204 mutex_lock(&v3d->cache_clean_lock);
205 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
206 V3D_L2TCACTL_L2TFLS |
207 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM));
209 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
210 V3D_L2TCACTL_L2TFLS), 100)) {
211 DRM_ERROR("Timeout waiting for L2T clean\n");
214 mutex_unlock(&v3d->cache_clean_lock);
216 trace_v3d_cache_clean_end(dev);
219 /* Invalidates the slice caches. These are read-only caches. */
221 v3d_invalidate_slices(struct v3d_dev *v3d, int core)
223 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
224 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
225 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
226 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
227 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
231 v3d_invalidate_caches(struct v3d_dev *v3d)
233 /* Invalidate the caches from the outside in. That way if
234 * another CL's concurrent use of nearby memory were to pull
235 * an invalidated cacheline back in, we wouldn't leave stale
236 * data in the inner cache.
239 v3d_invalidate_l2c(v3d, 0);
240 v3d_flush_l2t(v3d, 0);
241 v3d_invalidate_slices(v3d, 0);
244 /* Takes the reservation lock on all the BOs being referenced, so that
245 * at queue submit time we can update the reservations.
247 * We don't lock the RCL the tile alloc/state BOs, or overflow memory
248 * (all of which are on exec->unref_list). They're entirely private
249 * to v3d, so we don't attach dma-buf fences to them.
252 v3d_lock_bo_reservations(struct v3d_job *job,
253 struct ww_acquire_ctx *acquire_ctx)
257 ret = drm_gem_lock_reservations(job->bo, job->bo_count, acquire_ctx);
261 for (i = 0; i < job->bo_count; i++) {
262 ret = dma_resv_reserve_fences(job->bo[i]->resv, 1);
266 ret = drm_sched_job_add_implicit_dependencies(&job->base,
275 drm_gem_unlock_reservations(job->bo, job->bo_count, acquire_ctx);
280 * v3d_lookup_bos() - Sets up job->bo[] with the GEM objects
281 * referenced by the job.
283 * @file_priv: DRM file for this fd
284 * @job: V3D job being set up
285 * @bo_handles: GEM handles
286 * @bo_count: Number of GEM handles passed in
288 * The command validator needs to reference BOs by their index within
289 * the submitted job's BO list. This does the validation of the job's
290 * BO list and reference counting for the lifetime of the job.
292 * Note that this function doesn't need to unreference the BOs on
293 * failure, because that will happen at v3d_exec_cleanup() time.
296 v3d_lookup_bos(struct drm_device *dev,
297 struct drm_file *file_priv,
306 job->bo_count = bo_count;
308 if (!job->bo_count) {
309 /* See comment on bo_index for why we have to check
312 DRM_DEBUG("Rendering requires BOs\n");
316 job->bo = kvmalloc_array(job->bo_count,
317 sizeof(struct drm_gem_cma_object *),
318 GFP_KERNEL | __GFP_ZERO);
320 DRM_DEBUG("Failed to allocate validated BO pointers\n");
324 handles = kvmalloc_array(job->bo_count, sizeof(u32), GFP_KERNEL);
327 DRM_DEBUG("Failed to allocate incoming GEM handles\n");
331 if (copy_from_user(handles,
332 (void __user *)(uintptr_t)bo_handles,
333 job->bo_count * sizeof(u32))) {
335 DRM_DEBUG("Failed to copy in GEM handles\n");
339 spin_lock(&file_priv->table_lock);
340 for (i = 0; i < job->bo_count; i++) {
341 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
344 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
347 spin_unlock(&file_priv->table_lock);
350 drm_gem_object_get(bo);
353 spin_unlock(&file_priv->table_lock);
361 v3d_job_free(struct kref *ref)
363 struct v3d_job *job = container_of(ref, struct v3d_job, refcount);
366 for (i = 0; i < job->bo_count; i++) {
368 drm_gem_object_put(job->bo[i]);
372 dma_fence_put(job->irq_fence);
373 dma_fence_put(job->done_fence);
375 pm_runtime_mark_last_busy(job->v3d->drm.dev);
376 pm_runtime_put_autosuspend(job->v3d->drm.dev);
379 v3d_perfmon_put(job->perfmon);
385 v3d_render_job_free(struct kref *ref)
387 struct v3d_render_job *job = container_of(ref, struct v3d_render_job,
389 struct v3d_bo *bo, *save;
391 list_for_each_entry_safe(bo, save, &job->unref_list, unref_head) {
392 drm_gem_object_put(&bo->base.base);
398 void v3d_job_cleanup(struct v3d_job *job)
403 drm_sched_job_cleanup(&job->base);
407 void v3d_job_put(struct v3d_job *job)
409 kref_put(&job->refcount, job->free);
413 v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
414 struct drm_file *file_priv)
417 struct drm_v3d_wait_bo *args = data;
418 ktime_t start = ktime_get();
420 unsigned long timeout_jiffies =
421 nsecs_to_jiffies_timeout(args->timeout_ns);
426 ret = drm_gem_dma_resv_wait(file_priv, args->handle,
427 true, timeout_jiffies);
429 /* Decrement the user's timeout, in case we got interrupted
430 * such that the ioctl will be restarted.
432 delta_ns = ktime_to_ns(ktime_sub(ktime_get(), start));
433 if (delta_ns < args->timeout_ns)
434 args->timeout_ns -= delta_ns;
436 args->timeout_ns = 0;
438 /* Asked to wait beyond the jiffie/scheduler precision? */
439 if (ret == -ETIME && args->timeout_ns)
446 v3d_job_add_deps(struct drm_file *file_priv, struct v3d_job *job,
447 u32 in_sync, u32 point)
449 struct dma_fence *in_fence = NULL;
452 ret = drm_syncobj_find_fence(file_priv, in_sync, point, 0, &in_fence);
456 return drm_sched_job_add_dependency(&job->base, in_fence);
460 v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv,
461 void **container, size_t size, void (*free)(struct kref *ref),
462 u32 in_sync, struct v3d_submit_ext *se, enum v3d_queue queue)
464 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
466 bool has_multisync = se && (se->flags & DRM_V3D_EXT_ID_MULTI_SYNC);
469 *container = kcalloc(1, size, GFP_KERNEL);
471 DRM_ERROR("Cannot allocate memory for v3d job.");
479 ret = pm_runtime_get_sync(v3d->drm.dev);
483 ret = drm_sched_job_init(&job->base, &v3d_priv->sched_entity[queue],
489 if (se->in_sync_count && se->wait_stage == queue) {
490 struct drm_v3d_sem __user *handle = u64_to_user_ptr(se->in_syncs);
492 for (i = 0; i < se->in_sync_count; i++) {
493 struct drm_v3d_sem in;
495 if (copy_from_user(&in, handle++, sizeof(in))) {
497 DRM_DEBUG("Failed to copy wait dep handle.\n");
500 ret = v3d_job_add_deps(file_priv, job, in.handle, 0);
506 ret = v3d_job_add_deps(file_priv, job, in_sync, 0);
511 kref_init(&job->refcount);
516 drm_sched_job_cleanup(&job->base);
518 pm_runtime_put_autosuspend(v3d->drm.dev);
527 v3d_push_job(struct v3d_job *job)
529 drm_sched_job_arm(&job->base);
531 job->done_fence = dma_fence_get(&job->base.s_fence->finished);
533 /* put by scheduler job completion */
534 kref_get(&job->refcount);
536 drm_sched_entity_push_job(&job->base);
540 v3d_attach_fences_and_unlock_reservation(struct drm_file *file_priv,
542 struct ww_acquire_ctx *acquire_ctx,
544 struct v3d_submit_ext *se,
545 struct dma_fence *done_fence)
547 struct drm_syncobj *sync_out;
548 bool has_multisync = se && (se->flags & DRM_V3D_EXT_ID_MULTI_SYNC);
551 for (i = 0; i < job->bo_count; i++) {
552 /* XXX: Use shared fences for read-only objects. */
553 dma_resv_add_fence(job->bo[i]->resv, job->done_fence,
554 DMA_RESV_USAGE_WRITE);
557 drm_gem_unlock_reservations(job->bo, job->bo_count, acquire_ctx);
559 /* Update the return sync object for the job */
560 /* If it only supports a single signal semaphore*/
561 if (!has_multisync) {
562 sync_out = drm_syncobj_find(file_priv, out_sync);
564 drm_syncobj_replace_fence(sync_out, done_fence);
565 drm_syncobj_put(sync_out);
570 /* If multiple semaphores extension is supported */
571 if (se->out_sync_count) {
572 for (i = 0; i < se->out_sync_count; i++) {
573 drm_syncobj_replace_fence(se->out_syncs[i].syncobj,
575 drm_syncobj_put(se->out_syncs[i].syncobj);
577 kvfree(se->out_syncs);
582 v3d_put_multisync_post_deps(struct v3d_submit_ext *se)
586 if (!(se && se->out_sync_count))
589 for (i = 0; i < se->out_sync_count; i++)
590 drm_syncobj_put(se->out_syncs[i].syncobj);
591 kvfree(se->out_syncs);
595 v3d_get_multisync_post_deps(struct drm_file *file_priv,
596 struct v3d_submit_ext *se,
597 u32 count, u64 handles)
599 struct drm_v3d_sem __user *post_deps;
605 se->out_syncs = (struct v3d_submit_outsync *)
606 kvmalloc_array(count,
607 sizeof(struct v3d_submit_outsync),
612 post_deps = u64_to_user_ptr(handles);
614 for (i = 0; i < count; i++) {
615 struct drm_v3d_sem out;
617 if (copy_from_user(&out, post_deps++, sizeof(out))) {
619 DRM_DEBUG("Failed to copy post dep handles\n");
623 se->out_syncs[i].syncobj = drm_syncobj_find(file_priv,
625 if (!se->out_syncs[i].syncobj) {
630 se->out_sync_count = count;
635 for (i--; i >= 0; i--)
636 drm_syncobj_put(se->out_syncs[i].syncobj);
637 kvfree(se->out_syncs);
642 /* Get data for multiple binary semaphores synchronization. Parse syncobj
643 * to be signaled when job completes (out_sync).
646 v3d_get_multisync_submit_deps(struct drm_file *file_priv,
647 struct drm_v3d_extension __user *ext,
650 struct drm_v3d_multi_sync multisync;
651 struct v3d_submit_ext *se = data;
654 if (copy_from_user(&multisync, ext, sizeof(multisync)))
660 ret = v3d_get_multisync_post_deps(file_priv, data, multisync.out_sync_count,
661 multisync.out_syncs);
665 se->in_sync_count = multisync.in_sync_count;
666 se->in_syncs = multisync.in_syncs;
667 se->flags |= DRM_V3D_EXT_ID_MULTI_SYNC;
668 se->wait_stage = multisync.wait_stage;
673 /* Whenever userspace sets ioctl extensions, v3d_get_extensions parses data
674 * according to the extension id (name).
677 v3d_get_extensions(struct drm_file *file_priv,
681 struct drm_v3d_extension __user *user_ext;
684 user_ext = u64_to_user_ptr(ext_handles);
686 struct drm_v3d_extension ext;
688 if (copy_from_user(&ext, user_ext, sizeof(ext))) {
689 DRM_DEBUG("Failed to copy submit extension\n");
694 case DRM_V3D_EXT_ID_MULTI_SYNC:
695 ret = v3d_get_multisync_submit_deps(file_priv, user_ext, data);
700 DRM_DEBUG_DRIVER("Unknown extension id: %d\n", ext.id);
704 user_ext = u64_to_user_ptr(ext.next);
711 * v3d_submit_cl_ioctl() - Submits a job (frame) to the V3D.
713 * @data: ioctl argument
714 * @file_priv: DRM file for this fd
716 * This is the main entrypoint for userspace to submit a 3D frame to
717 * the GPU. Userspace provides the binner command list (if
718 * applicable), and the kernel sets up the render command list to draw
719 * to the framebuffer described in the ioctl, using the command lists
720 * that the 3D engine's binner will produce.
723 v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
726 struct v3d_dev *v3d = to_v3d_dev(dev);
727 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
728 struct drm_v3d_submit_cl *args = data;
729 struct v3d_submit_ext se = {0};
730 struct v3d_bin_job *bin = NULL;
731 struct v3d_render_job *render = NULL;
732 struct v3d_job *clean_job = NULL;
733 struct v3d_job *last_job;
734 struct ww_acquire_ctx acquire_ctx;
737 trace_v3d_submit_cl_ioctl(&v3d->drm, args->rcl_start, args->rcl_end);
743 args->flags & ~(DRM_V3D_SUBMIT_CL_FLUSH_CACHE |
744 DRM_V3D_SUBMIT_EXTENSION)) {
745 DRM_INFO("invalid flags: %d\n", args->flags);
749 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
750 ret = v3d_get_extensions(file_priv, args->extensions, &se);
752 DRM_DEBUG("Failed to get extensions.\n");
757 ret = v3d_job_init(v3d, file_priv, (void *)&render, sizeof(*render),
758 v3d_render_job_free, args->in_sync_rcl, &se, V3D_RENDER);
762 render->start = args->rcl_start;
763 render->end = args->rcl_end;
764 INIT_LIST_HEAD(&render->unref_list);
766 if (args->bcl_start != args->bcl_end) {
767 ret = v3d_job_init(v3d, file_priv, (void *)&bin, sizeof(*bin),
768 v3d_job_free, args->in_sync_bcl, &se, V3D_BIN);
772 bin->start = args->bcl_start;
773 bin->end = args->bcl_end;
774 bin->qma = args->qma;
775 bin->qms = args->qms;
776 bin->qts = args->qts;
777 bin->render = render;
780 if (args->flags & DRM_V3D_SUBMIT_CL_FLUSH_CACHE) {
781 ret = v3d_job_init(v3d, file_priv, (void *)&clean_job, sizeof(*clean_job),
782 v3d_job_free, 0, NULL, V3D_CACHE_CLEAN);
786 last_job = clean_job;
788 last_job = &render->base;
791 ret = v3d_lookup_bos(dev, file_priv, last_job,
792 args->bo_handles, args->bo_handle_count);
796 ret = v3d_lock_bo_reservations(last_job, &acquire_ctx);
800 if (args->perfmon_id) {
801 render->base.perfmon = v3d_perfmon_find(v3d_priv,
804 if (!render->base.perfmon) {
810 mutex_lock(&v3d->sched_lock);
812 bin->base.perfmon = render->base.perfmon;
813 v3d_perfmon_get(bin->base.perfmon);
814 v3d_push_job(&bin->base);
816 ret = drm_sched_job_add_dependency(&render->base.base,
817 dma_fence_get(bin->base.done_fence));
822 v3d_push_job(&render->base);
825 struct dma_fence *render_fence =
826 dma_fence_get(render->base.done_fence);
827 ret = drm_sched_job_add_dependency(&clean_job->base,
831 clean_job->perfmon = render->base.perfmon;
832 v3d_perfmon_get(clean_job->perfmon);
833 v3d_push_job(clean_job);
836 mutex_unlock(&v3d->sched_lock);
838 v3d_attach_fences_and_unlock_reservation(file_priv,
843 last_job->done_fence);
846 v3d_job_put(&bin->base);
847 v3d_job_put(&render->base);
849 v3d_job_put(clean_job);
854 mutex_unlock(&v3d->sched_lock);
856 drm_gem_unlock_reservations(last_job->bo,
857 last_job->bo_count, &acquire_ctx);
859 v3d_job_cleanup((void *)bin);
860 v3d_job_cleanup((void *)render);
861 v3d_job_cleanup(clean_job);
862 v3d_put_multisync_post_deps(&se);
868 * v3d_submit_tfu_ioctl() - Submits a TFU (texture formatting) job to the V3D.
870 * @data: ioctl argument
871 * @file_priv: DRM file for this fd
873 * Userspace provides the register setup for the TFU, which we don't
874 * need to validate since the TFU is behind the MMU.
877 v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file_priv)
880 struct v3d_dev *v3d = to_v3d_dev(dev);
881 struct drm_v3d_submit_tfu *args = data;
882 struct v3d_submit_ext se = {0};
883 struct v3d_tfu_job *job = NULL;
884 struct ww_acquire_ctx acquire_ctx;
887 trace_v3d_submit_tfu_ioctl(&v3d->drm, args->iia);
889 if (args->flags && !(args->flags & DRM_V3D_SUBMIT_EXTENSION)) {
890 DRM_DEBUG("invalid flags: %d\n", args->flags);
894 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
895 ret = v3d_get_extensions(file_priv, args->extensions, &se);
897 DRM_DEBUG("Failed to get extensions.\n");
902 ret = v3d_job_init(v3d, file_priv, (void *)&job, sizeof(*job),
903 v3d_job_free, args->in_sync, &se, V3D_TFU);
907 job->base.bo = kcalloc(ARRAY_SIZE(args->bo_handles),
908 sizeof(*job->base.bo), GFP_KERNEL);
916 spin_lock(&file_priv->table_lock);
917 for (job->base.bo_count = 0;
918 job->base.bo_count < ARRAY_SIZE(args->bo_handles);
919 job->base.bo_count++) {
920 struct drm_gem_object *bo;
922 if (!args->bo_handles[job->base.bo_count])
925 bo = idr_find(&file_priv->object_idr,
926 args->bo_handles[job->base.bo_count]);
928 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
930 args->bo_handles[job->base.bo_count]);
932 spin_unlock(&file_priv->table_lock);
935 drm_gem_object_get(bo);
936 job->base.bo[job->base.bo_count] = bo;
938 spin_unlock(&file_priv->table_lock);
940 ret = v3d_lock_bo_reservations(&job->base, &acquire_ctx);
944 mutex_lock(&v3d->sched_lock);
945 v3d_push_job(&job->base);
946 mutex_unlock(&v3d->sched_lock);
948 v3d_attach_fences_and_unlock_reservation(file_priv,
949 &job->base, &acquire_ctx,
952 job->base.done_fence);
954 v3d_job_put(&job->base);
959 v3d_job_cleanup((void *)job);
960 v3d_put_multisync_post_deps(&se);
966 * v3d_submit_csd_ioctl() - Submits a CSD (texture formatting) job to the V3D.
968 * @data: ioctl argument
969 * @file_priv: DRM file for this fd
971 * Userspace provides the register setup for the CSD, which we don't
972 * need to validate since the CSD is behind the MMU.
975 v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
976 struct drm_file *file_priv)
978 struct v3d_dev *v3d = to_v3d_dev(dev);
979 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
980 struct drm_v3d_submit_csd *args = data;
981 struct v3d_submit_ext se = {0};
982 struct v3d_csd_job *job = NULL;
983 struct v3d_job *clean_job = NULL;
984 struct ww_acquire_ctx acquire_ctx;
987 trace_v3d_submit_csd_ioctl(&v3d->drm, args->cfg[5], args->cfg[6]);
992 if (!v3d_has_csd(v3d)) {
993 DRM_DEBUG("Attempting CSD submit on non-CSD hardware\n");
997 if (args->flags && !(args->flags & DRM_V3D_SUBMIT_EXTENSION)) {
998 DRM_INFO("invalid flags: %d\n", args->flags);
1002 if (args->flags & DRM_V3D_SUBMIT_EXTENSION) {
1003 ret = v3d_get_extensions(file_priv, args->extensions, &se);
1005 DRM_DEBUG("Failed to get extensions.\n");
1010 ret = v3d_job_init(v3d, file_priv, (void *)&job, sizeof(*job),
1011 v3d_job_free, args->in_sync, &se, V3D_CSD);
1015 ret = v3d_job_init(v3d, file_priv, (void *)&clean_job, sizeof(*clean_job),
1016 v3d_job_free, 0, NULL, V3D_CACHE_CLEAN);
1022 ret = v3d_lookup_bos(dev, file_priv, clean_job,
1023 args->bo_handles, args->bo_handle_count);
1027 ret = v3d_lock_bo_reservations(clean_job, &acquire_ctx);
1031 if (args->perfmon_id) {
1032 job->base.perfmon = v3d_perfmon_find(v3d_priv,
1034 if (!job->base.perfmon) {
1040 mutex_lock(&v3d->sched_lock);
1041 v3d_push_job(&job->base);
1043 ret = drm_sched_job_add_dependency(&clean_job->base,
1044 dma_fence_get(job->base.done_fence));
1046 goto fail_unreserve;
1048 v3d_push_job(clean_job);
1049 mutex_unlock(&v3d->sched_lock);
1051 v3d_attach_fences_and_unlock_reservation(file_priv,
1056 clean_job->done_fence);
1058 v3d_job_put(&job->base);
1059 v3d_job_put(clean_job);
1064 mutex_unlock(&v3d->sched_lock);
1066 drm_gem_unlock_reservations(clean_job->bo, clean_job->bo_count,
1069 v3d_job_cleanup((void *)job);
1070 v3d_job_cleanup(clean_job);
1071 v3d_put_multisync_post_deps(&se);
1077 v3d_gem_init(struct drm_device *dev)
1079 struct v3d_dev *v3d = to_v3d_dev(dev);
1080 u32 pt_size = 4096 * 1024;
1083 for (i = 0; i < V3D_MAX_QUEUES; i++)
1084 v3d->queue[i].fence_context = dma_fence_context_alloc(1);
1086 spin_lock_init(&v3d->mm_lock);
1087 spin_lock_init(&v3d->job_lock);
1088 mutex_init(&v3d->bo_lock);
1089 mutex_init(&v3d->reset_lock);
1090 mutex_init(&v3d->sched_lock);
1091 mutex_init(&v3d->cache_clean_lock);
1093 /* Note: We don't allocate address 0. Various bits of HW
1094 * treat 0 as special, such as the occlusion query counters
1095 * where 0 means "disabled".
1097 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
1099 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size,
1101 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
1103 drm_mm_takedown(&v3d->mm);
1104 dev_err(v3d->drm.dev,
1105 "Failed to allocate page tables. Please ensure you have CMA enabled.\n");
1109 v3d_init_hw_state(v3d);
1110 v3d_mmu_set_page_table(v3d);
1112 ret = v3d_sched_init(v3d);
1114 drm_mm_takedown(&v3d->mm);
1115 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,
1123 v3d_gem_destroy(struct drm_device *dev)
1125 struct v3d_dev *v3d = to_v3d_dev(dev);
1127 v3d_sched_fini(v3d);
1129 /* Waiting for jobs to finish would need to be done before
1130 * unregistering V3D.
1132 WARN_ON(v3d->bin_job);
1133 WARN_ON(v3d->render_job);
1135 drm_mm_takedown(&v3d->mm);
1137 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,