1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
4 #include <linux/delay.h>
5 #include <linux/mutex.h>
6 #include <linux/spinlock_types.h>
7 #include <linux/workqueue.h>
9 #include <drm/drm_encoder.h>
10 #include <drm/drm_gem.h>
11 #include <drm/drm_gem_shmem_helper.h>
12 #include <drm/gpu_scheduler.h>
14 #include "uapi/drm/v3d_drm.h"
17 struct platform_device;
20 #define GMP_GRANULARITY (128 * 1024)
22 #define V3D_MAX_QUEUES (V3D_CPU + 1)
24 static inline char *v3d_queue_to_string(enum v3d_queue queue)
27 case V3D_BIN: return "bin";
28 case V3D_RENDER: return "render";
29 case V3D_TFU: return "tfu";
30 case V3D_CSD: return "csd";
31 case V3D_CACHE_CLEAN: return "cache_clean";
32 case V3D_CPU: return "cpu";
37 struct v3d_queue_state {
38 struct drm_gpu_scheduler sched;
48 /* Performance monitor object. The perform lifetime is controlled by userspace
49 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
50 * request, and when this is the case, HW perf counters will be activated just
51 * before the submit_cl is submitted to the GPU and disabled when the job is
52 * done. This way, only events related to a specific job will be counted.
55 /* Tracks the number of users of the perfmon, when this counter reaches
56 * zero the perfmon is destroyed.
60 /* Protects perfmon stop, as it can be invoked from multiple places. */
63 /* Number of counters activated in this perfmon instance
64 * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
68 /* Events counted by the HW perf counters. */
69 u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
71 /* Storage for counter values. Counters are incremented by the
72 * HW perf counter values every time the perfmon is attached
73 * to a GPU job. This way, perfmon users don't have to
74 * retrieve the results after each job if they want to track
75 * events covering several submissions. Note that counter
76 * values can't be reset, but you can fake a reset by
77 * destroying the perfmon and creating a new one.
79 u64 values[] __counted_by(ncounters);
83 struct drm_device drm;
85 /* Short representation (e.g. 33, 41) of the V3D tech version
91 void __iomem *hub_regs;
92 void __iomem *core_regs[3];
93 void __iomem *bridge_regs;
94 void __iomem *gca_regs;
96 struct reset_control *reset;
98 /* Virtual and DMA addresses of the single shared page table. */
102 /* Virtual and DMA addresses of the MMU's scratch page. When
103 * a read or write is invalid in the MMU, it will be
107 dma_addr_t mmu_scratch_paddr;
108 /* virtual address bits from V3D to the MMU. */
111 /* Number of V3D cores. */
114 /* Allocator managing the address space. All units are in
120 struct work_struct overflow_mem_work;
122 struct v3d_bin_job *bin_job;
123 struct v3d_render_job *render_job;
124 struct v3d_tfu_job *tfu_job;
125 struct v3d_csd_job *csd_job;
126 struct v3d_cpu_job *cpu_job;
128 struct v3d_queue_state queue[V3D_MAX_QUEUES];
130 /* Spinlock used to synchronize the overflow memory
131 * management against bin job submission.
135 /* Used to track the active perfmon if any. */
136 struct v3d_perfmon *active_perfmon;
138 /* Protects bo_stats */
139 struct mutex bo_lock;
141 /* Lock taken when resetting the GPU, to keep multiple
142 * processes from trying to park the scheduler threads and
145 struct mutex reset_lock;
147 /* Lock taken when creating and pushing the GPU scheduler
148 * jobs, to keep the sched-fence seqnos in order.
150 struct mutex sched_lock;
152 /* Lock taken during a cache clean and when initiating an L2
153 * flush, to keep L2 flushes from interfering with the
154 * synchronous L2 cleans.
156 struct mutex cache_clean_lock;
164 static inline struct v3d_dev *
165 to_v3d_dev(struct drm_device *dev)
167 return container_of(dev, struct v3d_dev, drm);
171 v3d_has_csd(struct v3d_dev *v3d)
173 return v3d->ver >= 41;
176 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
178 /* The per-fd struct, which tracks the MMU mappings. */
179 struct v3d_file_priv {
187 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
189 u64 start_ns[V3D_MAX_QUEUES];
191 u64 enabled_ns[V3D_MAX_QUEUES];
193 u64 jobs_sent[V3D_MAX_QUEUES];
197 struct drm_gem_shmem_object base;
199 struct drm_mm_node node;
201 /* List entry for the BO's position in
202 * v3d_render_job->unref_list
204 struct list_head unref_head;
209 static inline struct v3d_bo *
210 to_v3d_bo(struct drm_gem_object *bo)
212 return (struct v3d_bo *)bo;
216 struct dma_fence base;
217 struct drm_device *dev;
218 /* v3d seqno for signaled() test */
220 enum v3d_queue queue;
223 static inline struct v3d_fence *
224 to_v3d_fence(struct dma_fence *fence)
226 return (struct v3d_fence *)fence;
229 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
230 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
232 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
233 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
235 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
236 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
238 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
239 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
242 struct drm_sched_job base;
244 struct kref refcount;
248 /* This is the array of BOs that were looked up at the start
251 struct drm_gem_object **bo;
254 /* v3d fence to be signaled by IRQ handler when the job is complete. */
255 struct dma_fence *irq_fence;
257 /* scheduler fence for when the job is considered complete and
258 * the BO reservations can be released.
260 struct dma_fence *done_fence;
262 /* Pointer to a performance monitor object if the user requested it,
265 struct v3d_perfmon *perfmon;
267 /* File descriptor of the process that submitted the job that could be used
268 * for collecting stats by process of GPU usage.
270 struct drm_file *file;
272 /* Callback for the freeing of the job on refcount going to 0. */
273 void (*free)(struct kref *ref);
279 /* GPU virtual addresses of the start/end of the CL job. */
282 u32 timedout_ctca, timedout_ctra;
284 /* Corresponding render job, for attaching our overflow memory. */
285 struct v3d_render_job *render;
287 /* Submitted tile memory allocation start/size, tile state. */
291 struct v3d_render_job {
294 /* GPU virtual addresses of the start/end of the CL job. */
297 u32 timedout_ctca, timedout_ctra;
299 /* List of overflow BOs used in the job that need to be
300 * released once the job is complete.
302 struct list_head unref_list;
308 struct drm_v3d_submit_tfu args;
314 u32 timedout_batches;
316 struct drm_v3d_submit_csd args;
319 enum v3d_cpu_job_type {
320 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1,
321 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY,
322 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY,
323 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY,
324 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY,
325 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY,
328 struct v3d_timestamp_query {
329 /* Offset of this query in the timestamp BO for its value. */
332 /* Syncobj that indicates the timestamp availability */
333 struct drm_syncobj *syncobj;
336 /* Number of perfmons required to handle all supported performance counters */
337 #define V3D_MAX_PERFMONS DIV_ROUND_UP(V3D_PERFCNT_NUM, \
338 DRM_V3D_MAX_PERF_COUNTERS)
340 struct v3d_performance_query {
341 /* Performance monitor IDs for this query */
342 u32 kperfmon_ids[V3D_MAX_PERFMONS];
344 /* Syncobj that indicates the query availability */
345 struct drm_syncobj *syncobj;
348 struct v3d_indirect_csd_info {
350 struct v3d_csd_job *job;
352 /* Clean cache job associated to the Indirect CSD job */
353 struct v3d_job *clean_job;
355 /* Offset within the BO where the workgroup counts are stored */
358 /* Workgroups size */
361 /* Indices of the uniforms with the workgroup dispatch counts
362 * in the uniform stream.
364 u32 wg_uniform_offsets[3];
367 struct drm_gem_object *indirect;
369 /* Context of the Indirect CSD job */
370 struct ww_acquire_ctx acquire_ctx;
373 struct v3d_timestamp_query_info {
374 struct v3d_timestamp_query *queries;
379 struct v3d_performance_query_info {
380 struct v3d_performance_query *queries;
382 /* Number of performance queries */
385 /* Number of performance monitors related to that query pool */
388 /* Number of performance counters related to that query pool */
392 struct v3d_copy_query_results_info {
393 /* Define if should write to buffer using 64 or 32 bits */
396 /* Define if it can write to buffer even if the query is not available */
399 /* Define if it should write availability bit to buffer */
400 bool availability_bit;
402 /* Offset of the copy buffer in the BO */
405 /* Stride of the copy buffer in the BO */
412 enum v3d_cpu_job_type job_type;
414 struct v3d_indirect_csd_info indirect_csd;
416 struct v3d_timestamp_query_info timestamp_query;
418 struct v3d_copy_query_results_info copy;
420 struct v3d_performance_query_info performance_query;
423 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *);
425 struct v3d_submit_outsync {
426 struct drm_syncobj *syncobj;
429 struct v3d_submit_ext {
437 struct v3d_submit_outsync *out_syncs;
441 * __wait_for - magic wait macro
443 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
444 * important that we check the condition again after having timed out, since the
445 * timeout could be due to preemption or similar and we've never had a chance to
446 * check the condition before the timeout.
448 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
449 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
450 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
454 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
456 /* Guarantee COND check prior to timeout */ \
463 ret__ = -ETIMEDOUT; \
466 usleep_range(wait__, wait__ * 2); \
467 if (wait__ < (Wmax)) \
473 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
475 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
477 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
479 /* nsecs_to_jiffies64() does not guard against overflow */
480 if ((NSEC_PER_SEC % HZ) != 0 &&
481 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
482 return MAX_JIFFY_OFFSET;
484 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
488 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
489 void v3d_free_object(struct drm_gem_object *gem_obj);
490 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
492 void v3d_get_bo_vaddr(struct v3d_bo *bo);
493 void v3d_put_bo_vaddr(struct v3d_bo *bo);
494 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *file_priv);
496 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
497 struct drm_file *file_priv);
498 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
499 struct drm_file *file_priv);
500 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
501 struct drm_file *file_priv);
502 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
503 struct dma_buf_attachment *attach,
504 struct sg_table *sgt);
507 void v3d_debugfs_init(struct drm_minor *minor);
510 extern const struct dma_fence_ops v3d_fence_ops;
511 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
514 int v3d_gem_init(struct drm_device *dev);
515 void v3d_gem_destroy(struct drm_device *dev);
516 void v3d_reset(struct v3d_dev *v3d);
517 void v3d_invalidate_caches(struct v3d_dev *v3d);
518 void v3d_clean_caches(struct v3d_dev *v3d);
521 void v3d_job_cleanup(struct v3d_job *job);
522 void v3d_job_put(struct v3d_job *job);
523 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file_priv);
525 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv);
527 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
528 struct drm_file *file_priv);
529 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data,
530 struct drm_file *file_priv);
533 int v3d_irq_init(struct v3d_dev *v3d);
534 void v3d_irq_enable(struct v3d_dev *v3d);
535 void v3d_irq_disable(struct v3d_dev *v3d);
536 void v3d_irq_reset(struct v3d_dev *v3d);
539 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
540 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
541 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
544 int v3d_sched_init(struct v3d_dev *v3d);
545 void v3d_sched_fini(struct v3d_dev *v3d);
548 void v3d_perfmon_get(struct v3d_perfmon *perfmon);
549 void v3d_perfmon_put(struct v3d_perfmon *perfmon);
550 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
551 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
553 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
554 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
555 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
556 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
557 struct drm_file *file_priv);
558 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
559 struct drm_file *file_priv);
560 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
561 struct drm_file *file_priv);
564 int v3d_sysfs_init(struct device *dev);
565 void v3d_sysfs_destroy(struct device *dev);