1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
7 #include <drm/drm_atomic.h>
8 #include <drm/drm_atomic_helper.h>
9 #include <drm/drm_crtc.h>
10 #include <drm/drm_flip_work.h>
11 #include <drm/drm_plane_helper.h>
12 #include <linux/workqueue.h>
13 #include <linux/completion.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/of_graph.h>
16 #include <linux/math64.h>
18 #include "tilcdc_drv.h"
19 #include "tilcdc_regs.h"
21 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
22 #define TILCDC_PALETTE_SIZE 32
23 #define TILCDC_PALETTE_FIRST_ENTRY 0x4000
28 struct drm_plane primary;
29 const struct tilcdc_panel_info *info;
30 struct drm_pending_vblank_event *event;
31 struct mutex enable_lock;
34 wait_queue_head_t frame_done_wq;
38 unsigned int lcd_fck_rate;
41 unsigned int hvtotal_us;
43 struct drm_framebuffer *next_fb;
45 /* Only set if an external encoder is connected */
46 bool simulate_vesa_sync;
50 struct work_struct recover_work;
52 dma_addr_t palette_dma_handle;
54 struct completion palette_loaded;
56 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
58 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
60 struct drm_device *dev = crtc->dev;
61 struct tilcdc_drm_private *priv = dev->dev_private;
62 struct drm_gem_cma_object *gem;
63 dma_addr_t start, end;
64 u64 dma_base_and_ceiling;
66 gem = drm_fb_cma_get_gem_obj(fb, 0);
68 start = gem->paddr + fb->offsets[0] +
69 crtc->y * fb->pitches[0] +
70 crtc->x * fb->format->cpp[0];
72 end = start + (crtc->mode.vdisplay * fb->pitches[0]);
74 /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
75 * with a single insruction, if available. This should make it more
76 * unlikely that LCDC would fetch the DMA addresses in the middle of
82 dma_base_and_ceiling = (u64)end << 32 | start;
83 tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
87 * The driver currently only supports only true color formats. For
88 * true color the palette block is bypassed, but a 32 byte palette
89 * should still be loaded. The first 16-bit entry must be 0x4000 while
90 * all other entries must be zeroed.
92 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
94 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
95 struct drm_device *dev = crtc->dev;
96 struct tilcdc_drm_private *priv = dev->dev_private;
99 reinit_completion(&tilcdc_crtc->palette_loaded);
101 /* Tell the LCDC where the palette is located. */
102 tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
103 tilcdc_crtc->palette_dma_handle);
104 tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
105 (u32) tilcdc_crtc->palette_dma_handle +
106 TILCDC_PALETTE_SIZE - 1);
108 /* Set dma load mode for palette loading only. */
109 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
110 LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
111 LCDC_PALETTE_LOAD_MODE_MASK);
113 /* Enable DMA Palette Loaded Interrupt */
115 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
117 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
119 /* Enable LCDC DMA and wait for palette to be loaded. */
120 tilcdc_clear_irqstatus(dev, 0xffffffff);
121 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
123 ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
124 msecs_to_jiffies(50));
126 dev_err(dev->dev, "%s: Palette loading timeout", __func__);
128 /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
129 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
131 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
133 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
136 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
138 struct tilcdc_drm_private *priv = dev->dev_private;
140 tilcdc_clear_irqstatus(dev, 0xffffffff);
142 if (priv->rev == 1) {
143 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
144 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
145 LCDC_V1_UNDERFLOW_INT_ENA);
146 tilcdc_set(dev, LCDC_DMA_CTRL_REG,
147 LCDC_V1_END_OF_FRAME_INT_ENA);
149 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
150 LCDC_V2_UNDERFLOW_INT_ENA |
151 LCDC_V2_END_OF_FRAME0_INT_ENA |
152 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
156 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
158 struct tilcdc_drm_private *priv = dev->dev_private;
160 /* disable irqs that we might have enabled: */
161 if (priv->rev == 1) {
162 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
163 LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
164 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
165 tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
166 LCDC_V1_END_OF_FRAME_INT_ENA);
168 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
169 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
170 LCDC_V2_END_OF_FRAME0_INT_ENA |
171 LCDC_FRAME_DONE | LCDC_SYNC_LOST);
175 static void reset(struct drm_crtc *crtc)
177 struct drm_device *dev = crtc->dev;
178 struct tilcdc_drm_private *priv = dev->dev_private;
183 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
184 usleep_range(250, 1000);
185 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
189 * Calculate the percentage difference between the requested pixel clock rate
190 * and the effective rate resulting from calculating the clock divider value.
192 static unsigned int tilcdc_pclk_diff(unsigned long rate,
193 unsigned long real_rate)
195 int r = rate / 100, rr = real_rate / 100;
197 return (unsigned int)(abs(((rr - r) * 100) / r));
200 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
202 struct drm_device *dev = crtc->dev;
203 struct tilcdc_drm_private *priv = dev->dev_private;
204 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
205 unsigned long clk_rate, real_rate, req_rate;
209 clkdiv = 2; /* first try using a standard divider of 2 */
211 /* mode.clock is in KHz, set_rate wants parameter in Hz */
212 req_rate = crtc->mode.clock * 1000;
214 ret = clk_set_rate(priv->clk, req_rate * clkdiv);
215 clk_rate = clk_get_rate(priv->clk);
216 if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) {
218 * If we fail to set the clock rate (some architectures don't
219 * use the common clock framework yet and may not implement
220 * all the clk API calls for every clock), try the next best
221 * thing: adjusting the clock divider, unless clk_get_rate()
225 /* Nothing more we can do. Just bail out. */
227 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
231 clkdiv = DIV_ROUND_CLOSEST(clk_rate, req_rate);
234 * Emit a warning if the real clock rate resulting from the
235 * calculated divider differs much from the requested rate.
237 * 5% is an arbitrary value - LCDs are usually quite tolerant
238 * about pixel clock rates.
240 real_rate = clkdiv * req_rate;
242 if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) {
244 "effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n",
245 clk_rate, real_rate);
249 tilcdc_crtc->lcd_fck_rate = clk_rate;
251 DBG("lcd_clk=%u, mode clock=%d, div=%u",
252 tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
254 /* Configure the LCD clock divisor. */
255 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
259 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
260 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
261 LCDC_V2_CORE_CLK_EN);
264 static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
266 return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
270 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
272 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct tilcdc_drm_private *priv = dev->dev_private;
275 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
276 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
277 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
278 struct drm_framebuffer *fb = crtc->primary->state->fb;
286 /* Configure the Burst Size and fifo threshold of DMA: */
287 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
288 switch (info->dma_burst_sz) {
290 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
293 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
296 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
299 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
302 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
305 dev_err(dev->dev, "invalid burst size\n");
308 reg |= (info->fifo_th << 8);
309 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
311 /* Configure timings: */
312 hbp = mode->htotal - mode->hsync_end;
313 hfp = mode->hsync_start - mode->hdisplay;
314 hsw = mode->hsync_end - mode->hsync_start;
315 vbp = mode->vtotal - mode->vsync_end;
316 vfp = mode->vsync_start - mode->vdisplay;
317 vsw = mode->vsync_end - mode->vsync_start;
319 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
320 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
322 /* Set AC Bias Period and Number of Transitions per Interrupt: */
323 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
324 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
325 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
328 * subtract one from hfp, hbp, hsw because the hardware uses
331 if (priv->rev == 2) {
332 /* clear bits we're going to set */
334 reg |= ((hfp-1) & 0x300) >> 8;
335 reg |= ((hbp-1) & 0x300) >> 4;
336 reg |= ((hsw-1) & 0x3c0) << 21;
338 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
340 reg = (((mode->hdisplay >> 4) - 1) << 4) |
341 (((hbp-1) & 0xff) << 24) |
342 (((hfp-1) & 0xff) << 16) |
343 (((hsw-1) & 0x3f) << 10);
345 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
346 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
348 reg = ((mode->vdisplay - 1) & 0x3ff) |
349 ((vbp & 0xff) << 24) |
350 ((vfp & 0xff) << 16) |
351 (((vsw-1) & 0x3f) << 10);
352 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
355 * be sure to set Bit 10 for the V2 LCDC controller,
356 * otherwise limited to 1024 pixels width, stopping
357 * 1920x1080 being supported.
359 if (priv->rev == 2) {
360 if ((mode->vdisplay - 1) & 0x400) {
361 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
364 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
369 /* Configure display type: */
370 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
371 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
372 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
373 0x000ff000 /* Palette Loading Delay bits */);
374 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
375 if (info->tft_alt_mode)
376 reg |= LCDC_TFT_ALT_ENABLE;
377 if (priv->rev == 2) {
378 switch (fb->format->format) {
379 case DRM_FORMAT_BGR565:
380 case DRM_FORMAT_RGB565:
382 case DRM_FORMAT_XBGR8888:
383 case DRM_FORMAT_XRGB8888:
384 reg |= LCDC_V2_TFT_24BPP_UNPACK;
386 case DRM_FORMAT_BGR888:
387 case DRM_FORMAT_RGB888:
388 reg |= LCDC_V2_TFT_24BPP_MODE;
391 dev_err(dev->dev, "invalid pixel format\n");
395 reg |= info->fdd < 12;
396 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
398 if (info->invert_pxl_clk)
399 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
401 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
404 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
406 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
409 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
411 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
413 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
414 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
416 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
418 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
419 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
421 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
423 if (info->raster_order)
424 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
426 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
428 tilcdc_crtc_set_clk(crtc);
430 tilcdc_crtc_load_palette(crtc);
432 set_scanout(crtc, fb);
434 crtc->hwmode = crtc->state->adjusted_mode;
436 tilcdc_crtc->hvtotal_us =
437 tilcdc_mode_hvtotal(&crtc->hwmode);
440 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
442 struct drm_device *dev = crtc->dev;
443 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
446 mutex_lock(&tilcdc_crtc->enable_lock);
447 if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
448 mutex_unlock(&tilcdc_crtc->enable_lock);
452 pm_runtime_get_sync(dev->dev);
456 tilcdc_crtc_set_mode(crtc);
458 tilcdc_crtc_enable_irqs(dev);
460 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
461 tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
462 LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
463 LCDC_PALETTE_LOAD_MODE_MASK);
465 /* There is no real chance for a race here as the time stamp
466 * is taken before the raster DMA is started. The spin-lock is
467 * taken to have a memory barrier after taking the time-stamp
468 * and to avoid a context switch between taking the stamp and
469 * enabling the raster.
471 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
472 tilcdc_crtc->last_vblank = ktime_get();
473 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
474 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
476 drm_crtc_vblank_on(crtc);
478 tilcdc_crtc->enabled = true;
479 mutex_unlock(&tilcdc_crtc->enable_lock);
482 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
483 struct drm_crtc_state *old_state)
485 tilcdc_crtc_enable(crtc);
488 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
490 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
491 struct drm_device *dev = crtc->dev;
494 mutex_lock(&tilcdc_crtc->enable_lock);
496 tilcdc_crtc->shutdown = true;
497 if (!tilcdc_crtc->enabled) {
498 mutex_unlock(&tilcdc_crtc->enable_lock);
501 tilcdc_crtc->frame_done = false;
502 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
505 * Wait for framedone irq which will still come before putting
508 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
509 tilcdc_crtc->frame_done,
510 msecs_to_jiffies(500));
512 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
515 drm_crtc_vblank_off(crtc);
517 tilcdc_crtc_disable_irqs(dev);
519 pm_runtime_put_sync(dev->dev);
521 tilcdc_crtc->enabled = false;
522 mutex_unlock(&tilcdc_crtc->enable_lock);
525 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
527 tilcdc_crtc_off(crtc, false);
530 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
531 struct drm_crtc_state *old_state)
533 tilcdc_crtc_disable(crtc);
536 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
538 tilcdc_crtc_off(crtc, true);
541 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
543 return crtc->state && crtc->state->enable && crtc->state->active;
546 static void tilcdc_crtc_recover_work(struct work_struct *work)
548 struct tilcdc_crtc *tilcdc_crtc =
549 container_of(work, struct tilcdc_crtc, recover_work);
550 struct drm_crtc *crtc = &tilcdc_crtc->base;
552 dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
554 drm_modeset_lock(&crtc->mutex, NULL);
556 if (!tilcdc_crtc_is_on(crtc))
559 tilcdc_crtc_disable(crtc);
560 tilcdc_crtc_enable(crtc);
562 drm_modeset_unlock(&crtc->mutex);
565 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
567 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
569 tilcdc_crtc_shutdown(crtc);
571 flush_workqueue(priv->wq);
573 of_node_put(crtc->port);
574 drm_crtc_cleanup(crtc);
577 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
578 struct drm_framebuffer *fb,
579 struct drm_pending_vblank_event *event)
581 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
582 struct drm_device *dev = crtc->dev;
584 if (tilcdc_crtc->event) {
585 dev_err(dev->dev, "already pending page flip!\n");
589 tilcdc_crtc->event = event;
591 mutex_lock(&tilcdc_crtc->enable_lock);
593 if (tilcdc_crtc->enabled) {
598 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
600 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
601 tilcdc_crtc->hvtotal_us);
602 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
604 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
605 tilcdc_crtc->next_fb = fb;
607 set_scanout(crtc, fb);
609 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
612 mutex_unlock(&tilcdc_crtc->enable_lock);
617 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
618 const struct drm_display_mode *mode,
619 struct drm_display_mode *adjusted_mode)
621 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
623 if (!tilcdc_crtc->simulate_vesa_sync)
627 * tilcdc does not generate VESA-compliant sync but aligns
628 * VS on the second edge of HS instead of first edge.
629 * We use adjusted_mode, to fixup sync by aligning both rising
630 * edges and add HSKEW offset to fix the sync.
632 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
633 adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
635 if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
636 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
637 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
639 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
640 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
646 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
647 struct drm_crtc_state *state)
649 struct drm_display_mode *mode = &state->mode;
652 /* If we are not active we don't care */
656 if (state->state->planes[0].ptr != crtc->primary ||
657 state->state->planes[0].state == NULL ||
658 state->state->planes[0].state->crtc != crtc) {
659 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
663 ret = tilcdc_crtc_mode_valid(crtc, mode);
665 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
672 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
677 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
681 static void tilcdc_crtc_reset(struct drm_crtc *crtc)
683 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
684 struct drm_device *dev = crtc->dev;
687 drm_atomic_helper_crtc_reset(crtc);
689 /* Turn the raster off if it for some reason is on. */
690 pm_runtime_get_sync(dev->dev);
691 if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
692 /* Enable DMA Frame Done Interrupt */
693 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE);
694 tilcdc_clear_irqstatus(dev, 0xffffffff);
696 tilcdc_crtc->frame_done = false;
697 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
699 ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
700 tilcdc_crtc->frame_done,
701 msecs_to_jiffies(500));
703 dev_err(dev->dev, "%s: timeout waiting for framedone\n",
706 pm_runtime_put_sync(dev->dev);
709 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
710 .destroy = tilcdc_crtc_destroy,
711 .set_config = drm_atomic_helper_set_config,
712 .page_flip = drm_atomic_helper_page_flip,
713 .reset = tilcdc_crtc_reset,
714 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
715 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
716 .enable_vblank = tilcdc_crtc_enable_vblank,
717 .disable_vblank = tilcdc_crtc_disable_vblank,
720 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
721 .mode_fixup = tilcdc_crtc_mode_fixup,
722 .atomic_check = tilcdc_crtc_atomic_check,
723 .atomic_enable = tilcdc_crtc_atomic_enable,
724 .atomic_disable = tilcdc_crtc_atomic_disable,
727 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
729 struct drm_device *dev = crtc->dev;
730 struct tilcdc_drm_private *priv = dev->dev_private;
735 else if (priv->rev == 2)
741 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
743 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
744 unsigned int bandwidth;
745 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
748 * check to see if the width is within the range that
749 * the LCD Controller physically supports
751 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
752 return MODE_VIRTUAL_X;
754 /* width must be multiple of 16 */
755 if (mode->hdisplay & 0xf)
756 return MODE_VIRTUAL_X;
758 if (mode->vdisplay > 2048)
759 return MODE_VIRTUAL_Y;
761 DBG("Processing mode %dx%d@%d with pixel clock %d",
762 mode->hdisplay, mode->vdisplay,
763 drm_mode_vrefresh(mode), mode->clock);
765 hbp = mode->htotal - mode->hsync_end;
766 hfp = mode->hsync_start - mode->hdisplay;
767 hsw = mode->hsync_end - mode->hsync_start;
768 vbp = mode->vtotal - mode->vsync_end;
769 vfp = mode->vsync_start - mode->vdisplay;
770 vsw = mode->vsync_end - mode->vsync_start;
772 if ((hbp-1) & ~0x3ff) {
773 DBG("Pruning mode: Horizontal Back Porch out of range");
774 return MODE_HBLANK_WIDE;
777 if ((hfp-1) & ~0x3ff) {
778 DBG("Pruning mode: Horizontal Front Porch out of range");
779 return MODE_HBLANK_WIDE;
782 if ((hsw-1) & ~0x3ff) {
783 DBG("Pruning mode: Horizontal Sync Width out of range");
784 return MODE_HSYNC_WIDE;
788 DBG("Pruning mode: Vertical Back Porch out of range");
789 return MODE_VBLANK_WIDE;
793 DBG("Pruning mode: Vertical Front Porch out of range");
794 return MODE_VBLANK_WIDE;
797 if ((vsw-1) & ~0x3f) {
798 DBG("Pruning mode: Vertical Sync Width out of range");
799 return MODE_VSYNC_WIDE;
803 * some devices have a maximum allowed pixel clock
804 * configured from the DT
806 if (mode->clock > priv->max_pixelclock) {
807 DBG("Pruning mode: pixel clock too high");
808 return MODE_CLOCK_HIGH;
812 * some devices further limit the max horizontal resolution
813 * configured from the DT
815 if (mode->hdisplay > priv->max_width)
816 return MODE_BAD_WIDTH;
818 /* filter out modes that would require too much memory bandwidth: */
819 bandwidth = mode->hdisplay * mode->vdisplay *
820 drm_mode_vrefresh(mode);
821 if (bandwidth > priv->max_bandwidth) {
822 DBG("Pruning mode: exceeds defined bandwidth limit");
829 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
830 const struct tilcdc_panel_info *info)
832 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
833 tilcdc_crtc->info = info;
836 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
837 bool simulate_vesa_sync)
839 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
841 tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
844 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
846 struct drm_device *dev = crtc->dev;
847 struct tilcdc_drm_private *priv = dev->dev_private;
848 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
850 drm_modeset_lock(&crtc->mutex, NULL);
851 if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
852 if (tilcdc_crtc_is_on(crtc)) {
853 pm_runtime_get_sync(dev->dev);
854 tilcdc_crtc_disable(crtc);
856 tilcdc_crtc_set_clk(crtc);
858 tilcdc_crtc_enable(crtc);
859 pm_runtime_put_sync(dev->dev);
862 drm_modeset_unlock(&crtc->mutex);
865 #define SYNC_LOST_COUNT_LIMIT 50
867 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
869 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
870 struct drm_device *dev = crtc->dev;
871 struct tilcdc_drm_private *priv = dev->dev_private;
874 stat = tilcdc_read_irqstatus(dev);
875 tilcdc_clear_irqstatus(dev, stat);
877 if (stat & LCDC_END_OF_FRAME0) {
879 bool skip_event = false;
884 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
886 tilcdc_crtc->last_vblank = now;
888 if (tilcdc_crtc->next_fb) {
889 set_scanout(crtc, tilcdc_crtc->next_fb);
890 tilcdc_crtc->next_fb = NULL;
894 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
896 drm_crtc_handle_vblank(crtc);
899 struct drm_pending_vblank_event *event;
901 spin_lock_irqsave(&dev->event_lock, flags);
903 event = tilcdc_crtc->event;
904 tilcdc_crtc->event = NULL;
906 drm_crtc_send_vblank_event(crtc, event);
908 spin_unlock_irqrestore(&dev->event_lock, flags);
911 if (tilcdc_crtc->frame_intact)
912 tilcdc_crtc->sync_lost_count = 0;
914 tilcdc_crtc->frame_intact = true;
917 if (stat & LCDC_FIFO_UNDERFLOW)
918 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
921 if (stat & LCDC_PL_LOAD_DONE) {
922 complete(&tilcdc_crtc->palette_loaded);
924 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
927 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
931 if (stat & LCDC_SYNC_LOST) {
932 dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
934 tilcdc_crtc->frame_intact = false;
935 if (priv->rev == 1) {
936 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
937 if (reg & LCDC_RASTER_ENABLE) {
938 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
940 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
944 if (tilcdc_crtc->sync_lost_count++ >
945 SYNC_LOST_COUNT_LIMIT) {
947 "%s(0x%08x): Sync lost flood detected, recovering",
949 queue_work(system_wq,
950 &tilcdc_crtc->recover_work);
951 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
953 tilcdc_crtc->sync_lost_count = 0;
958 if (stat & LCDC_FRAME_DONE) {
959 tilcdc_crtc->frame_done = true;
960 wake_up(&tilcdc_crtc->frame_done_wq);
961 /* rev 1 lcdc appears to hang if irq is not disbaled here */
963 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
964 LCDC_V1_FRAME_DONE_INT_ENA);
967 /* For revision 2 only */
968 if (priv->rev == 2) {
969 /* Indicate to LCDC that the interrupt service routine has
970 * completed, see 13.3.6.1.6 in AM335x TRM.
972 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
978 int tilcdc_crtc_create(struct drm_device *dev)
980 struct tilcdc_drm_private *priv = dev->dev_private;
981 struct tilcdc_crtc *tilcdc_crtc;
982 struct drm_crtc *crtc;
985 tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
989 init_completion(&tilcdc_crtc->palette_loaded);
990 tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
992 &tilcdc_crtc->palette_dma_handle,
993 GFP_KERNEL | __GFP_ZERO);
994 if (!tilcdc_crtc->palette_base)
996 *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
998 crtc = &tilcdc_crtc->base;
1000 ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1004 mutex_init(&tilcdc_crtc->enable_lock);
1006 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1008 spin_lock_init(&tilcdc_crtc->irq_lock);
1009 INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1011 ret = drm_crtc_init_with_planes(dev, crtc,
1012 &tilcdc_crtc->primary,
1019 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1021 if (priv->is_componentized) {
1022 crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1023 if (!crtc->port) { /* This should never happen */
1024 dev_err(dev->dev, "Port node not found in %pOF\n",
1035 tilcdc_crtc_destroy(crtc);