2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/clk-provider.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
20 #include <soc/tegra/pmc.h>
22 #include <sound/hda_verbs.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_dp_helper.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_scdc_helper.h>
34 #define SOR_REKEY 0x38
36 struct tegra_sor_hdmi_settings {
37 unsigned long frequency;
56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
58 .frequency = 54000000,
70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
73 .frequency = 75000000,
85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
88 .frequency = 150000000,
100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
103 .frequency = 300000000,
111 .bg_vref_level = 0xa,
115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
118 .frequency = 600000000,
126 .bg_vref_level = 0x8,
130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
137 .frequency = 75000000,
145 .bg_vref_level = 0x8,
149 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
152 .frequency = 150000000,
160 .bg_vref_level = 0x8,
164 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
167 .frequency = 300000000,
175 .bg_vref_level = 0xf,
179 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
182 .frequency = 600000000,
190 .bg_vref_level = 0xe,
194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
202 .frequency = 54000000,
214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
217 .frequency = 75000000,
229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
232 .frequency = 150000000,
238 .tx_pu_value = 0x66 /* 0 */,
243 .sparepll = 0x00, /* 0x34 */
244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
247 .frequency = 300000000,
259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
262 .frequency = 600000000,
274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
281 .frequency = 54000000,
293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
296 .frequency = 75000000,
308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
311 .frequency = 150000000,
317 .tx_pu_value = 0x66 /* 0 */,
322 .sparepll = 0x00, /* 0x34 */
323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
326 .frequency = 300000000,
338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
341 .frequency = 600000000,
353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
358 struct tegra_sor_regs {
359 unsigned int head_state0;
360 unsigned int head_state1;
361 unsigned int head_state2;
362 unsigned int head_state3;
363 unsigned int head_state4;
364 unsigned int head_state5;
369 unsigned int dp_padctl0;
370 unsigned int dp_padctl2;
373 struct tegra_sor_soc {
379 const struct tegra_sor_regs *regs;
382 const struct tegra_sor_hdmi_settings *settings;
383 unsigned int num_settings;
390 struct tegra_sor_ops {
392 int (*probe)(struct tegra_sor *sor);
393 int (*remove)(struct tegra_sor *sor);
397 struct host1x_client client;
398 struct tegra_output output;
401 const struct tegra_sor_soc *soc;
406 struct reset_control *rst;
407 struct clk *clk_parent;
408 struct clk *clk_safe;
414 struct drm_dp_aux *aux;
416 struct drm_info_list *debugfs_files;
418 const struct tegra_sor_ops *ops;
419 enum tegra_io_pad pad;
422 struct tegra_sor_hdmi_settings *settings;
423 unsigned int num_settings;
425 struct regulator *avdd_io_supply;
426 struct regulator *vdd_pll_supply;
427 struct regulator *hdmi_supply;
429 struct delayed_work scdc;
433 unsigned int sample_rate;
434 unsigned int channels;
438 struct tegra_sor_state {
439 struct drm_connector_state base;
441 unsigned int link_speed;
446 static inline struct tegra_sor_state *
447 to_sor_state(struct drm_connector_state *state)
449 return container_of(state, struct tegra_sor_state, base);
452 struct tegra_sor_config {
465 static inline struct tegra_sor *
466 host1x_client_to_sor(struct host1x_client *client)
468 return container_of(client, struct tegra_sor, client);
471 static inline struct tegra_sor *to_sor(struct tegra_output *output)
473 return container_of(output, struct tegra_sor, output);
476 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
478 u32 value = readl(sor->regs + (offset << 2));
480 trace_sor_readl(sor->dev, offset, value);
485 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
488 trace_sor_writel(sor->dev, offset, value);
489 writel(value, sor->regs + (offset << 2));
492 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
496 clk_disable_unprepare(sor->clk);
498 err = clk_set_parent(sor->clk_out, parent);
502 err = clk_prepare_enable(sor->clk);
509 struct tegra_clk_sor_pad {
511 struct tegra_sor *sor;
514 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
516 return container_of(hw, struct tegra_clk_sor_pad, hw);
519 static const char * const tegra_clk_sor_pad_parents[] = {
520 "pll_d2_out0", "pll_dp"
523 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
525 struct tegra_clk_sor_pad *pad = to_pad(hw);
526 struct tegra_sor *sor = pad->sor;
529 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
530 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
534 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
538 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
542 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
547 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
549 struct tegra_clk_sor_pad *pad = to_pad(hw);
550 struct tegra_sor *sor = pad->sor;
554 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
556 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
557 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
558 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
562 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
563 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
571 static const struct clk_ops tegra_clk_sor_pad_ops = {
572 .set_parent = tegra_clk_sor_pad_set_parent,
573 .get_parent = tegra_clk_sor_pad_get_parent,
576 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
579 struct tegra_clk_sor_pad *pad;
580 struct clk_init_data init;
583 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
585 return ERR_PTR(-ENOMEM);
591 init.parent_names = tegra_clk_sor_pad_parents;
592 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
593 init.ops = &tegra_clk_sor_pad_ops;
595 pad->hw.init = &init;
597 clk = devm_clk_register(sor->dev, &pad->hw);
602 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
603 struct drm_dp_link *link)
610 /* setup lane parameters */
611 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
612 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
613 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
614 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
615 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
617 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
618 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
619 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
620 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
621 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
623 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
624 SOR_LANE_POSTCURSOR_LANE2(0x00) |
625 SOR_LANE_POSTCURSOR_LANE1(0x00) |
626 SOR_LANE_POSTCURSOR_LANE0(0x00);
627 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
629 /* disable LVDS mode */
630 tegra_sor_writel(sor, 0, SOR_LVDS);
632 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
633 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
634 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
635 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
638 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
639 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
640 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
641 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
643 usleep_range(10, 100);
645 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
646 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
647 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
648 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
650 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
654 for (i = 0, value = 0; i < link->num_lanes; i++) {
655 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
656 SOR_DP_TPG_SCRAMBLER_NONE |
657 SOR_DP_TPG_PATTERN_TRAIN1;
658 value = (value << 8) | lane;
661 tegra_sor_writel(sor, value, SOR_DP_TPG);
663 pattern = DP_TRAINING_PATTERN_1;
665 err = drm_dp_aux_train(sor->aux, link, pattern);
669 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
670 value |= SOR_DP_SPARE_SEQ_ENABLE;
671 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
672 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
673 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
675 for (i = 0, value = 0; i < link->num_lanes; i++) {
676 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
677 SOR_DP_TPG_SCRAMBLER_NONE |
678 SOR_DP_TPG_PATTERN_TRAIN2;
679 value = (value << 8) | lane;
682 tegra_sor_writel(sor, value, SOR_DP_TPG);
684 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
686 err = drm_dp_aux_train(sor->aux, link, pattern);
690 for (i = 0, value = 0; i < link->num_lanes; i++) {
691 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
692 SOR_DP_TPG_SCRAMBLER_GALIOS |
693 SOR_DP_TPG_PATTERN_NONE;
694 value = (value << 8) | lane;
697 tegra_sor_writel(sor, value, SOR_DP_TPG);
699 pattern = DP_TRAINING_PATTERN_DISABLE;
701 err = drm_dp_aux_train(sor->aux, link, pattern);
708 static void tegra_sor_super_update(struct tegra_sor *sor)
710 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
711 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
712 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
715 static void tegra_sor_update(struct tegra_sor *sor)
717 tegra_sor_writel(sor, 0, SOR_STATE0);
718 tegra_sor_writel(sor, 1, SOR_STATE0);
719 tegra_sor_writel(sor, 0, SOR_STATE0);
722 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
726 value = tegra_sor_readl(sor, SOR_PWM_DIV);
727 value &= ~SOR_PWM_DIV_MASK;
728 value |= 0x400; /* period */
729 tegra_sor_writel(sor, value, SOR_PWM_DIV);
731 value = tegra_sor_readl(sor, SOR_PWM_CTL);
732 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
733 value |= 0x400; /* duty cycle */
734 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
735 value |= SOR_PWM_CTL_TRIGGER;
736 tegra_sor_writel(sor, value, SOR_PWM_CTL);
738 timeout = jiffies + msecs_to_jiffies(timeout);
740 while (time_before(jiffies, timeout)) {
741 value = tegra_sor_readl(sor, SOR_PWM_CTL);
742 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
745 usleep_range(25, 100);
751 static int tegra_sor_attach(struct tegra_sor *sor)
753 unsigned long value, timeout;
755 /* wake up in normal mode */
756 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
757 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
758 value |= SOR_SUPER_STATE_MODE_NORMAL;
759 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
760 tegra_sor_super_update(sor);
763 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
764 value |= SOR_SUPER_STATE_ATTACHED;
765 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
766 tegra_sor_super_update(sor);
768 timeout = jiffies + msecs_to_jiffies(250);
770 while (time_before(jiffies, timeout)) {
771 value = tegra_sor_readl(sor, SOR_TEST);
772 if ((value & SOR_TEST_ATTACHED) != 0)
775 usleep_range(25, 100);
781 static int tegra_sor_wakeup(struct tegra_sor *sor)
783 unsigned long value, timeout;
785 timeout = jiffies + msecs_to_jiffies(250);
787 /* wait for head to wake up */
788 while (time_before(jiffies, timeout)) {
789 value = tegra_sor_readl(sor, SOR_TEST);
790 value &= SOR_TEST_HEAD_MODE_MASK;
792 if (value == SOR_TEST_HEAD_MODE_AWAKE)
795 usleep_range(25, 100);
801 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
805 value = tegra_sor_readl(sor, SOR_PWR);
806 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
807 tegra_sor_writel(sor, value, SOR_PWR);
809 timeout = jiffies + msecs_to_jiffies(timeout);
811 while (time_before(jiffies, timeout)) {
812 value = tegra_sor_readl(sor, SOR_PWR);
813 if ((value & SOR_PWR_TRIGGER) == 0)
816 usleep_range(25, 100);
822 struct tegra_sor_params {
823 /* number of link clocks per line */
824 unsigned int num_clocks;
825 /* ratio between input and output */
827 /* precision factor */
830 unsigned int active_polarity;
831 unsigned int active_count;
832 unsigned int active_frac;
833 unsigned int tu_size;
837 static int tegra_sor_compute_params(struct tegra_sor *sor,
838 struct tegra_sor_params *params,
839 unsigned int tu_size)
841 u64 active_sym, active_count, frac, approx;
842 u32 active_polarity, active_frac = 0;
843 const u64 f = params->precision;
846 active_sym = params->ratio * tu_size;
847 active_count = div_u64(active_sym, f) * f;
848 frac = active_sym - active_count;
851 if (frac >= (f / 2)) {
859 frac = div_u64(f * f, frac); /* 1/fraction */
860 if (frac <= (15 * f)) {
861 active_frac = div_u64(frac, f);
867 active_frac = active_polarity ? 1 : 15;
871 if (active_frac == 1)
874 if (active_polarity == 1) {
876 approx = active_count + (active_frac * (f - 1)) * f;
877 approx = div_u64(approx, active_frac * f);
879 approx = active_count + f;
883 approx = active_count + div_u64(f, active_frac);
885 approx = active_count;
888 error = div_s64(active_sym - approx, tu_size);
889 error *= params->num_clocks;
891 if (error <= 0 && abs(error) < params->error) {
892 params->active_count = div_u64(active_count, f);
893 params->active_polarity = active_polarity;
894 params->active_frac = active_frac;
895 params->error = abs(error);
896 params->tu_size = tu_size;
905 static int tegra_sor_compute_config(struct tegra_sor *sor,
906 const struct drm_display_mode *mode,
907 struct tegra_sor_config *config,
908 struct drm_dp_link *link)
910 const u64 f = 100000, link_rate = link->rate * 1000;
911 const u64 pclk = mode->clock * 1000;
912 u64 input, output, watermark, num;
913 struct tegra_sor_params params;
914 u32 num_syms_per_line;
917 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
920 output = link_rate * 8 * link->num_lanes;
921 input = pclk * config->bits_per_pixel;
926 memset(¶ms, 0, sizeof(params));
927 params.ratio = div64_u64(input * f, output);
928 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
929 params.precision = f;
930 params.error = 64 * f;
933 for (i = params.tu_size; i >= 32; i--)
934 if (tegra_sor_compute_params(sor, ¶ms, i))
937 if (params.active_frac == 0) {
938 config->active_polarity = 0;
939 config->active_count = params.active_count;
941 if (!params.active_polarity)
942 config->active_count--;
944 config->tu_size = params.tu_size;
945 config->active_frac = 1;
947 config->active_polarity = params.active_polarity;
948 config->active_count = params.active_count;
949 config->active_frac = params.active_frac;
950 config->tu_size = params.tu_size;
954 "polarity: %d active count: %d tu size: %d active frac: %d\n",
955 config->active_polarity, config->active_count,
956 config->tu_size, config->active_frac);
958 watermark = params.ratio * config->tu_size * (f - params.ratio);
959 watermark = div_u64(watermark, f);
961 watermark = div_u64(watermark + params.error, f);
962 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
963 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
964 (link->num_lanes * 8);
966 if (config->watermark > 30) {
967 config->watermark = 30;
969 "unable to compute TU size, forcing watermark to %u\n",
971 } else if (config->watermark > num_syms_per_line) {
972 config->watermark = num_syms_per_line;
973 dev_err(sor->dev, "watermark too high, forcing to %u\n",
977 /* compute the number of symbols per horizontal blanking interval */
978 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
979 config->hblank_symbols = div_u64(num, pclk);
981 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
982 config->hblank_symbols -= 3;
984 config->hblank_symbols -= 12 / link->num_lanes;
986 /* compute the number of symbols per vertical blanking interval */
987 num = (mode->hdisplay - 25) * link_rate;
988 config->vblank_symbols = div_u64(num, pclk);
989 config->vblank_symbols -= 36 / link->num_lanes + 4;
991 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
992 config->vblank_symbols);
997 static void tegra_sor_apply_config(struct tegra_sor *sor,
998 const struct tegra_sor_config *config)
1002 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1003 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1004 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1005 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1007 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1008 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1009 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1011 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1012 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1014 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1015 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1017 if (config->active_polarity)
1018 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1020 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1022 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1023 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1024 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1026 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1027 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1028 value |= config->hblank_symbols & 0xffff;
1029 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1031 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1032 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1033 value |= config->vblank_symbols & 0xffff;
1034 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1037 static void tegra_sor_mode_set(struct tegra_sor *sor,
1038 const struct drm_display_mode *mode,
1039 struct tegra_sor_state *state)
1041 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1042 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1045 value = tegra_sor_readl(sor, SOR_STATE1);
1046 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1047 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1048 value &= ~SOR_STATE_ASY_OWNER_MASK;
1050 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1051 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1053 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1054 value &= ~SOR_STATE_ASY_HSYNCPOL;
1056 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1057 value |= SOR_STATE_ASY_HSYNCPOL;
1059 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1060 value &= ~SOR_STATE_ASY_VSYNCPOL;
1062 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1063 value |= SOR_STATE_ASY_VSYNCPOL;
1065 switch (state->bpc) {
1067 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1071 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1075 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1079 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1083 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1087 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1091 tegra_sor_writel(sor, value, SOR_STATE1);
1094 * TODO: The video timing programming below doesn't seem to match the
1095 * register definitions.
1098 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1099 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1101 /* sync end = sync width - 1 */
1102 vse = mode->vsync_end - mode->vsync_start - 1;
1103 hse = mode->hsync_end - mode->hsync_start - 1;
1105 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1106 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1108 /* blank end = sync end + back porch */
1109 vbe = vse + (mode->vtotal - mode->vsync_end);
1110 hbe = hse + (mode->htotal - mode->hsync_end);
1112 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1113 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1115 /* blank start = blank end + active */
1116 vbs = vbe + mode->vdisplay;
1117 hbs = hbe + mode->hdisplay;
1119 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1120 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1122 /* XXX interlacing support */
1123 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1126 static int tegra_sor_detach(struct tegra_sor *sor)
1128 unsigned long value, timeout;
1130 /* switch to safe mode */
1131 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1132 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1133 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1134 tegra_sor_super_update(sor);
1136 timeout = jiffies + msecs_to_jiffies(250);
1138 while (time_before(jiffies, timeout)) {
1139 value = tegra_sor_readl(sor, SOR_PWR);
1140 if (value & SOR_PWR_MODE_SAFE)
1144 if ((value & SOR_PWR_MODE_SAFE) == 0)
1148 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1149 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1150 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1151 tegra_sor_super_update(sor);
1154 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1155 value &= ~SOR_SUPER_STATE_ATTACHED;
1156 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1157 tegra_sor_super_update(sor);
1159 timeout = jiffies + msecs_to_jiffies(250);
1161 while (time_before(jiffies, timeout)) {
1162 value = tegra_sor_readl(sor, SOR_TEST);
1163 if ((value & SOR_TEST_ATTACHED) == 0)
1166 usleep_range(25, 100);
1169 if ((value & SOR_TEST_ATTACHED) != 0)
1175 static int tegra_sor_power_down(struct tegra_sor *sor)
1177 unsigned long value, timeout;
1180 value = tegra_sor_readl(sor, SOR_PWR);
1181 value &= ~SOR_PWR_NORMAL_STATE_PU;
1182 value |= SOR_PWR_TRIGGER;
1183 tegra_sor_writel(sor, value, SOR_PWR);
1185 timeout = jiffies + msecs_to_jiffies(250);
1187 while (time_before(jiffies, timeout)) {
1188 value = tegra_sor_readl(sor, SOR_PWR);
1189 if ((value & SOR_PWR_TRIGGER) == 0)
1192 usleep_range(25, 100);
1195 if ((value & SOR_PWR_TRIGGER) != 0)
1198 /* switch to safe parent clock */
1199 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1201 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1205 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1206 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1207 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1208 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1210 /* stop lane sequencer */
1211 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1212 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1213 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1215 timeout = jiffies + msecs_to_jiffies(250);
1217 while (time_before(jiffies, timeout)) {
1218 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1219 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1222 usleep_range(25, 100);
1225 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1228 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1229 value |= SOR_PLL2_PORT_POWERDOWN;
1230 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1232 usleep_range(20, 100);
1234 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1235 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1236 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1238 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1239 value |= SOR_PLL2_SEQ_PLLCAPPD;
1240 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1241 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1243 usleep_range(20, 100);
1248 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1252 timeout = jiffies + msecs_to_jiffies(timeout);
1254 while (time_before(jiffies, timeout)) {
1255 value = tegra_sor_readl(sor, SOR_CRCA);
1256 if (value & SOR_CRCA_VALID)
1259 usleep_range(100, 200);
1265 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1267 struct drm_info_node *node = s->private;
1268 struct tegra_sor *sor = node->info_ent->data;
1269 struct drm_crtc *crtc = sor->output.encoder.crtc;
1270 struct drm_device *drm = node->minor->dev;
1274 drm_modeset_lock_all(drm);
1276 if (!crtc || !crtc->state->active) {
1281 value = tegra_sor_readl(sor, SOR_STATE1);
1282 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1283 tegra_sor_writel(sor, value, SOR_STATE1);
1285 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1286 value |= SOR_CRC_CNTRL_ENABLE;
1287 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1289 value = tegra_sor_readl(sor, SOR_TEST);
1290 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1291 tegra_sor_writel(sor, value, SOR_TEST);
1293 err = tegra_sor_crc_wait(sor, 100);
1297 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1298 value = tegra_sor_readl(sor, SOR_CRCB);
1300 seq_printf(s, "%08x\n", value);
1303 drm_modeset_unlock_all(drm);
1307 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1309 static const struct debugfs_reg32 tegra_sor_regs[] = {
1310 DEBUGFS_REG32(SOR_CTXSW),
1311 DEBUGFS_REG32(SOR_SUPER_STATE0),
1312 DEBUGFS_REG32(SOR_SUPER_STATE1),
1313 DEBUGFS_REG32(SOR_STATE0),
1314 DEBUGFS_REG32(SOR_STATE1),
1315 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1316 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1317 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1318 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1319 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1320 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1321 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1322 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1323 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1324 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1325 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1326 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1327 DEBUGFS_REG32(SOR_CRC_CNTRL),
1328 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1329 DEBUGFS_REG32(SOR_CLK_CNTRL),
1330 DEBUGFS_REG32(SOR_CAP),
1331 DEBUGFS_REG32(SOR_PWR),
1332 DEBUGFS_REG32(SOR_TEST),
1333 DEBUGFS_REG32(SOR_PLL0),
1334 DEBUGFS_REG32(SOR_PLL1),
1335 DEBUGFS_REG32(SOR_PLL2),
1336 DEBUGFS_REG32(SOR_PLL3),
1337 DEBUGFS_REG32(SOR_CSTM),
1338 DEBUGFS_REG32(SOR_LVDS),
1339 DEBUGFS_REG32(SOR_CRCA),
1340 DEBUGFS_REG32(SOR_CRCB),
1341 DEBUGFS_REG32(SOR_BLANK),
1342 DEBUGFS_REG32(SOR_SEQ_CTL),
1343 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1344 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1345 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1346 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1347 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1348 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1349 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1350 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1351 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1352 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1353 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1354 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1355 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1356 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1357 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1358 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1359 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1360 DEBUGFS_REG32(SOR_PWM_DIV),
1361 DEBUGFS_REG32(SOR_PWM_CTL),
1362 DEBUGFS_REG32(SOR_VCRC_A0),
1363 DEBUGFS_REG32(SOR_VCRC_A1),
1364 DEBUGFS_REG32(SOR_VCRC_B0),
1365 DEBUGFS_REG32(SOR_VCRC_B1),
1366 DEBUGFS_REG32(SOR_CCRC_A0),
1367 DEBUGFS_REG32(SOR_CCRC_A1),
1368 DEBUGFS_REG32(SOR_CCRC_B0),
1369 DEBUGFS_REG32(SOR_CCRC_B1),
1370 DEBUGFS_REG32(SOR_EDATA_A0),
1371 DEBUGFS_REG32(SOR_EDATA_A1),
1372 DEBUGFS_REG32(SOR_EDATA_B0),
1373 DEBUGFS_REG32(SOR_EDATA_B1),
1374 DEBUGFS_REG32(SOR_COUNT_A0),
1375 DEBUGFS_REG32(SOR_COUNT_A1),
1376 DEBUGFS_REG32(SOR_COUNT_B0),
1377 DEBUGFS_REG32(SOR_COUNT_B1),
1378 DEBUGFS_REG32(SOR_DEBUG_A0),
1379 DEBUGFS_REG32(SOR_DEBUG_A1),
1380 DEBUGFS_REG32(SOR_DEBUG_B0),
1381 DEBUGFS_REG32(SOR_DEBUG_B1),
1382 DEBUGFS_REG32(SOR_TRIG),
1383 DEBUGFS_REG32(SOR_MSCHECK),
1384 DEBUGFS_REG32(SOR_XBAR_CTRL),
1385 DEBUGFS_REG32(SOR_XBAR_POL),
1386 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1387 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1388 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1389 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1390 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1391 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1392 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1393 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1394 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1395 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1396 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1397 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1398 DEBUGFS_REG32(SOR_DP_CONFIG0),
1399 DEBUGFS_REG32(SOR_DP_CONFIG1),
1400 DEBUGFS_REG32(SOR_DP_MN0),
1401 DEBUGFS_REG32(SOR_DP_MN1),
1402 DEBUGFS_REG32(SOR_DP_PADCTL0),
1403 DEBUGFS_REG32(SOR_DP_PADCTL1),
1404 DEBUGFS_REG32(SOR_DP_PADCTL2),
1405 DEBUGFS_REG32(SOR_DP_DEBUG0),
1406 DEBUGFS_REG32(SOR_DP_DEBUG1),
1407 DEBUGFS_REG32(SOR_DP_SPARE0),
1408 DEBUGFS_REG32(SOR_DP_SPARE1),
1409 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1410 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1411 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1415 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1416 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1417 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1418 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1419 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1420 DEBUGFS_REG32(SOR_DP_TPG),
1421 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1422 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1423 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1424 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1427 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1429 struct drm_info_node *node = s->private;
1430 struct tegra_sor *sor = node->info_ent->data;
1431 struct drm_crtc *crtc = sor->output.encoder.crtc;
1432 struct drm_device *drm = node->minor->dev;
1436 drm_modeset_lock_all(drm);
1438 if (!crtc || !crtc->state->active) {
1443 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1444 unsigned int offset = tegra_sor_regs[i].offset;
1446 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1447 offset, tegra_sor_readl(sor, offset));
1451 drm_modeset_unlock_all(drm);
1455 static const struct drm_info_list debugfs_files[] = {
1456 { "crc", tegra_sor_show_crc, 0, NULL },
1457 { "regs", tegra_sor_show_regs, 0, NULL },
1460 static int tegra_sor_late_register(struct drm_connector *connector)
1462 struct tegra_output *output = connector_to_output(connector);
1463 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1464 struct drm_minor *minor = connector->dev->primary;
1465 struct dentry *root = connector->debugfs_entry;
1466 struct tegra_sor *sor = to_sor(output);
1469 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1471 if (!sor->debugfs_files)
1474 for (i = 0; i < count; i++)
1475 sor->debugfs_files[i].data = sor;
1477 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1484 kfree(sor->debugfs_files);
1485 sor->debugfs_files = NULL;
1490 static void tegra_sor_early_unregister(struct drm_connector *connector)
1492 struct tegra_output *output = connector_to_output(connector);
1493 unsigned int count = ARRAY_SIZE(debugfs_files);
1494 struct tegra_sor *sor = to_sor(output);
1496 drm_debugfs_remove_files(sor->debugfs_files, count,
1497 connector->dev->primary);
1498 kfree(sor->debugfs_files);
1499 sor->debugfs_files = NULL;
1502 static void tegra_sor_connector_reset(struct drm_connector *connector)
1504 struct tegra_sor_state *state;
1506 state = kzalloc(sizeof(*state), GFP_KERNEL);
1510 if (connector->state) {
1511 __drm_atomic_helper_connector_destroy_state(connector->state);
1512 kfree(connector->state);
1515 __drm_atomic_helper_connector_reset(connector, &state->base);
1518 static enum drm_connector_status
1519 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1521 struct tegra_output *output = connector_to_output(connector);
1522 struct tegra_sor *sor = to_sor(output);
1525 return drm_dp_aux_detect(sor->aux);
1527 return tegra_output_connector_detect(connector, force);
1530 static struct drm_connector_state *
1531 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1533 struct tegra_sor_state *state = to_sor_state(connector->state);
1534 struct tegra_sor_state *copy;
1536 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1540 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1545 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1546 .reset = tegra_sor_connector_reset,
1547 .detect = tegra_sor_connector_detect,
1548 .fill_modes = drm_helper_probe_single_connector_modes,
1549 .destroy = tegra_output_connector_destroy,
1550 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1551 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1552 .late_register = tegra_sor_late_register,
1553 .early_unregister = tegra_sor_early_unregister,
1556 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1558 struct tegra_output *output = connector_to_output(connector);
1559 struct tegra_sor *sor = to_sor(output);
1563 drm_dp_aux_enable(sor->aux);
1565 err = tegra_output_connector_get_modes(connector);
1568 drm_dp_aux_disable(sor->aux);
1573 static enum drm_mode_status
1574 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1575 struct drm_display_mode *mode)
1580 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1581 .get_modes = tegra_sor_connector_get_modes,
1582 .mode_valid = tegra_sor_connector_mode_valid,
1585 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1586 .destroy = tegra_output_encoder_destroy,
1589 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1591 struct tegra_output *output = encoder_to_output(encoder);
1592 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1593 struct tegra_sor *sor = to_sor(output);
1598 drm_panel_disable(output->panel);
1600 err = tegra_sor_detach(sor);
1602 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1604 tegra_sor_writel(sor, 0, SOR_STATE1);
1605 tegra_sor_update(sor);
1608 * The following accesses registers of the display controller, so make
1609 * sure it's only executed when the output is attached to one.
1612 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1613 value &= ~SOR_ENABLE(0);
1614 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1616 tegra_dc_commit(dc);
1619 err = tegra_sor_power_down(sor);
1621 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1624 err = drm_dp_aux_disable(sor->aux);
1626 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1629 err = tegra_io_pad_power_disable(sor->pad);
1631 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1634 drm_panel_unprepare(output->panel);
1636 pm_runtime_put(sor->dev);
1640 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1641 unsigned int *value)
1643 unsigned int hfp, hsw, hbp, a = 0, b;
1645 hfp = mode->hsync_start - mode->hdisplay;
1646 hsw = mode->hsync_end - mode->hsync_start;
1647 hbp = mode->htotal - mode->hsync_end;
1649 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1653 pr_info("a: %u, b: %u\n", a, b);
1654 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1656 if (a + hsw + hbp <= 11) {
1657 a = 1 + 11 - hsw - hbp;
1658 pr_info("a: %u\n", a);
1667 if (mode->hdisplay < 16)
1681 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1683 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1684 struct tegra_output *output = encoder_to_output(encoder);
1685 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1686 struct tegra_sor *sor = to_sor(output);
1687 struct tegra_sor_config config;
1688 struct tegra_sor_state *state;
1689 struct drm_dp_link link;
1695 state = to_sor_state(output->connector.state);
1697 pm_runtime_get_sync(sor->dev);
1700 drm_panel_prepare(output->panel);
1702 err = drm_dp_aux_enable(sor->aux);
1704 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1706 err = drm_dp_link_probe(sor->aux, &link);
1708 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1712 /* switch to safe parent clock */
1713 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1715 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1717 memset(&config, 0, sizeof(config));
1718 config.bits_per_pixel = state->bpc * 3;
1720 err = tegra_sor_compute_config(sor, mode, &config, &link);
1722 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1724 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1725 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1726 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1727 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1730 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1732 usleep_range(20, 100);
1734 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1735 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1736 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1738 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1739 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1740 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1742 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1743 value |= SOR_PLL2_SEQ_PLLCAPPD;
1744 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1745 value |= SOR_PLL2_LVDS_ENABLE;
1746 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1748 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1749 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1752 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1753 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1756 usleep_range(250, 1000);
1759 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1760 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1761 value &= ~SOR_PLL2_PORT_POWERDOWN;
1762 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1768 /* set safe link bandwidth (1.62 Gbps) */
1769 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1770 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1771 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1772 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1775 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1776 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1777 SOR_PLL2_BANDGAP_POWERDOWN;
1778 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1780 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1781 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1782 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1784 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1785 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1786 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1789 err = tegra_io_pad_power_enable(sor->pad);
1791 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1793 usleep_range(5, 100);
1796 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1797 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1798 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1800 usleep_range(20, 100);
1803 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1804 value &= ~SOR_PLL0_VCOPD;
1805 value &= ~SOR_PLL0_PWR;
1806 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1808 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1809 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1810 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1812 usleep_range(200, 1000);
1815 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1816 value &= ~SOR_PLL2_PORT_POWERDOWN;
1817 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1819 /* XXX not in TRM */
1820 for (value = 0, i = 0; i < 5; i++)
1821 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1822 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1824 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1825 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1827 /* switch to DP parent clock */
1828 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1830 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1832 /* power DP lanes */
1833 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1835 if (link.num_lanes <= 2)
1836 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1838 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1840 if (link.num_lanes <= 1)
1841 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1843 value |= SOR_DP_PADCTL_PD_TXD_1;
1845 if (link.num_lanes == 0)
1846 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1848 value |= SOR_DP_PADCTL_PD_TXD_0;
1850 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1852 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1853 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1854 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1855 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1857 /* start lane sequencer */
1858 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1859 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1860 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1863 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1864 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1867 usleep_range(250, 1000);
1870 /* set link bandwidth */
1871 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1872 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1873 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1876 tegra_sor_apply_config(sor, &config);
1879 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1880 value |= SOR_DP_LINKCTL_ENABLE;
1881 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1882 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1884 for (i = 0, value = 0; i < 4; i++) {
1885 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1886 SOR_DP_TPG_SCRAMBLER_GALIOS |
1887 SOR_DP_TPG_PATTERN_NONE;
1888 value = (value << 8) | lane;
1891 tegra_sor_writel(sor, value, SOR_DP_TPG);
1893 /* enable pad calibration logic */
1894 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1895 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1896 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1898 err = drm_dp_link_probe(sor->aux, &link);
1900 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1902 err = drm_dp_link_power_up(sor->aux, &link);
1904 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1906 err = drm_dp_link_configure(sor->aux, &link);
1908 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1910 rate = drm_dp_link_rate_to_bw_code(link.rate);
1911 lanes = link.num_lanes;
1913 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1914 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1915 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1916 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1918 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1919 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1920 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1922 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1923 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1925 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1927 /* disable training pattern generator */
1929 for (i = 0; i < link.num_lanes; i++) {
1930 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1931 SOR_DP_TPG_SCRAMBLER_GALIOS |
1932 SOR_DP_TPG_PATTERN_NONE;
1933 value = (value << 8) | lane;
1936 tegra_sor_writel(sor, value, SOR_DP_TPG);
1938 err = tegra_sor_dp_train_fast(sor, &link);
1940 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1942 dev_dbg(sor->dev, "fast link training succeeded\n");
1944 err = tegra_sor_power_up(sor, 250);
1946 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1948 /* CSTM (LVDS, link A/B, upper) */
1949 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1951 tegra_sor_writel(sor, value, SOR_CSTM);
1953 /* use DP-A protocol */
1954 value = tegra_sor_readl(sor, SOR_STATE1);
1955 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1956 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1957 tegra_sor_writel(sor, value, SOR_STATE1);
1959 tegra_sor_mode_set(sor, mode, state);
1962 err = tegra_sor_setup_pwm(sor, 250);
1964 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1966 tegra_sor_update(sor);
1968 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1969 value |= SOR_ENABLE(0);
1970 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1972 tegra_dc_commit(dc);
1974 err = tegra_sor_attach(sor);
1976 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1978 err = tegra_sor_wakeup(sor);
1980 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1983 drm_panel_enable(output->panel);
1987 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1988 struct drm_crtc_state *crtc_state,
1989 struct drm_connector_state *conn_state)
1991 struct tegra_output *output = encoder_to_output(encoder);
1992 struct tegra_sor_state *state = to_sor_state(conn_state);
1993 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1994 unsigned long pclk = crtc_state->mode.clock * 1000;
1995 struct tegra_sor *sor = to_sor(output);
1996 struct drm_display_info *info;
1999 info = &output->connector.display_info;
2002 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2003 * the pixel clock must be corrected accordingly.
2005 if (pclk >= 340000000) {
2006 state->link_speed = 20;
2007 state->pclk = pclk / 2;
2009 state->link_speed = 10;
2013 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2016 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2020 switch (info->bpc) {
2023 state->bpc = info->bpc;
2027 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2035 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2036 .disable = tegra_sor_edp_disable,
2037 .enable = tegra_sor_edp_enable,
2038 .atomic_check = tegra_sor_encoder_atomic_check,
2041 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2046 for (i = size; i > 0; i--)
2047 value = (value << 8) | ptr[i - 1];
2052 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2053 const void *data, size_t size)
2055 const u8 *ptr = data;
2056 unsigned long offset;
2061 case HDMI_INFOFRAME_TYPE_AVI:
2062 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2065 case HDMI_INFOFRAME_TYPE_AUDIO:
2066 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2069 case HDMI_INFOFRAME_TYPE_VENDOR:
2070 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2074 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2079 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2080 INFOFRAME_HEADER_VERSION(ptr[1]) |
2081 INFOFRAME_HEADER_LEN(ptr[2]);
2082 tegra_sor_writel(sor, value, offset);
2086 * Each subpack contains 7 bytes, divided into:
2087 * - subpack_low: bytes 0 - 3
2088 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2090 for (i = 3, j = 0; i < size; i += 7, j += 8) {
2091 size_t rem = size - i, num = min_t(size_t, rem, 4);
2093 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2094 tegra_sor_writel(sor, value, offset++);
2096 num = min_t(size_t, rem - num, 3);
2098 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2099 tegra_sor_writel(sor, value, offset++);
2104 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2105 const struct drm_display_mode *mode)
2107 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2108 struct hdmi_avi_infoframe frame;
2112 /* disable AVI infoframe */
2113 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2114 value &= ~INFOFRAME_CTRL_SINGLE;
2115 value &= ~INFOFRAME_CTRL_OTHER;
2116 value &= ~INFOFRAME_CTRL_ENABLE;
2117 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2119 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2120 &sor->output.connector, mode);
2122 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2126 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2128 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2132 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2134 /* enable AVI infoframe */
2135 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2136 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2137 value |= INFOFRAME_CTRL_ENABLE;
2138 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2143 static void tegra_sor_write_eld(struct tegra_sor *sor)
2145 size_t length = drm_eld_size(sor->output.connector.eld), i;
2147 for (i = 0; i < length; i++)
2148 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2149 SOR_AUDIO_HDA_ELD_BUFWR);
2152 * The HDA codec will always report an ELD buffer size of 96 bytes and
2153 * the HDA codec driver will check that each byte read from the buffer
2154 * is valid. Therefore every byte must be written, even if no 96 bytes
2155 * were parsed from EDID.
2157 for (i = length; i < 96; i++)
2158 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2161 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2165 tegra_sor_write_eld(sor);
2167 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2168 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2171 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2173 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2176 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2178 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2179 struct hdmi_audio_infoframe frame;
2183 err = hdmi_audio_infoframe_init(&frame);
2185 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2189 frame.channels = sor->audio.channels;
2191 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2193 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2197 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2199 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2200 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2201 value |= INFOFRAME_CTRL_ENABLE;
2202 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2207 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2211 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2213 /* select HDA audio input */
2214 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2215 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2217 /* inject null samples */
2218 if (sor->audio.channels != 2)
2219 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2221 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2223 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2225 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2227 /* enable advertising HBR capability */
2228 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2230 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2232 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2233 SOR_HDMI_SPARE_CTS_RESET(1) |
2234 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2235 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2238 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2239 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2241 /* allow packet to be sent */
2242 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2243 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2245 /* reset N counter and enable lookup */
2246 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2247 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2249 value = (24000 * 4096) / (128 * sor->audio.sample_rate / 1000);
2250 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2251 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2253 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2254 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2256 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2257 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2259 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2260 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2262 value = (24000 * 6144) / (128 * sor->audio.sample_rate / 1000);
2263 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2264 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2266 value = (24000 * 12288) / (128 * sor->audio.sample_rate / 1000);
2267 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2268 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2270 value = (24000 * 24576) / (128 * sor->audio.sample_rate / 1000);
2271 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2272 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2274 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2275 value &= ~SOR_HDMI_AUDIO_N_RESET;
2276 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2278 tegra_sor_hdmi_enable_audio_infoframe(sor);
2281 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2285 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2286 value &= ~INFOFRAME_CTRL_ENABLE;
2287 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2290 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2292 tegra_sor_hdmi_disable_audio_infoframe(sor);
2295 static struct tegra_sor_hdmi_settings *
2296 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2300 for (i = 0; i < sor->num_settings; i++)
2301 if (frequency <= sor->settings[i].frequency)
2302 return &sor->settings[i];
2307 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2311 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2312 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2313 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2314 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2317 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2319 struct i2c_adapter *ddc = sor->output.ddc;
2321 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2322 drm_scdc_set_scrambling(ddc, false);
2324 tegra_sor_hdmi_disable_scrambling(sor);
2327 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2329 if (sor->scdc_enabled) {
2330 cancel_delayed_work_sync(&sor->scdc);
2331 tegra_sor_hdmi_scdc_disable(sor);
2335 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2339 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2340 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2341 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2342 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2345 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2347 struct i2c_adapter *ddc = sor->output.ddc;
2349 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2350 drm_scdc_set_scrambling(ddc, true);
2352 tegra_sor_hdmi_enable_scrambling(sor);
2355 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2357 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2358 struct i2c_adapter *ddc = sor->output.ddc;
2360 if (!drm_scdc_get_scrambling_status(ddc)) {
2361 DRM_DEBUG_KMS("SCDC not scrambled\n");
2362 tegra_sor_hdmi_scdc_enable(sor);
2365 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2368 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2370 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2371 struct drm_display_mode *mode;
2373 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2375 if (mode->clock >= 340000 && scdc->supported) {
2376 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2377 tegra_sor_hdmi_scdc_enable(sor);
2378 sor->scdc_enabled = true;
2382 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2384 struct tegra_output *output = encoder_to_output(encoder);
2385 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2386 struct tegra_sor *sor = to_sor(output);
2390 tegra_sor_audio_unprepare(sor);
2391 tegra_sor_hdmi_scdc_stop(sor);
2393 err = tegra_sor_detach(sor);
2395 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2397 tegra_sor_writel(sor, 0, SOR_STATE1);
2398 tegra_sor_update(sor);
2400 /* disable display to SOR clock */
2401 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2403 if (!sor->soc->has_nvdisplay)
2404 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2406 value &= ~SOR_ENABLE(sor->index);
2408 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2410 tegra_dc_commit(dc);
2412 err = tegra_sor_power_down(sor);
2414 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2416 err = tegra_io_pad_power_disable(sor->pad);
2418 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2420 pm_runtime_put(sor->dev);
2423 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2425 struct tegra_output *output = encoder_to_output(encoder);
2426 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2427 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2428 struct tegra_sor_hdmi_settings *settings;
2429 struct tegra_sor *sor = to_sor(output);
2430 struct tegra_sor_state *state;
2431 struct drm_display_mode *mode;
2432 unsigned long rate, pclk;
2433 unsigned int div, i;
2437 state = to_sor_state(output->connector.state);
2438 mode = &encoder->crtc->state->adjusted_mode;
2439 pclk = mode->clock * 1000;
2441 pm_runtime_get_sync(sor->dev);
2443 /* switch to safe parent clock */
2444 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2446 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2450 div = clk_get_rate(sor->clk) / 1000000 * 4;
2452 err = tegra_io_pad_power_enable(sor->pad);
2454 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2456 usleep_range(20, 100);
2458 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2459 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2460 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2462 usleep_range(20, 100);
2464 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2465 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2466 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2468 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2469 value &= ~SOR_PLL0_VCOPD;
2470 value &= ~SOR_PLL0_PWR;
2471 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2473 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2474 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2475 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2477 usleep_range(200, 400);
2479 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2480 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2481 value &= ~SOR_PLL2_PORT_POWERDOWN;
2482 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2484 usleep_range(20, 100);
2486 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2487 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2488 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2489 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2492 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2493 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2496 usleep_range(250, 1000);
2499 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2500 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2501 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2504 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2505 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2508 usleep_range(250, 1000);
2511 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2512 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2513 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2515 if (mode->clock < 340000) {
2516 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2517 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2519 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2520 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2523 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2524 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2526 /* SOR pad PLL stabilization time */
2527 usleep_range(250, 1000);
2529 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2530 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2531 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2532 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2534 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2535 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2536 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2537 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2538 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2539 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2541 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2542 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2543 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2545 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2546 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2547 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2548 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2550 if (!sor->soc->has_nvdisplay) {
2551 /* program the reference clock */
2552 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2553 tegra_sor_writel(sor, value, SOR_REFCLK);
2556 /* XXX not in TRM */
2557 for (value = 0, i = 0; i < 5; i++)
2558 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2559 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2561 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2562 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2564 /* switch to parent clock */
2565 err = clk_set_parent(sor->clk, sor->clk_parent);
2567 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2571 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2573 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2577 /* adjust clock rate for HDMI 2.0 modes */
2578 rate = clk_get_rate(sor->clk_parent);
2580 if (mode->clock >= 340000)
2583 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2585 clk_set_rate(sor->clk, rate);
2587 if (!sor->soc->has_nvdisplay) {
2588 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2590 /* XXX is this the proper check? */
2591 if (mode->clock < 75000)
2592 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2594 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2597 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2599 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2600 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2601 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2603 if (!dc->soc->has_nvdisplay) {
2604 /* H_PULSE2 setup */
2605 pulse_start = h_ref_to_sync +
2606 (mode->hsync_end - mode->hsync_start) +
2607 (mode->htotal - mode->hsync_end) - 10;
2609 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2610 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2611 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2613 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2614 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2616 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2617 value |= H_PULSE2_ENABLE;
2618 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2621 /* infoframe setup */
2622 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2624 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2626 /* XXX HDMI audio support not implemented yet */
2627 tegra_sor_hdmi_disable_audio_infoframe(sor);
2629 /* use single TMDS protocol */
2630 value = tegra_sor_readl(sor, SOR_STATE1);
2631 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2632 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2633 tegra_sor_writel(sor, value, SOR_STATE1);
2635 /* power up pad calibration */
2636 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2637 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2638 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2640 /* production settings */
2641 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2643 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2644 mode->clock * 1000);
2648 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2649 value &= ~SOR_PLL0_ICHPMP_MASK;
2650 value &= ~SOR_PLL0_FILTER_MASK;
2651 value &= ~SOR_PLL0_VCOCAP_MASK;
2652 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2653 value |= SOR_PLL0_FILTER(settings->filter);
2654 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2655 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2657 /* XXX not in TRM */
2658 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2659 value &= ~SOR_PLL1_LOADADJ_MASK;
2660 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2661 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2662 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2663 value |= SOR_PLL1_TMDS_TERM;
2664 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2666 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2667 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2668 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2669 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2670 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2671 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2672 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2673 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2674 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2675 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2677 value = settings->drive_current[3] << 24 |
2678 settings->drive_current[2] << 16 |
2679 settings->drive_current[1] << 8 |
2680 settings->drive_current[0] << 0;
2681 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2683 value = settings->preemphasis[3] << 24 |
2684 settings->preemphasis[2] << 16 |
2685 settings->preemphasis[1] << 8 |
2686 settings->preemphasis[0] << 0;
2687 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2689 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2690 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2691 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2692 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2693 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2695 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2696 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2697 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2698 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2700 /* power down pad calibration */
2701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2702 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2705 if (!dc->soc->has_nvdisplay) {
2706 /* miscellaneous display controller settings */
2707 value = VSYNC_H_POSITION(1);
2708 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2711 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2712 value &= ~DITHER_CONTROL_MASK;
2713 value &= ~BASE_COLOR_SIZE_MASK;
2715 switch (state->bpc) {
2717 value |= BASE_COLOR_SIZE_666;
2721 value |= BASE_COLOR_SIZE_888;
2725 value |= BASE_COLOR_SIZE_101010;
2729 value |= BASE_COLOR_SIZE_121212;
2733 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2734 value |= BASE_COLOR_SIZE_888;
2738 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2740 /* XXX set display head owner */
2741 value = tegra_sor_readl(sor, SOR_STATE1);
2742 value &= ~SOR_STATE_ASY_OWNER_MASK;
2743 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2744 tegra_sor_writel(sor, value, SOR_STATE1);
2746 err = tegra_sor_power_up(sor, 250);
2748 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2750 /* configure dynamic range of output */
2751 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2752 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2753 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2754 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2756 /* configure colorspace */
2757 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2758 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2759 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2760 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2762 tegra_sor_mode_set(sor, mode, state);
2764 tegra_sor_update(sor);
2766 /* program preamble timing in SOR (XXX) */
2767 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2768 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2769 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2771 err = tegra_sor_attach(sor);
2773 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2775 /* enable display to SOR clock and generate HDMI preamble */
2776 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2778 if (!sor->soc->has_nvdisplay)
2779 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2781 value |= SOR_ENABLE(sor->index);
2783 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2785 if (dc->soc->has_nvdisplay) {
2786 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2787 value &= ~PROTOCOL_MASK;
2788 value |= PROTOCOL_SINGLE_TMDS_A;
2789 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2792 tegra_dc_commit(dc);
2794 err = tegra_sor_wakeup(sor);
2796 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2798 tegra_sor_hdmi_scdc_start(sor);
2799 tegra_sor_audio_prepare(sor);
2802 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2803 .disable = tegra_sor_hdmi_disable,
2804 .enable = tegra_sor_hdmi_enable,
2805 .atomic_check = tegra_sor_encoder_atomic_check,
2808 static int tegra_sor_init(struct host1x_client *client)
2810 struct drm_device *drm = dev_get_drvdata(client->parent);
2811 const struct drm_encoder_helper_funcs *helpers = NULL;
2812 struct tegra_sor *sor = host1x_client_to_sor(client);
2813 int connector = DRM_MODE_CONNECTOR_Unknown;
2814 int encoder = DRM_MODE_ENCODER_NONE;
2819 if (sor->soc->supports_hdmi) {
2820 connector = DRM_MODE_CONNECTOR_HDMIA;
2821 encoder = DRM_MODE_ENCODER_TMDS;
2822 helpers = &tegra_sor_hdmi_helpers;
2823 } else if (sor->soc->supports_lvds) {
2824 connector = DRM_MODE_CONNECTOR_LVDS;
2825 encoder = DRM_MODE_ENCODER_LVDS;
2828 if (sor->soc->supports_edp) {
2829 connector = DRM_MODE_CONNECTOR_eDP;
2830 encoder = DRM_MODE_ENCODER_TMDS;
2831 helpers = &tegra_sor_edp_helpers;
2832 } else if (sor->soc->supports_dp) {
2833 connector = DRM_MODE_CONNECTOR_DisplayPort;
2834 encoder = DRM_MODE_ENCODER_TMDS;
2838 sor->output.dev = sor->dev;
2840 drm_connector_init(drm, &sor->output.connector,
2841 &tegra_sor_connector_funcs,
2843 drm_connector_helper_add(&sor->output.connector,
2844 &tegra_sor_connector_helper_funcs);
2845 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2847 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2849 drm_encoder_helper_add(&sor->output.encoder, helpers);
2851 drm_connector_attach_encoder(&sor->output.connector,
2852 &sor->output.encoder);
2853 drm_connector_register(&sor->output.connector);
2855 err = tegra_output_init(drm, &sor->output);
2857 dev_err(client->dev, "failed to initialize output: %d\n", err);
2861 tegra_output_find_possible_crtcs(&sor->output, drm);
2864 err = drm_dp_aux_attach(sor->aux, &sor->output);
2866 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2872 * XXX: Remove this reset once proper hand-over from firmware to
2873 * kernel is possible.
2876 err = reset_control_assert(sor->rst);
2878 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2884 err = clk_prepare_enable(sor->clk);
2886 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2890 usleep_range(1000, 3000);
2893 err = reset_control_deassert(sor->rst);
2895 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2901 err = clk_prepare_enable(sor->clk_safe);
2905 err = clk_prepare_enable(sor->clk_dp);
2910 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2911 * is used for interoperability between the HDA codec driver and the
2914 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2915 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2916 tegra_sor_writel(sor, value, SOR_INT_MASK);
2921 static int tegra_sor_exit(struct host1x_client *client)
2923 struct tegra_sor *sor = host1x_client_to_sor(client);
2926 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2927 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2929 tegra_output_exit(&sor->output);
2932 err = drm_dp_aux_detach(sor->aux);
2934 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2939 clk_disable_unprepare(sor->clk_safe);
2940 clk_disable_unprepare(sor->clk_dp);
2941 clk_disable_unprepare(sor->clk);
2946 static const struct host1x_client_ops sor_client_ops = {
2947 .init = tegra_sor_init,
2948 .exit = tegra_sor_exit,
2951 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2955 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2959 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2960 if (IS_ERR(sor->avdd_io_supply)) {
2961 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2962 PTR_ERR(sor->avdd_io_supply));
2963 return PTR_ERR(sor->avdd_io_supply);
2966 err = regulator_enable(sor->avdd_io_supply);
2968 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2973 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2974 if (IS_ERR(sor->vdd_pll_supply)) {
2975 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2976 PTR_ERR(sor->vdd_pll_supply));
2977 return PTR_ERR(sor->vdd_pll_supply);
2980 err = regulator_enable(sor->vdd_pll_supply);
2982 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2987 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2988 if (IS_ERR(sor->hdmi_supply)) {
2989 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2990 PTR_ERR(sor->hdmi_supply));
2991 return PTR_ERR(sor->hdmi_supply);
2994 err = regulator_enable(sor->hdmi_supply);
2996 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3000 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3005 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3007 regulator_disable(sor->hdmi_supply);
3008 regulator_disable(sor->vdd_pll_supply);
3009 regulator_disable(sor->avdd_io_supply);
3014 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3016 .probe = tegra_sor_hdmi_probe,
3017 .remove = tegra_sor_hdmi_remove,
3020 static const u8 tegra124_sor_xbar_cfg[5] = {
3024 static const struct tegra_sor_regs tegra124_sor_regs = {
3025 .head_state0 = 0x05,
3026 .head_state1 = 0x07,
3027 .head_state2 = 0x09,
3028 .head_state3 = 0x0b,
3029 .head_state4 = 0x0d,
3030 .head_state5 = 0x0f,
3039 static const struct tegra_sor_soc tegra124_sor = {
3040 .supports_edp = true,
3041 .supports_lvds = true,
3042 .supports_hdmi = false,
3043 .supports_dp = false,
3044 .regs = &tegra124_sor_regs,
3045 .has_nvdisplay = false,
3046 .xbar_cfg = tegra124_sor_xbar_cfg,
3049 static const struct tegra_sor_regs tegra210_sor_regs = {
3050 .head_state0 = 0x05,
3051 .head_state1 = 0x07,
3052 .head_state2 = 0x09,
3053 .head_state3 = 0x0b,
3054 .head_state4 = 0x0d,
3055 .head_state5 = 0x0f,
3064 static const struct tegra_sor_soc tegra210_sor = {
3065 .supports_edp = true,
3066 .supports_lvds = false,
3067 .supports_hdmi = false,
3068 .supports_dp = false,
3069 .regs = &tegra210_sor_regs,
3070 .has_nvdisplay = false,
3071 .xbar_cfg = tegra124_sor_xbar_cfg,
3074 static const u8 tegra210_sor_xbar_cfg[5] = {
3078 static const struct tegra_sor_soc tegra210_sor1 = {
3079 .supports_edp = false,
3080 .supports_lvds = false,
3081 .supports_hdmi = true,
3082 .supports_dp = true,
3084 .regs = &tegra210_sor_regs,
3085 .has_nvdisplay = false,
3087 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3088 .settings = tegra210_sor_hdmi_defaults,
3090 .xbar_cfg = tegra210_sor_xbar_cfg,
3093 static const struct tegra_sor_regs tegra186_sor_regs = {
3094 .head_state0 = 0x151,
3095 .head_state1 = 0x154,
3096 .head_state2 = 0x157,
3097 .head_state3 = 0x15a,
3098 .head_state4 = 0x15d,
3099 .head_state5 = 0x160,
3104 .dp_padctl0 = 0x168,
3105 .dp_padctl2 = 0x16a,
3108 static const struct tegra_sor_soc tegra186_sor = {
3109 .supports_edp = false,
3110 .supports_lvds = false,
3111 .supports_hdmi = false,
3112 .supports_dp = true,
3114 .regs = &tegra186_sor_regs,
3115 .has_nvdisplay = true,
3117 .xbar_cfg = tegra124_sor_xbar_cfg,
3120 static const struct tegra_sor_soc tegra186_sor1 = {
3121 .supports_edp = false,
3122 .supports_lvds = false,
3123 .supports_hdmi = true,
3124 .supports_dp = true,
3126 .regs = &tegra186_sor_regs,
3127 .has_nvdisplay = true,
3129 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3130 .settings = tegra186_sor_hdmi_defaults,
3132 .xbar_cfg = tegra124_sor_xbar_cfg,
3135 static const struct tegra_sor_regs tegra194_sor_regs = {
3136 .head_state0 = 0x151,
3137 .head_state1 = 0x155,
3138 .head_state2 = 0x159,
3139 .head_state3 = 0x15d,
3140 .head_state4 = 0x161,
3141 .head_state5 = 0x165,
3146 .dp_padctl0 = 0x16e,
3147 .dp_padctl2 = 0x16f,
3150 static const struct tegra_sor_soc tegra194_sor = {
3151 .supports_edp = true,
3152 .supports_lvds = false,
3153 .supports_hdmi = true,
3154 .supports_dp = true,
3156 .regs = &tegra194_sor_regs,
3157 .has_nvdisplay = true,
3159 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3160 .settings = tegra194_sor_hdmi_defaults,
3162 .xbar_cfg = tegra210_sor_xbar_cfg,
3165 static const struct of_device_id tegra_sor_of_match[] = {
3166 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3167 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3168 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3169 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3170 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3171 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3174 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3176 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3178 struct device_node *np = sor->dev->of_node;
3182 if (sor->soc->has_nvdisplay) {
3183 err = of_property_read_u32(np, "nvidia,interface", &value);
3190 * override the default that we already set for Tegra210 and
3193 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3199 static void tegra_hda_parse_format(unsigned int format, unsigned int *rate,
3200 unsigned int *channels)
3202 unsigned int mul, div;
3204 if (format & AC_FMT_BASE_44K)
3209 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
3210 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
3212 *rate = *rate * (mul + 1) / (div + 1);
3214 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
3217 static irqreturn_t tegra_sor_irq(int irq, void *data)
3219 struct tegra_sor *sor = data;
3222 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3223 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3225 if (value & SOR_INT_CODEC_SCRATCH0) {
3226 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3228 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3229 unsigned int format, sample_rate, channels;
3231 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3233 tegra_hda_parse_format(format, &sample_rate, &channels);
3235 sor->audio.sample_rate = sample_rate;
3236 sor->audio.channels = channels;
3238 tegra_sor_hdmi_audio_enable(sor);
3240 tegra_sor_hdmi_audio_disable(sor);
3247 static int tegra_sor_probe(struct platform_device *pdev)
3249 struct device_node *np;
3250 struct tegra_sor *sor;
3251 struct resource *regs;
3254 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3258 sor->soc = of_device_get_match_data(&pdev->dev);
3259 sor->output.dev = sor->dev = &pdev->dev;
3261 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3262 sor->soc->num_settings *
3263 sizeof(*sor->settings),
3268 sor->num_settings = sor->soc->num_settings;
3270 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3272 sor->aux = drm_dp_aux_find_by_of_node(np);
3276 return -EPROBE_DEFER;
3280 if (sor->soc->supports_hdmi) {
3281 sor->ops = &tegra_sor_hdmi_ops;
3282 sor->pad = TEGRA_IO_PAD_HDMI;
3283 } else if (sor->soc->supports_lvds) {
3284 dev_err(&pdev->dev, "LVDS not supported yet\n");
3287 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3291 if (sor->soc->supports_edp) {
3292 sor->ops = &tegra_sor_edp_ops;
3293 sor->pad = TEGRA_IO_PAD_LVDS;
3294 } else if (sor->soc->supports_dp) {
3295 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3298 dev_err(&pdev->dev, "unknown (DP) support\n");
3303 err = tegra_sor_parse_dt(sor);
3307 err = tegra_output_probe(&sor->output);
3309 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3313 if (sor->ops && sor->ops->probe) {
3314 err = sor->ops->probe(sor);
3316 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3317 sor->ops->name, err);
3322 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3323 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3324 if (IS_ERR(sor->regs)) {
3325 err = PTR_ERR(sor->regs);
3329 err = platform_get_irq(pdev, 0);
3331 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3337 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3338 dev_name(sor->dev), sor);
3340 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3344 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
3345 if (IS_ERR(sor->rst)) {
3346 err = PTR_ERR(sor->rst);
3348 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3349 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3355 * At this point, the reset control is most likely being used
3356 * by the generic power domain implementation. With any luck
3357 * the power domain will have taken care of resetting the SOR
3358 * and we don't have to do anything.
3363 sor->clk = devm_clk_get(&pdev->dev, NULL);
3364 if (IS_ERR(sor->clk)) {
3365 err = PTR_ERR(sor->clk);
3366 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3370 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3371 struct device_node *np = pdev->dev.of_node;
3375 * For backwards compatibility with Tegra210 device trees,
3376 * fall back to the old clock name "source" if the new "out"
3377 * clock is not available.
3379 if (of_property_match_string(np, "clock-names", "out") < 0)
3384 sor->clk_out = devm_clk_get(&pdev->dev, name);
3385 if (IS_ERR(sor->clk_out)) {
3386 err = PTR_ERR(sor->clk_out);
3387 dev_err(sor->dev, "failed to get %s clock: %d\n",
3392 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3393 sor->clk_out = sor->clk;
3396 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3397 if (IS_ERR(sor->clk_parent)) {
3398 err = PTR_ERR(sor->clk_parent);
3399 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3403 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3404 if (IS_ERR(sor->clk_safe)) {
3405 err = PTR_ERR(sor->clk_safe);
3406 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3410 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3411 if (IS_ERR(sor->clk_dp)) {
3412 err = PTR_ERR(sor->clk_dp);
3413 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3418 * Starting with Tegra186, the BPMP provides an implementation for
3419 * the pad output clock, so we have to look it up from device tree.
3421 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3422 if (IS_ERR(sor->clk_pad)) {
3423 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3424 err = PTR_ERR(sor->clk_pad);
3429 * If the pad output clock is not available, then we assume
3430 * we're on Tegra210 or earlier and have to provide our own
3433 sor->clk_pad = NULL;
3437 * The bootloader may have set up the SOR such that it's module clock
3438 * is sourced by one of the display PLLs. However, that doesn't work
3439 * without properly having set up other bits of the SOR.
3441 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3443 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3447 platform_set_drvdata(pdev, sor);
3448 pm_runtime_enable(&pdev->dev);
3451 * On Tegra210 and earlier, provide our own implementation for the
3454 if (!sor->clk_pad) {
3455 err = pm_runtime_get_sync(&pdev->dev);
3457 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3462 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3464 pm_runtime_put(&pdev->dev);
3467 if (IS_ERR(sor->clk_pad)) {
3468 err = PTR_ERR(sor->clk_pad);
3469 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3474 INIT_LIST_HEAD(&sor->client.list);
3475 sor->client.ops = &sor_client_ops;
3476 sor->client.dev = &pdev->dev;
3478 err = host1x_client_register(&sor->client);
3480 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3488 if (sor->ops && sor->ops->remove)
3489 sor->ops->remove(sor);
3491 tegra_output_remove(&sor->output);
3495 static int tegra_sor_remove(struct platform_device *pdev)
3497 struct tegra_sor *sor = platform_get_drvdata(pdev);
3500 pm_runtime_disable(&pdev->dev);
3502 err = host1x_client_unregister(&sor->client);
3504 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3509 if (sor->ops && sor->ops->remove) {
3510 err = sor->ops->remove(sor);
3512 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3515 tegra_output_remove(&sor->output);
3521 static int tegra_sor_suspend(struct device *dev)
3523 struct tegra_sor *sor = dev_get_drvdata(dev);
3527 err = reset_control_assert(sor->rst);
3529 dev_err(dev, "failed to assert reset: %d\n", err);
3534 usleep_range(1000, 2000);
3536 clk_disable_unprepare(sor->clk);
3541 static int tegra_sor_resume(struct device *dev)
3543 struct tegra_sor *sor = dev_get_drvdata(dev);
3546 err = clk_prepare_enable(sor->clk);
3548 dev_err(dev, "failed to enable clock: %d\n", err);
3552 usleep_range(1000, 2000);
3555 err = reset_control_deassert(sor->rst);
3557 dev_err(dev, "failed to deassert reset: %d\n", err);
3558 clk_disable_unprepare(sor->clk);
3567 static const struct dev_pm_ops tegra_sor_pm_ops = {
3568 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3571 struct platform_driver tegra_sor_driver = {
3573 .name = "tegra-sor",
3574 .of_match_table = tegra_sor_of_match,
3575 .pm = &tegra_sor_pm_ops,
3577 .probe = tegra_sor_probe,
3578 .remove = tegra_sor_remove,