drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016 Allwinnertech Co., Ltd.
   4  * Copyright (C) 2017-2018 Bootlin
   5  *
   6  * Maxime Ripard <maxime.ripard@bootlin.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/crc-ccitt.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/phy/phy-mipi-dphy.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_print.h>
  26 #include <drm/drm_probe_helper.h>
  27
  28 #include "sun4i_crtc.h"
  29 #include "sun4i_drv.h"
  30 #include "sun4i_tcon.h"
  31 #include "sun6i_mipi_dsi.h"
  32
  33 #include <video/mipi_display.h>
  34
  35 #define SUN6I_DSI_CTL_REG               0x000
  36 #define SUN6I_DSI_CTL_EN                        BIT(0)
  37
  38 #define SUN6I_DSI_BASIC_CTL_REG         0x00c
  39 #define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n)                (((n) & 0xf) << 4)
  40 #define SUN6I_DSI_BASIC_CTL_TRAIL_FILL          BIT(3)
  41 #define SUN6I_DSI_BASIC_CTL_HBP_DIS             BIT(2)
  42 #define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS         BIT(1)
  43 #define SUN6I_DSI_BASIC_CTL_VIDEO_BURST         BIT(0)
  44
  45 #define SUN6I_DSI_BASIC_CTL0_REG        0x010
  46 #define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN         BIT(18)
  47 #define SUN6I_DSI_BASIC_CTL0_CRC_EN             BIT(17)
  48 #define SUN6I_DSI_BASIC_CTL0_ECC_EN             BIT(16)
  49 #define SUN6I_DSI_BASIC_CTL0_INST_ST            BIT(0)
  50
  51 #define SUN6I_DSI_BASIC_CTL1_REG        0x014
  52 #define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n)  (((n) & 0x1fff) << 4)
  53 #define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL         BIT(2)
  54 #define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION    BIT(1)
  55 #define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE         BIT(0)
  56
  57 #define SUN6I_DSI_BASIC_SIZE0_REG       0x018
  58 #define SUN6I_DSI_BASIC_SIZE0_VBP(n)            (((n) & 0xfff) << 16)
  59 #define SUN6I_DSI_BASIC_SIZE0_VSA(n)            ((n) & 0xfff)
  60
  61 #define SUN6I_DSI_BASIC_SIZE1_REG       0x01c
  62 #define SUN6I_DSI_BASIC_SIZE1_VT(n)             (((n) & 0xfff) << 16)
  63 #define SUN6I_DSI_BASIC_SIZE1_VACT(n)           ((n) & 0xfff)
  64
  65 #define SUN6I_DSI_INST_FUNC_REG(n)      (0x020 + (n) * 0x04)
  66 #define SUN6I_DSI_INST_FUNC_INST_MODE(n)        (((n) & 0xf) << 28)
  67 #define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n)     (((n) & 0xf) << 24)
  68 #define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n)     (((n) & 0xf) << 20)
  69 #define SUN6I_DSI_INST_FUNC_LANE_CEN            BIT(4)
  70 #define SUN6I_DSI_INST_FUNC_LANE_DEN(n)         ((n) & 0xf)
  71
  72 #define SUN6I_DSI_INST_LOOP_SEL_REG     0x040
  73
  74 #define SUN6I_DSI_INST_LOOP_NUM_REG(n)  (0x044 + (n) * 0x10)
  75 #define SUN6I_DSI_INST_LOOP_NUM_N1(n)           (((n) & 0xfff) << 16)
  76 #define SUN6I_DSI_INST_LOOP_NUM_N0(n)           ((n) & 0xfff)
  77
  78 #define SUN6I_DSI_INST_JUMP_SEL_REG     0x048
  79
  80 #define SUN6I_DSI_INST_JUMP_CFG_REG(n)  (0x04c + (n) * 0x04)
  81 #define SUN6I_DSI_INST_JUMP_CFG_TO(n)           (((n) & 0xf) << 20)
  82 #define SUN6I_DSI_INST_JUMP_CFG_POINT(n)        (((n) & 0xf) << 16)
  83 #define SUN6I_DSI_INST_JUMP_CFG_NUM(n)          ((n) & 0xffff)
  84
  85 #define SUN6I_DSI_TRANS_START_REG       0x060
  86
  87 #define SUN6I_DSI_TRANS_ZERO_REG        0x078
  88
  89 #define SUN6I_DSI_TCON_DRQ_REG          0x07c
  90 #define SUN6I_DSI_TCON_DRQ_ENABLE_MODE          BIT(28)
  91 #define SUN6I_DSI_TCON_DRQ_SET(n)               ((n) & 0x3ff)
  92
  93 #define SUN6I_DSI_PIXEL_CTL0_REG        0x080
  94 #define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE    BIT(16)
  95 #define SUN6I_DSI_PIXEL_CTL0_FORMAT(n)          ((n) & 0xf)
  96
  97 #define SUN6I_DSI_PIXEL_CTL1_REG        0x084
  98
  99 #define SUN6I_DSI_PIXEL_PH_REG          0x090
 100 #define SUN6I_DSI_PIXEL_PH_ECC(n)               (((n) & 0xff) << 24)
 101 #define SUN6I_DSI_PIXEL_PH_WC(n)                (((n) & 0xffff) << 8)
 102 #define SUN6I_DSI_PIXEL_PH_VC(n)                (((n) & 3) << 6)
 103 #define SUN6I_DSI_PIXEL_PH_DT(n)                ((n) & 0x3f)
 104
 105 #define SUN6I_DSI_PIXEL_PF0_REG         0x098
 106 #define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n)        ((n) & 0xffff)
 107
 108 #define SUN6I_DSI_PIXEL_PF1_REG         0x09c
 109 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n)   (((n) & 0xffff) << 16)
 110 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n)   ((n) & 0xffff)
 111
 112 #define SUN6I_DSI_SYNC_HSS_REG          0x0b0
 113
 114 #define SUN6I_DSI_SYNC_HSE_REG          0x0b4
 115
 116 #define SUN6I_DSI_SYNC_VSS_REG          0x0b8
 117
 118 #define SUN6I_DSI_SYNC_VSE_REG          0x0bc
 119
 120 #define SUN6I_DSI_BLK_HSA0_REG          0x0c0
 121
 122 #define SUN6I_DSI_BLK_HSA1_REG          0x0c4
 123 #define SUN6I_DSI_BLK_PF(n)                     (((n) & 0xffff) << 16)
 124 #define SUN6I_DSI_BLK_PD(n)                     ((n) & 0xff)
 125
 126 #define SUN6I_DSI_BLK_HBP0_REG          0x0c8
 127
 128 #define SUN6I_DSI_BLK_HBP1_REG          0x0cc
 129
 130 #define SUN6I_DSI_BLK_HFP0_REG          0x0d0
 131
 132 #define SUN6I_DSI_BLK_HFP1_REG          0x0d4
 133
 134 #define SUN6I_DSI_BLK_HBLK0_REG         0x0e0
 135
 136 #define SUN6I_DSI_BLK_HBLK1_REG         0x0e4
 137
 138 #define SUN6I_DSI_BLK_VBLK0_REG         0x0e8
 139
 140 #define SUN6I_DSI_BLK_VBLK1_REG         0x0ec
 141
 142 #define SUN6I_DSI_BURST_LINE_REG        0x0f0
 143 #define SUN6I_DSI_BURST_LINE_SYNC_POINT(n)      (((n) & 0xffff) << 16)
 144 #define SUN6I_DSI_BURST_LINE_NUM(n)             ((n) & 0xffff)
 145
 146 #define SUN6I_DSI_BURST_DRQ_REG         0x0f4
 147 #define SUN6I_DSI_BURST_DRQ_EDGE1(n)            (((n) & 0xffff) << 16)
 148 #define SUN6I_DSI_BURST_DRQ_EDGE0(n)            ((n) & 0xffff)
 149
 150 #define SUN6I_DSI_CMD_CTL_REG           0x200
 151 #define SUN6I_DSI_CMD_CTL_RX_OVERFLOW           BIT(26)
 152 #define SUN6I_DSI_CMD_CTL_RX_FLAG               BIT(25)
 153 #define SUN6I_DSI_CMD_CTL_TX_FLAG               BIT(9)
 154
 155 #define SUN6I_DSI_CMD_RX_REG(n)         (0x240 + (n) * 0x04)
 156
 157 #define SUN6I_DSI_DEBUG_DATA_REG        0x2f8
 158
 159 #define SUN6I_DSI_CMD_TX_REG(n)         (0x300 + (n) * 0x04)
 160
 161 #define SUN6I_DSI_SYNC_POINT            40
 162
 163 enum sun6i_dsi_start_inst {
 164         DSI_START_LPRX,
 165         DSI_START_LPTX,
 166         DSI_START_HSC,
 167         DSI_START_HSD,
 168 };
 169
 170 enum sun6i_dsi_inst_id {
 171         DSI_INST_ID_LP11        = 0,
 172         DSI_INST_ID_TBA,
 173         DSI_INST_ID_HSC,
 174         DSI_INST_ID_HSD,
 175         DSI_INST_ID_LPDT,
 176         DSI_INST_ID_HSCEXIT,
 177         DSI_INST_ID_NOP,
 178         DSI_INST_ID_DLY,
 179         DSI_INST_ID_END         = 15,
 180 };
 181
 182 enum sun6i_dsi_inst_mode {
 183         DSI_INST_MODE_STOP      = 0,
 184         DSI_INST_MODE_TBA,
 185         DSI_INST_MODE_HS,
 186         DSI_INST_MODE_ESCAPE,
 187         DSI_INST_MODE_HSCEXIT,
 188         DSI_INST_MODE_NOP,
 189 };
 190
 191 enum sun6i_dsi_inst_escape {
 192         DSI_INST_ESCA_LPDT      = 0,
 193         DSI_INST_ESCA_ULPS,
 194         DSI_INST_ESCA_UN1,
 195         DSI_INST_ESCA_UN2,
 196         DSI_INST_ESCA_RESET,
 197         DSI_INST_ESCA_UN3,
 198         DSI_INST_ESCA_UN4,
 199         DSI_INST_ESCA_UN5,
 200 };
 201
 202 enum sun6i_dsi_inst_packet {
 203         DSI_INST_PACK_PIXEL     = 0,
 204         DSI_INST_PACK_COMMAND,
 205 };
 206
 207 static const u32 sun6i_dsi_ecc_array[] = {
 208         [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
 209                BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
 210                BIT(23)),
 211         [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
 212                BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
 213                BIT(23)),
 214         [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
 215                BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
 216         [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
 217                BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
 218         [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
 219                BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
 220         [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
 221                BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
 222                BIT(23)),
 223 };
 224
 225 static u32 sun6i_dsi_ecc_compute(unsigned int data)
 226 {
 227         int i;
 228         u8 ecc = 0;
 229
 230         for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
 231                 u32 field = sun6i_dsi_ecc_array[i];
 232                 bool init = false;
 233                 u8 val = 0;
 234                 int j;
 235
 236                 for (j = 0; j < 24; j++) {
 237                         if (!(BIT(j) & field))
 238                                 continue;
 239
 240                         if (!init) {
 241                                 val = (BIT(j) & data) ? 1 : 0;
 242                                 init = true;
 243                         } else {
 244                                 val ^= (BIT(j) & data) ? 1 : 0;
 245                         }
 246                 }
 247
 248                 ecc |= val << i;
 249         }
 250
 251         return ecc;
 252 }
 253
 254 static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
 255 {
 256         return crc_ccitt(0xffff, buffer, len);
 257 }
 258
 259 static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len)
 260 {
 261         memset(buffer, pd, len);
 262
 263         return sun6i_dsi_crc_compute(buffer, len);
 264 }
 265
 266 static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
 267 {
 268         u32 val = dt & 0x3f;
 269
 270         val |= (vc & 3) << 6;
 271         val |= (d0 & 0xff) << 8;
 272         val |= (d1 & 0xff) << 16;
 273         val |= sun6i_dsi_ecc_compute(val) << 24;
 274
 275         return val;
 276 }
 277
 278 static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
 279 {
 280         return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
 281                                         wc & 0xff, wc >> 8);
 282 }
 283
 284 static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len)
 285 {
 286         u32 val = SUN6I_DSI_BLK_PD(pd);
 287
 288         return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len));
 289 }
 290
 291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
 292 {
 293         regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
 294                            SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
 295 }
 296
 297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
 298 {
 299         regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
 300                            SUN6I_DSI_BASIC_CTL0_INST_ST,
 301                            SUN6I_DSI_BASIC_CTL0_INST_ST);
 302 }
 303
 304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
 305 {
 306         u32 val;
 307
 308         return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
 309                                         val,
 310                                         !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
 311                                         100, 5000);
 312 }
 313
 314 static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
 315                                  enum sun6i_dsi_inst_id id,
 316                                  enum sun6i_dsi_inst_mode mode,
 317                                  bool clock, u8 data,
 318                                  enum sun6i_dsi_inst_packet packet,
 319                                  enum sun6i_dsi_inst_escape escape)
 320 {
 321         regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
 322                      SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
 323                      SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
 324                      SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
 325                      (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
 326                      SUN6I_DSI_INST_FUNC_LANE_DEN(data));
 327 }
 328
 329 static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
 330                                 struct mipi_dsi_device *device)
 331 {
 332         u8 lanes_mask = GENMASK(device->lanes - 1, 0);
 333
 334         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
 335                              true, lanes_mask, 0, 0);
 336
 337         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
 338                              false, 1, 0, 0);
 339
 340         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
 341                              true, 0, DSI_INST_PACK_PIXEL, 0);
 342
 343         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
 344                              false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
 345
 346         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
 347                              false, 1, DSI_INST_PACK_COMMAND,
 348                              DSI_INST_ESCA_LPDT);
 349
 350         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
 351                              true, 0, 0, 0);
 352
 353         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
 354                              false, lanes_mask, 0, 0);
 355
 356         sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
 357                              true, lanes_mask, 0, 0);
 358
 359         regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
 360                      SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
 361                      SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
 362                      SUN6I_DSI_INST_JUMP_CFG_NUM(1));
 363 };
 364
 365 static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
 366                                            struct drm_display_mode *mode)
 367 {
 368         u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100);
 369         u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + start;
 370
 371         if (delay > mode->vtotal)
 372                 delay = delay % mode->vtotal;
 373
 374         return max_t(u16, delay, 1);
 375 }
 376
 377 static u16 sun6i_dsi_get_line_num(struct sun6i_dsi *dsi,
 378                                   struct drm_display_mode *mode)
 379 {
 380         struct mipi_dsi_device *device = dsi->device;
 381         unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
 382
 383         return mode->htotal * Bpp / device->lanes;
 384 }
 385
 386 static u16 sun6i_dsi_get_drq_edge0(struct sun6i_dsi *dsi,
 387                                    struct drm_display_mode *mode,
 388                                    u16 line_num, u16 edge1)
 389 {
 390         u16 edge0 = edge1;
 391
 392         edge0 += (mode->hdisplay + 40) * SUN6I_DSI_TCON_DIV / 8;
 393
 394         if (edge0 > line_num)
 395                 return edge0 - line_num;
 396
 397         return 1;
 398 }
 399
 400 static u16 sun6i_dsi_get_drq_edge1(struct sun6i_dsi *dsi,
 401                                    struct drm_display_mode *mode,
 402                                    u16 line_num)
 403 {
 404         struct mipi_dsi_device *device = dsi->device;
 405         unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
 406         unsigned int hbp = mode->htotal - mode->hsync_end;
 407         u16 edge1;
 408
 409         edge1 = SUN6I_DSI_SYNC_POINT;
 410         edge1 += (mode->hdisplay + hbp + 20) * Bpp / device->lanes;
 411
 412         if (edge1 > line_num)
 413                 return line_num;
 414
 415         return edge1;
 416 }
 417
 418 static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
 419                                   struct drm_display_mode *mode)
 420 {
 421         struct mipi_dsi_device *device = dsi->device;
 422         u32 val = 0;
 423
 424         if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 425                 u16 line_num = sun6i_dsi_get_line_num(dsi, mode);
 426                 u16 edge0, edge1;
 427
 428                 edge1 = sun6i_dsi_get_drq_edge1(dsi, mode, line_num);
 429                 edge0 = sun6i_dsi_get_drq_edge0(dsi, mode, line_num, edge1);
 430
 431                 regmap_write(dsi->regs, SUN6I_DSI_BURST_DRQ_REG,
 432                              SUN6I_DSI_BURST_DRQ_EDGE0(edge0) |
 433                              SUN6I_DSI_BURST_DRQ_EDGE1(edge1));
 434
 435                 regmap_write(dsi->regs, SUN6I_DSI_BURST_LINE_REG,
 436                              SUN6I_DSI_BURST_LINE_NUM(line_num) |
 437                              SUN6I_DSI_BURST_LINE_SYNC_POINT(SUN6I_DSI_SYNC_POINT));
 438
 439                 val = SUN6I_DSI_TCON_DRQ_ENABLE_MODE;
 440         } else if ((mode->hsync_end - mode->hdisplay) > 20) {
 441                 /* Maaaaaagic */
 442                 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
 443
 444                 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
 445                 drq /= 32;
 446
 447                 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
 448                        SUN6I_DSI_TCON_DRQ_SET(drq));
 449         }
 450
 451         regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
 452 }
 453
 454 static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
 455                                       struct drm_display_mode *mode)
 456 {
 457         struct mipi_dsi_device *device = dsi->device;
 458         u16 delay = 50 - 1;
 459
 460         if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 461                 u32 hsync_porch = (mode->htotal - mode->hdisplay) * 150;
 462
 463                 delay = (hsync_porch / ((mode->clock / 1000) * 8));
 464                 delay -= 50;
 465         }
 466
 467         regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_SEL_REG,
 468                      2 << (4 * DSI_INST_ID_LP11) |
 469                      3 << (4 * DSI_INST_ID_DLY));
 470
 471         regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
 472                      SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
 473                      SUN6I_DSI_INST_LOOP_NUM_N1(delay));
 474         regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
 475                      SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
 476                      SUN6I_DSI_INST_LOOP_NUM_N1(delay));
 477 }
 478
 479 static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
 480                                    struct drm_display_mode *mode)
 481 {
 482         struct mipi_dsi_device *device = dsi->device;
 483         u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
 484         u8 dt, fmt;
 485         u16 wc;
 486
 487         /*
 488          * TODO: The format defines are only valid in video mode and
 489          * change in command mode.
 490          */
 491         switch (device->format) {
 492         case MIPI_DSI_FMT_RGB888:
 493                 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
 494                 fmt = 8;
 495                 break;
 496         case MIPI_DSI_FMT_RGB666:
 497                 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
 498                 fmt = 9;
 499                 break;
 500         case MIPI_DSI_FMT_RGB666_PACKED:
 501                 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
 502                 fmt = 10;
 503                 break;
 504         case MIPI_DSI_FMT_RGB565:
 505                 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
 506                 fmt = 11;
 507                 break;
 508         default:
 509                 return;
 510         }
 511         val |= SUN6I_DSI_PIXEL_PH_DT(dt);
 512
 513         wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
 514         val |= SUN6I_DSI_PIXEL_PH_WC(wc);
 515         val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
 516
 517         regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
 518
 519         regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
 520                      SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
 521
 522         regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
 523                      SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
 524                      SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
 525
 526         regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
 527                      SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
 528                      SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
 529 }
 530
 531 static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
 532                                     struct drm_display_mode *mode)
 533 {
 534         struct mipi_dsi_device *device = dsi->device;
 535         unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
 536         u16 hbp = 0, hfp = 0, hsa = 0, hblk = 0, vblk = 0;
 537         u32 basic_ctl = 0;
 538         size_t bytes;
 539         u8 *buffer;
 540
 541         /* Do all timing calculations up front to allocate buffer space */
 542
 543         if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 544                 hblk = mode->hdisplay * Bpp;
 545                 basic_ctl = SUN6I_DSI_BASIC_CTL_VIDEO_BURST |
 546                             SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS |
 547                             SUN6I_DSI_BASIC_CTL_HBP_DIS;
 548
 549                 if (device->lanes == 4)
 550                         basic_ctl |= SUN6I_DSI_BASIC_CTL_TRAIL_FILL |
 551                                      SUN6I_DSI_BASIC_CTL_TRAIL_INV(0xc);
 552         } else {
 553                 /*
 554                  * A sync period is composed of a blanking packet (4
 555                  * bytes + payload + 2 bytes) and a sync event packet
 556                  * (4 bytes). Its minimal size is therefore 10 bytes
 557                  */
 558 #define HSA_PACKET_OVERHEAD     10
 559                 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
 560                           (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
 561
 562                 /*
 563                  * The backporch is set using a blanking packet (4
 564                  * bytes + payload + 2 bytes). Its minimal size is
 565                  * therefore 6 bytes
 566                  */
 567 #define HBP_PACKET_OVERHEAD     6
 568                 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
 569                           (mode->htotal - mode->hsync_end) * Bpp - HBP_PACKET_OVERHEAD);
 570
 571                 /*
 572                  * The frontporch is set using a blanking packet (4
 573                  * bytes + payload + 2 bytes). Its minimal size is
 574                  * therefore 6 bytes
 575                  */
 576 #define HFP_PACKET_OVERHEAD     6
 577                 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
 578                           (mode->hsync_start - mode->hdisplay) * Bpp - HFP_PACKET_OVERHEAD);
 579
 580                 /*
 581                  * The blanking is set using a sync event (4 bytes)
 582                  * and a blanking packet (4 bytes + payload + 2
 583                  * bytes). Its minimal size is therefore 10 bytes.
 584                  */
 585 #define HBLK_PACKET_OVERHEAD    10
 586                 hblk = max((unsigned int)HBLK_PACKET_OVERHEAD,
 587                            (mode->htotal - (mode->hsync_end - mode->hsync_start)) * Bpp -
 588                            HBLK_PACKET_OVERHEAD);
 589
 590                 /*
 591                  * And I'm not entirely sure what vblk is about. The driver in
 592                  * Allwinner BSP is using a rather convoluted calculation
 593                  * there only for 4 lanes. However, using 0 (the !4 lanes
 594                  * case) even with a 4 lanes screen seems to work...
 595                  */
 596                 vblk = 0;
 597         }
 598
 599         /* How many bytes do we need to send all payloads? */
 600         bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
 601         buffer = kmalloc(bytes, GFP_KERNEL);
 602         if (WARN_ON(!buffer))
 603                 return;
 604
 605         regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, basic_ctl);
 606
 607         regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
 608                      sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
 609                                               device->channel,
 610                                               0, 0));
 611
 612         regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
 613                      sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
 614                                               device->channel,
 615                                               0, 0));
 616
 617         regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
 618                      sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
 619                                               device->channel,
 620                                               0, 0));
 621
 622         regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
 623                      sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
 624                                               device->channel,
 625                                               0, 0));
 626
 627         regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
 628                      SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
 629                                                mode->vsync_start) |
 630                      SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal -
 631                                                mode->vsync_end));
 632
 633         regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
 634                      SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
 635                      SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
 636
 637         /* sync */
 638         regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
 639                      sun6i_dsi_build_blk0_pkt(device->channel, hsa));
 640         regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
 641                      sun6i_dsi_build_blk1_pkt(0, buffer, hsa));
 642
 643         /* backporch */
 644         regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
 645                      sun6i_dsi_build_blk0_pkt(device->channel, hbp));
 646         regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
 647                      sun6i_dsi_build_blk1_pkt(0, buffer, hbp));
 648
 649         /* frontporch */
 650         regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
 651                      sun6i_dsi_build_blk0_pkt(device->channel, hfp));
 652         regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
 653                      sun6i_dsi_build_blk1_pkt(0, buffer, hfp));
 654
 655         /* hblk */
 656         regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
 657                      sun6i_dsi_build_blk0_pkt(device->channel, hblk));
 658         regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
 659                      sun6i_dsi_build_blk1_pkt(0, buffer, hblk));
 660
 661         /* vblk */
 662         regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
 663                      sun6i_dsi_build_blk0_pkt(device->channel, vblk));
 664         regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
 665                      sun6i_dsi_build_blk1_pkt(0, buffer, vblk));
 666
 667         kfree(buffer);
 668 }
 669
 670 static int sun6i_dsi_start(struct sun6i_dsi *dsi,
 671                            enum sun6i_dsi_start_inst func)
 672 {
 673         switch (func) {
 674         case DSI_START_LPTX:
 675                 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
 676                              DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
 677                              DSI_INST_ID_END  << (4 * DSI_INST_ID_LPDT));
 678                 break;
 679         case DSI_START_LPRX:
 680                 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
 681                              DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
 682                              DSI_INST_ID_DLY  << (4 * DSI_INST_ID_LPDT) |
 683                              DSI_INST_ID_TBA  << (4 * DSI_INST_ID_DLY) |
 684                              DSI_INST_ID_END  << (4 * DSI_INST_ID_TBA));
 685                 break;
 686         case DSI_START_HSC:
 687                 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
 688                              DSI_INST_ID_HSC  << (4 * DSI_INST_ID_LP11) |
 689                              DSI_INST_ID_END  << (4 * DSI_INST_ID_HSC));
 690                 break;
 691         case DSI_START_HSD:
 692                 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
 693                              DSI_INST_ID_NOP  << (4 * DSI_INST_ID_LP11) |
 694                              DSI_INST_ID_HSD  << (4 * DSI_INST_ID_NOP) |
 695                              DSI_INST_ID_DLY  << (4 * DSI_INST_ID_HSD) |
 696                              DSI_INST_ID_NOP  << (4 * DSI_INST_ID_DLY) |
 697                              DSI_INST_ID_END  << (4 * DSI_INST_ID_HSCEXIT));
 698                 break;
 699         default:
 700                 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
 701                              DSI_INST_ID_END  << (4 * DSI_INST_ID_LP11));
 702                 break;
 703         }
 704
 705         sun6i_dsi_inst_abort(dsi);
 706         sun6i_dsi_inst_commit(dsi);
 707
 708         if (func == DSI_START_HSC)
 709                 regmap_write_bits(dsi->regs,
 710                                   SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
 711                                   SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
 712
 713         return 0;
 714 }
 715
 716 static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
 717 {
 718         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 719         struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
 720         struct mipi_dsi_device *device = dsi->device;
 721         union phy_configure_opts opts = { 0 };
 722         struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
 723         u16 delay;
 724
 725         DRM_DEBUG_DRIVER("Enabling DSI output\n");
 726
 727         pm_runtime_get_sync(dsi->dev);
 728
 729         delay = sun6i_dsi_get_video_start_delay(dsi, mode);
 730         regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
 731                      SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
 732                      SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
 733                      SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
 734                      SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
 735
 736         sun6i_dsi_setup_burst(dsi, mode);
 737         sun6i_dsi_setup_inst_loop(dsi, mode);
 738         sun6i_dsi_setup_format(dsi, mode);
 739         sun6i_dsi_setup_timings(dsi, mode);
 740
 741         phy_init(dsi->dphy);
 742
 743         phy_mipi_dphy_get_default_config(mode->clock * 1000,
 744                                          mipi_dsi_pixel_format_to_bpp(device->format),
 745                                          device->lanes, cfg);
 746
 747         phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
 748         phy_configure(dsi->dphy, &opts);
 749         phy_power_on(dsi->dphy);
 750
 751         if (!IS_ERR(dsi->panel))
 752                 drm_panel_prepare(dsi->panel);
 753
 754         /*
 755          * FIXME: This should be moved after the switch to HS mode.
 756          *
 757          * Unfortunately, once in HS mode, it seems like we're not
 758          * able to send DCS commands anymore, which would prevent any
 759          * panel to send any DCS command as part as their enable
 760          * method, which is quite common.
 761          *
 762          * I haven't seen any artifact due to that sub-optimal
 763          * ordering on the panels I've tested it with, so I guess this
 764          * will do for now, until that IP is better understood.
 765          */
 766         if (!IS_ERR(dsi->panel))
 767                 drm_panel_enable(dsi->panel);
 768
 769         sun6i_dsi_start(dsi, DSI_START_HSC);
 770
 771         udelay(1000);
 772
 773         sun6i_dsi_start(dsi, DSI_START_HSD);
 774 }
 775
 776 static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
 777 {
 778         struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
 779
 780         DRM_DEBUG_DRIVER("Disabling DSI output\n");
 781
 782         if (!IS_ERR(dsi->panel)) {
 783                 drm_panel_disable(dsi->panel);
 784                 drm_panel_unprepare(dsi->panel);
 785         }
 786
 787         phy_power_off(dsi->dphy);
 788         phy_exit(dsi->dphy);
 789
 790         pm_runtime_put(dsi->dev);
 791 }
 792
 793 static int sun6i_dsi_get_modes(struct drm_connector *connector)
 794 {
 795         struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
 796
 797         return drm_panel_get_modes(dsi->panel);
 798 }
 799
 800 static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
 801         .get_modes      = sun6i_dsi_get_modes,
 802 };
 803
 804 static enum drm_connector_status
 805 sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
 806 {
 807         return connector_status_connected;
 808 }
 809
 810 static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
 811         .detect                 = sun6i_dsi_connector_detect,
 812         .fill_modes             = drm_helper_probe_single_connector_modes,
 813         .destroy                = drm_connector_cleanup,
 814         .reset                  = drm_atomic_helper_connector_reset,
 815         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 816         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 817 };
 818
 819 static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
 820         .disable        = sun6i_dsi_encoder_disable,
 821         .enable         = sun6i_dsi_encoder_enable,
 822 };
 823
 824 static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
 825         .destroy        = drm_encoder_cleanup,
 826 };
 827
 828 static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
 829                                        const struct mipi_dsi_msg *msg)
 830 {
 831         u32 pkt = msg->type;
 832
 833         if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
 834                 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
 835                 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
 836         } else {
 837                 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
 838                 if (msg->tx_len > 1)
 839                         pkt |= (((u8 *)msg->tx_buf)[1] << 16);
 840         }
 841
 842         pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
 843
 844         return pkt;
 845 }
 846
 847 static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
 848                                      const struct mipi_dsi_msg *msg)
 849 {
 850         regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
 851                      sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
 852         regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
 853                           0xff, (4 - 1));
 854
 855         sun6i_dsi_start(dsi, DSI_START_LPTX);
 856
 857         return msg->tx_len;
 858 }
 859
 860 static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
 861                                     const struct mipi_dsi_msg *msg)
 862 {
 863         int ret, len = 0;
 864         u8 *bounce;
 865         u16 crc;
 866
 867         regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
 868                      sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
 869
 870         bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
 871         if (!bounce)
 872                 return -ENOMEM;
 873
 874         memcpy(bounce, msg->tx_buf, msg->tx_len);
 875         len += msg->tx_len;
 876
 877         crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
 878         memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
 879         len += sizeof(crc);
 880
 881         regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
 882         regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
 883         kfree(bounce);
 884
 885         sun6i_dsi_start(dsi, DSI_START_LPTX);
 886
 887         ret = sun6i_dsi_inst_wait_for_completion(dsi);
 888         if (ret < 0) {
 889                 sun6i_dsi_inst_abort(dsi);
 890                 return ret;
 891         }
 892
 893         /*
 894          * TODO: There's some bits (reg 0x200, bits 8/9) that
 895          * apparently can be used to check whether the data have been
 896          * sent, but I couldn't get it to work reliably.
 897          */
 898         return msg->tx_len;
 899 }
 900
 901 static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
 902                               const struct mipi_dsi_msg *msg)
 903 {
 904         u32 val;
 905         int ret;
 906         u8 byte0;
 907
 908         regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
 909                      sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
 910         regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
 911                      (4 - 1));
 912
 913         sun6i_dsi_start(dsi, DSI_START_LPRX);
 914
 915         ret = sun6i_dsi_inst_wait_for_completion(dsi);
 916         if (ret < 0) {
 917                 sun6i_dsi_inst_abort(dsi);
 918                 return ret;
 919         }
 920
 921         /*
 922          * TODO: There's some bits (reg 0x200, bits 24/25) that
 923          * apparently can be used to check whether the data have been
 924          * received, but I couldn't get it to work reliably.
 925          */
 926         regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
 927         if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
 928                 return -EIO;
 929
 930         regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
 931         byte0 = val & 0xff;
 932         if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
 933                 return -EIO;
 934
 935         ((u8 *)msg->rx_buf)[0] = (val >> 8);
 936
 937         return 1;
 938 }
 939
 940 static int sun6i_dsi_attach(struct mipi_dsi_host *host,
 941                             struct mipi_dsi_device *device)
 942 {
 943         struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
 944
 945         dsi->device = device;
 946         dsi->panel = of_drm_find_panel(device->dev.of_node);
 947         if (IS_ERR(dsi->panel))
 948                 return PTR_ERR(dsi->panel);
 949
 950         dev_info(host->dev, "Attached device %s\n", device->name);
 951
 952         return 0;
 953 }
 954
 955 static int sun6i_dsi_detach(struct mipi_dsi_host *host,
 956                             struct mipi_dsi_device *device)
 957 {
 958         struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
 959
 960         dsi->panel = NULL;
 961         dsi->device = NULL;
 962
 963         return 0;
 964 }
 965
 966 static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
 967                                   const struct mipi_dsi_msg *msg)
 968 {
 969         struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
 970         int ret;
 971
 972         ret = sun6i_dsi_inst_wait_for_completion(dsi);
 973         if (ret < 0)
 974                 sun6i_dsi_inst_abort(dsi);
 975
 976         regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
 977                      SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
 978                      SUN6I_DSI_CMD_CTL_RX_FLAG |
 979                      SUN6I_DSI_CMD_CTL_TX_FLAG);
 980
 981         switch (msg->type) {
 982         case MIPI_DSI_DCS_SHORT_WRITE:
 983         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 984         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 985                 ret = sun6i_dsi_dcs_write_short(dsi, msg);
 986                 break;
 987
 988         case MIPI_DSI_DCS_LONG_WRITE:
 989                 ret = sun6i_dsi_dcs_write_long(dsi, msg);
 990                 break;
 991
 992         case MIPI_DSI_DCS_READ:
 993                 if (msg->rx_len == 1) {
 994                         ret = sun6i_dsi_dcs_read(dsi, msg);
 995                         break;
 996                 }
 997                 /* Else, fall through */
 998
 999         default:
1000                 ret = -EINVAL;
1001         }
1002
1003         return ret;
1004 }
1005
1006 static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
1007         .attach         = sun6i_dsi_attach,
1008         .detach         = sun6i_dsi_detach,
1009         .transfer       = sun6i_dsi_transfer,
1010 };
1011
1012 static const struct regmap_config sun6i_dsi_regmap_config = {
1013         .reg_bits       = 32,
1014         .val_bits       = 32,
1015         .reg_stride     = 4,
1016         .max_register   = SUN6I_DSI_CMD_TX_REG(255),
1017         .name           = "mipi-dsi",
1018 };
1019
1020 static int sun6i_dsi_bind(struct device *dev, struct device *master,
1021                          void *data)
1022 {
1023         struct drm_device *drm = data;
1024         struct sun4i_drv *drv = drm->dev_private;
1025         struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1026         int ret;
1027
1028         if (!dsi->panel)
1029                 return -EPROBE_DEFER;
1030
1031         dsi->drv = drv;
1032
1033         drm_encoder_helper_add(&dsi->encoder,
1034                                &sun6i_dsi_enc_helper_funcs);
1035         ret = drm_encoder_init(drm,
1036                                &dsi->encoder,
1037                                &sun6i_dsi_enc_funcs,
1038                                DRM_MODE_ENCODER_DSI,
1039                                NULL);
1040         if (ret) {
1041                 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
1042                 return ret;
1043         }
1044         dsi->encoder.possible_crtcs = BIT(0);
1045
1046         drm_connector_helper_add(&dsi->connector,
1047                                  &sun6i_dsi_connector_helper_funcs);
1048         ret = drm_connector_init(drm, &dsi->connector,
1049                                  &sun6i_dsi_connector_funcs,
1050                                  DRM_MODE_CONNECTOR_DSI);
1051         if (ret) {
1052                 dev_err(dsi->dev,
1053                         "Couldn't initialise the DSI connector\n");
1054                 goto err_cleanup_connector;
1055         }
1056
1057         drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
1058         drm_panel_attach(dsi->panel, &dsi->connector);
1059
1060         return 0;
1061
1062 err_cleanup_connector:
1063         drm_encoder_cleanup(&dsi->encoder);
1064         return ret;
1065 }
1066
1067 static void sun6i_dsi_unbind(struct device *dev, struct device *master,
1068                             void *data)
1069 {
1070         struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1071
1072         drm_panel_detach(dsi->panel);
1073 }
1074
1075 static const struct component_ops sun6i_dsi_ops = {
1076         .bind   = sun6i_dsi_bind,
1077         .unbind = sun6i_dsi_unbind,
1078 };
1079
1080 static int sun6i_dsi_probe(struct platform_device *pdev)
1081 {
1082         struct device *dev = &pdev->dev;
1083         struct sun6i_dsi *dsi;
1084         struct resource *res;
1085         void __iomem *base;
1086         int ret;
1087
1088         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1089         if (!dsi)
1090                 return -ENOMEM;
1091         dev_set_drvdata(dev, dsi);
1092         dsi->dev = dev;
1093         dsi->host.ops = &sun6i_dsi_host_ops;
1094         dsi->host.dev = dev;
1095
1096         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1097         base = devm_ioremap_resource(dev, res);
1098         if (IS_ERR(base)) {
1099                 dev_err(dev, "Couldn't map the DSI encoder registers\n");
1100                 return PTR_ERR(base);
1101         }
1102
1103         dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
1104                                               &sun6i_dsi_regmap_config);
1105         if (IS_ERR(dsi->regs)) {
1106                 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
1107                 return PTR_ERR(dsi->regs);
1108         }
1109
1110         dsi->reset = devm_reset_control_get_shared(dev, NULL);
1111         if (IS_ERR(dsi->reset)) {
1112                 dev_err(dev, "Couldn't get our reset line\n");
1113                 return PTR_ERR(dsi->reset);
1114         }
1115
1116         dsi->mod_clk = devm_clk_get(dev, "mod");
1117         if (IS_ERR(dsi->mod_clk)) {
1118                 dev_err(dev, "Couldn't get the DSI mod clock\n");
1119                 return PTR_ERR(dsi->mod_clk);
1120         }
1121
1122         /*
1123          * In order to operate properly, that clock seems to be always
1124          * set to 297MHz.
1125          */
1126         clk_set_rate_exclusive(dsi->mod_clk, 297000000);
1127
1128         dsi->dphy = devm_phy_get(dev, "dphy");
1129         if (IS_ERR(dsi->dphy)) {
1130                 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1131                 ret = PTR_ERR(dsi->dphy);
1132                 goto err_unprotect_clk;
1133         }
1134
1135         pm_runtime_enable(dev);
1136
1137         ret = mipi_dsi_host_register(&dsi->host);
1138         if (ret) {
1139                 dev_err(dev, "Couldn't register MIPI-DSI host\n");
1140                 goto err_pm_disable;
1141         }
1142
1143         ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1144         if (ret) {
1145                 dev_err(dev, "Couldn't register our component\n");
1146                 goto err_remove_dsi_host;
1147         }
1148
1149         return 0;
1150
1151 err_remove_dsi_host:
1152         mipi_dsi_host_unregister(&dsi->host);
1153 err_pm_disable:
1154         pm_runtime_disable(dev);
1155 err_unprotect_clk:
1156         clk_rate_exclusive_put(dsi->mod_clk);
1157         return ret;
1158 }
1159
1160 static int sun6i_dsi_remove(struct platform_device *pdev)
1161 {
1162         struct device *dev = &pdev->dev;
1163         struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1164
1165         component_del(&pdev->dev, &sun6i_dsi_ops);
1166         mipi_dsi_host_unregister(&dsi->host);
1167         pm_runtime_disable(dev);
1168         clk_rate_exclusive_put(dsi->mod_clk);
1169
1170         return 0;
1171 }
1172
1173 static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
1174 {
1175         struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1176
1177         reset_control_deassert(dsi->reset);
1178         clk_prepare_enable(dsi->mod_clk);
1179
1180         /*
1181          * Enable the DSI block.
1182          *
1183          * Some part of it can only be done once we get a number of
1184          * lanes, see sun6i_dsi_inst_init
1185          */
1186         regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1187
1188         regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1189                      SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1190
1191         regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1192         regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1193
1194         if (dsi->device)
1195                 sun6i_dsi_inst_init(dsi, dsi->device);
1196
1197         regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1198
1199         return 0;
1200 }
1201
1202 static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
1203 {
1204         struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1205
1206         clk_disable_unprepare(dsi->mod_clk);
1207         reset_control_assert(dsi->reset);
1208
1209         return 0;
1210 }
1211
1212 static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1213         SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1214                            sun6i_dsi_runtime_resume,
1215                            NULL)
1216 };
1217
1218 static const struct of_device_id sun6i_dsi_of_table[] = {
1219         { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1220         { }
1221 };
1222 MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1223
1224 static struct platform_driver sun6i_dsi_platform_driver = {
1225         .probe          = sun6i_dsi_probe,
1226         .remove         = sun6i_dsi_remove,
1227         .driver         = {
1228                 .name           = "sun6i-mipi-dsi",
1229                 .of_match_table = sun6i_dsi_of_table,
1230                 .pm             = &sun6i_dsi_pm_ops,
1231         },
1232 };
1233 module_platform_driver(sun6i_dsi_platform_driver);
1234
1235 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1236 MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1237 MODULE_LICENSE("GPL");