2 * Copyright (C) 2016 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_edid.h>
16 #include <drm/drm_encoder.h>
17 #include <drm/drm_of.h>
18 #include <drm/drm_panel.h>
20 #include <linux/clk.h>
21 #include <linux/component.h>
22 #include <linux/iopoll.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include "sun4i_backend.h"
27 #include "sun4i_crtc.h"
28 #include "sun4i_drv.h"
29 #include "sun4i_hdmi.h"
30 #include "sun4i_tcon.h"
32 static inline struct sun4i_hdmi *
33 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
35 return container_of(encoder, struct sun4i_hdmi,
39 static inline struct sun4i_hdmi *
40 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
42 return container_of(connector, struct sun4i_hdmi,
46 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
47 struct drm_display_mode *mode)
49 struct hdmi_avi_infoframe frame;
53 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
55 DRM_ERROR("Failed to get infoframes from mode\n");
59 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
61 DRM_ERROR("Failed to pack infoframes\n");
65 for (i = 0; i < sizeof(buffer); i++)
66 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
71 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
72 struct drm_crtc_state *crtc_state,
73 struct drm_connector_state *conn_state)
75 struct drm_display_mode *mode = &crtc_state->mode;
77 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
83 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
85 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
86 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
87 struct sun4i_tcon *tcon = crtc->tcon;
90 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
92 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
93 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
94 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
96 sun4i_tcon_channel_disable(tcon, 1);
99 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
101 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
102 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
103 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
104 struct sun4i_tcon *tcon = crtc->tcon;
107 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
109 sun4i_tcon_channel_enable(tcon, 1);
111 sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
112 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
113 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
114 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
116 val = SUN4I_HDMI_VID_CTRL_ENABLE;
117 if (hdmi->hdmi_monitor)
118 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
120 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
123 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
124 struct drm_display_mode *mode,
125 struct drm_display_mode *adjusted_mode)
127 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
128 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
129 struct sun4i_tcon *tcon = crtc->tcon;
133 sun4i_tcon1_mode_set(tcon, mode);
134 sun4i_tcon_set_mux(tcon, 1, encoder);
136 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
137 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
138 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
140 /* Set input sync enable */
141 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
142 hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
144 /* Setup timing registers */
145 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
146 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
147 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
149 x = mode->htotal - mode->hsync_start;
150 y = mode->vtotal - mode->vsync_start;
151 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
152 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
154 x = mode->hsync_start - mode->hdisplay;
155 y = mode->vsync_start - mode->vdisplay;
156 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
157 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
159 x = mode->hsync_end - mode->hsync_start;
160 y = mode->vsync_end - mode->vsync_start;
161 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
162 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
164 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
165 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
166 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
168 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
169 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
171 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
174 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
175 .atomic_check = sun4i_hdmi_atomic_check,
176 .disable = sun4i_hdmi_disable,
177 .enable = sun4i_hdmi_enable,
178 .mode_set = sun4i_hdmi_mode_set,
181 static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
182 .destroy = drm_encoder_cleanup,
185 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
187 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
191 edid = drm_get_edid(connector, hdmi->i2c);
195 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
196 DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
197 hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
199 drm_mode_connector_update_edid_property(connector, edid);
200 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
201 ret = drm_add_edid_modes(connector, edid);
207 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
208 .get_modes = sun4i_hdmi_get_modes,
211 static enum drm_connector_status
212 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
214 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
217 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
218 reg & SUN4I_HDMI_HPD_HIGH,
220 cec_phys_addr_invalidate(hdmi->cec_adap);
221 return connector_status_disconnected;
224 return connector_status_connected;
227 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
228 .detect = sun4i_hdmi_connector_detect,
229 .fill_modes = drm_helper_probe_single_connector_modes,
230 .destroy = drm_connector_cleanup,
231 .reset = drm_atomic_helper_connector_reset,
232 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
233 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
236 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
237 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
239 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
241 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
244 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
246 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
248 /* Start driving the CEC pin low */
249 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
252 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
254 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
257 * Stop driving the CEC pin, the pull up will take over
258 * unless another CEC device is driving the pin low.
260 writel(0, hdmi->base + SUN4I_HDMI_CEC);
263 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
264 .read = sun4i_hdmi_cec_pin_read,
265 .low = sun4i_hdmi_cec_pin_low,
266 .high = sun4i_hdmi_cec_pin_high,
270 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
273 struct platform_device *pdev = to_platform_device(dev);
274 struct drm_device *drm = data;
275 struct sun4i_drv *drv = drm->dev_private;
276 struct sun4i_hdmi *hdmi;
277 struct resource *res;
281 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
284 dev_set_drvdata(dev, hdmi);
288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289 hdmi->base = devm_ioremap_resource(dev, res);
290 if (IS_ERR(hdmi->base)) {
291 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
292 return PTR_ERR(hdmi->base);
295 hdmi->bus_clk = devm_clk_get(dev, "ahb");
296 if (IS_ERR(hdmi->bus_clk)) {
297 dev_err(dev, "Couldn't get the HDMI bus clock\n");
298 return PTR_ERR(hdmi->bus_clk);
300 clk_prepare_enable(hdmi->bus_clk);
302 hdmi->mod_clk = devm_clk_get(dev, "mod");
303 if (IS_ERR(hdmi->mod_clk)) {
304 dev_err(dev, "Couldn't get the HDMI mod clock\n");
305 ret = PTR_ERR(hdmi->mod_clk);
306 goto err_disable_bus_clk;
308 clk_prepare_enable(hdmi->mod_clk);
310 hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
311 if (IS_ERR(hdmi->pll0_clk)) {
312 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
313 ret = PTR_ERR(hdmi->pll0_clk);
314 goto err_disable_mod_clk;
317 hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
318 if (IS_ERR(hdmi->pll1_clk)) {
319 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
320 ret = PTR_ERR(hdmi->pll1_clk);
321 goto err_disable_mod_clk;
324 ret = sun4i_tmds_create(hdmi);
326 dev_err(dev, "Couldn't create the TMDS clock\n");
327 goto err_disable_mod_clk;
330 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
332 writel(SUN4I_HDMI_PAD_CTRL0_TXEN | SUN4I_HDMI_PAD_CTRL0_CKEN |
333 SUN4I_HDMI_PAD_CTRL0_PWENG | SUN4I_HDMI_PAD_CTRL0_PWEND |
334 SUN4I_HDMI_PAD_CTRL0_PWENC | SUN4I_HDMI_PAD_CTRL0_LDODEN |
335 SUN4I_HDMI_PAD_CTRL0_LDOCEN | SUN4I_HDMI_PAD_CTRL0_BIASEN,
336 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
339 * We can't just initialize the register there, we need to
340 * protect the clock bits that have already been read out and
341 * cached by the clock framework.
343 reg = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
344 reg &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
345 reg |= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
346 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
347 SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
348 SUN4I_HDMI_PAD_CTRL1_REG_DEN |
349 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
350 SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
351 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
352 SUN4I_HDMI_PAD_CTRL1_AMP_OPT;
353 writel(reg, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
355 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
356 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
357 reg |= SUN4I_HDMI_PLL_CTRL_VCO_S(8) | SUN4I_HDMI_PLL_CTRL_CS(7) |
358 SUN4I_HDMI_PLL_CTRL_CP_S(15) | SUN4I_HDMI_PLL_CTRL_S(7) |
359 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | SUN4I_HDMI_PLL_CTRL_SDIV2 |
360 SUN4I_HDMI_PLL_CTRL_LDO2_EN | SUN4I_HDMI_PLL_CTRL_LDO1_EN |
361 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | SUN4I_HDMI_PLL_CTRL_BWS |
362 SUN4I_HDMI_PLL_CTRL_PLL_EN;
363 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
365 ret = sun4i_hdmi_i2c_create(dev, hdmi);
367 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
368 goto err_disable_mod_clk;
371 drm_encoder_helper_add(&hdmi->encoder,
372 &sun4i_hdmi_helper_funcs);
373 ret = drm_encoder_init(drm,
376 DRM_MODE_ENCODER_TMDS,
379 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
380 goto err_del_i2c_adapter;
383 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
385 if (!hdmi->encoder.possible_crtcs) {
387 goto err_del_i2c_adapter;
390 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
391 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
392 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
393 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
394 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
396 goto err_cleanup_connector;
397 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
398 hdmi->base + SUN4I_HDMI_CEC);
401 drm_connector_helper_add(&hdmi->connector,
402 &sun4i_hdmi_connector_helper_funcs);
403 ret = drm_connector_init(drm, &hdmi->connector,
404 &sun4i_hdmi_connector_funcs,
405 DRM_MODE_CONNECTOR_HDMIA);
408 "Couldn't initialise the HDMI connector\n");
409 goto err_cleanup_connector;
412 /* There is no HPD interrupt, so we need to poll the controller */
413 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
414 DRM_CONNECTOR_POLL_DISCONNECT;
416 ret = cec_register_adapter(hdmi->cec_adap, dev);
418 goto err_cleanup_connector;
419 drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
423 err_cleanup_connector:
424 cec_delete_adapter(hdmi->cec_adap);
425 drm_encoder_cleanup(&hdmi->encoder);
427 i2c_del_adapter(hdmi->i2c);
429 clk_disable_unprepare(hdmi->mod_clk);
431 clk_disable_unprepare(hdmi->bus_clk);
435 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
438 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
440 cec_unregister_adapter(hdmi->cec_adap);
441 drm_connector_cleanup(&hdmi->connector);
442 drm_encoder_cleanup(&hdmi->encoder);
443 i2c_del_adapter(hdmi->i2c);
444 clk_disable_unprepare(hdmi->mod_clk);
445 clk_disable_unprepare(hdmi->bus_clk);
448 static const struct component_ops sun4i_hdmi_ops = {
449 .bind = sun4i_hdmi_bind,
450 .unbind = sun4i_hdmi_unbind,
453 static int sun4i_hdmi_probe(struct platform_device *pdev)
455 return component_add(&pdev->dev, &sun4i_hdmi_ops);
458 static int sun4i_hdmi_remove(struct platform_device *pdev)
460 component_del(&pdev->dev, &sun4i_hdmi_ops);
465 static const struct of_device_id sun4i_hdmi_of_table[] = {
466 { .compatible = "allwinner,sun5i-a10s-hdmi" },
469 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
471 static struct platform_driver sun4i_hdmi_driver = {
472 .probe = sun4i_hdmi_probe,
473 .remove = sun4i_hdmi_remove,
475 .name = "sun4i-hdmi",
476 .of_match_table = sun4i_hdmi_of_table,
479 module_platform_driver(sun4i_hdmi_driver);
481 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
482 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
483 MODULE_LICENSE("GPL");