2 * Copyright (C) 2016 Free Electrons
3 * Copyright (C) 2016 NextThing Co
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
16 #include "sun4i_tcon.h"
20 struct regmap *regmap;
23 static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
25 return container_of(hw, struct sun4i_dclk, hw);
28 static void sun4i_dclk_disable(struct clk_hw *hw)
30 struct sun4i_dclk *dclk = hw_to_dclk(hw);
32 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
33 BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
36 static int sun4i_dclk_enable(struct clk_hw *hw)
38 struct sun4i_dclk *dclk = hw_to_dclk(hw);
40 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
41 BIT(SUN4I_TCON0_DCLK_GATE_BIT),
42 BIT(SUN4I_TCON0_DCLK_GATE_BIT));
45 static int sun4i_dclk_is_enabled(struct clk_hw *hw)
47 struct sun4i_dclk *dclk = hw_to_dclk(hw);
50 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
52 return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
55 static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
56 unsigned long parent_rate)
58 struct sun4i_dclk *dclk = hw_to_dclk(hw);
61 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
63 val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
64 val &= SUN4I_TCON0_DCLK_DIV_WIDTH;
69 return parent_rate / val;
72 static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
73 unsigned long *parent_rate)
75 unsigned long best_parent = 0;
79 for (i = 6; i < 127; i++) {
80 unsigned long ideal = rate * i;
81 unsigned long rounded;
83 rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
86 if (rounded == ideal) {
87 best_parent = rounded;
92 if ((rounded < ideal) && (rounded > best_parent)) {
93 best_parent = rounded;
99 *parent_rate = best_parent;
101 return best_parent / best_div;
104 static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
105 unsigned long parent_rate)
107 struct sun4i_dclk *dclk = hw_to_dclk(hw);
108 u8 div = parent_rate / rate;
110 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
114 static int sun4i_dclk_get_phase(struct clk_hw *hw)
116 struct sun4i_dclk *dclk = hw_to_dclk(hw);
119 regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
127 static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
129 struct sun4i_dclk *dclk = hw_to_dclk(hw);
131 regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
138 static const struct clk_ops sun4i_dclk_ops = {
139 .disable = sun4i_dclk_disable,
140 .enable = sun4i_dclk_enable,
141 .is_enabled = sun4i_dclk_is_enabled,
143 .recalc_rate = sun4i_dclk_recalc_rate,
144 .round_rate = sun4i_dclk_round_rate,
145 .set_rate = sun4i_dclk_set_rate,
147 .get_phase = sun4i_dclk_get_phase,
148 .set_phase = sun4i_dclk_set_phase,
151 int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
153 const char *clk_name, *parent_name;
154 struct clk_init_data init;
155 struct sun4i_dclk *dclk;
158 parent_name = __clk_get_name(tcon->sclk0);
159 ret = of_property_read_string_index(dev->of_node,
160 "clock-output-names", 0,
165 dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
169 init.name = clk_name;
170 init.ops = &sun4i_dclk_ops;
171 init.parent_names = &parent_name;
172 init.num_parents = 1;
173 init.flags = CLK_SET_RATE_PARENT;
175 dclk->regmap = tcon->regs;
176 dclk->hw.init = &init;
178 tcon->dclk = clk_register(dev, &dclk->hw);
179 if (IS_ERR(tcon->dclk))
180 return PTR_ERR(tcon->dclk);
184 EXPORT_SYMBOL(sun4i_dclk_create);
186 int sun4i_dclk_free(struct sun4i_tcon *tcon)
188 clk_unregister(tcon->dclk);
191 EXPORT_SYMBOL(sun4i_dclk_free);