2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * Vincent Abriou <vincent.abriou@st.com>
6 * for STMicroelectronics.
7 * License terms: GNU General Public License (GPL), version 2
10 #include <linux/module.h>
11 #include <linux/notifier.h>
12 #include <linux/platform_device.h>
18 #define VTG_MODE_MASTER 0
19 #define VTG_MODE_SLAVE_BY_EXT0 1
21 /* registers offset */
22 #define VTG_MODE 0x0000
23 #define VTG_CLKLN 0x0008
24 #define VTG_HLFLN 0x000C
25 #define VTG_DRST_AUTOC 0x0010
26 #define VTG_VID_TFO 0x0040
27 #define VTG_VID_TFS 0x0044
28 #define VTG_VID_BFO 0x0048
29 #define VTG_VID_BFS 0x004C
31 #define VTG_HOST_ITS 0x0078
32 #define VTG_HOST_ITS_BCLR 0x007C
33 #define VTG_HOST_ITM_BCLR 0x0088
34 #define VTG_HOST_ITM_BSET 0x008C
36 #define VTG_H_HD_1 0x00C0
37 #define VTG_TOP_V_VD_1 0x00C4
38 #define VTG_BOT_V_VD_1 0x00C8
39 #define VTG_TOP_V_HD_1 0x00CC
40 #define VTG_BOT_V_HD_1 0x00D0
42 #define VTG_H_HD_2 0x00E0
43 #define VTG_TOP_V_VD_2 0x00E4
44 #define VTG_BOT_V_VD_2 0x00E8
45 #define VTG_TOP_V_HD_2 0x00EC
46 #define VTG_BOT_V_HD_2 0x00F0
48 #define VTG_H_HD_3 0x0100
49 #define VTG_TOP_V_VD_3 0x0104
50 #define VTG_BOT_V_VD_3 0x0108
51 #define VTG_TOP_V_HD_3 0x010C
52 #define VTG_BOT_V_HD_3 0x0110
54 #define VTG_H_HD_4 0x0120
55 #define VTG_TOP_V_VD_4 0x0124
56 #define VTG_BOT_V_VD_4 0x0128
57 #define VTG_TOP_V_HD_4 0x012c
58 #define VTG_BOT_V_HD_4 0x0130
60 #define VTG_IRQ_BOTTOM BIT(0)
61 #define VTG_IRQ_TOP BIT(1)
62 #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
64 /* Delay introduced by the HDMI in nb of pixel */
65 #define HDMI_DELAY (5)
67 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
68 #define AWG_DELAY_HD (-9)
69 #define AWG_DELAY_ED (-8)
70 #define AWG_DELAY_SD (-7)
72 LIST_HEAD(vtg_lookup);
75 * STI VTG register offset structure
77 *@h_hd: stores the VTG_H_HD_x register offset
78 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
79 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
80 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
81 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
83 struct sti_vtg_regs_offs {
91 #define VTG_MAX_SYNC_OUTPUT 4
92 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
94 VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
96 VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
98 VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
100 VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
104 * STI VTG synchronisation parameters structure
106 *@hsync: sample number falling and rising edge
107 *@vsync_line_top: vertical top field line number falling and rising edge
108 *@vsync_line_bot: vertical bottom field line number falling and rising edge
109 *@vsync_off_top: vertical top field sample number rising and falling edge
110 *@vsync_off_bot: vertical bottom field sample number rising and falling edge
112 struct sti_vtg_sync_params {
123 * @dev: pointer to device driver
125 * @regs: register mapping
126 * @sync_params: synchronisation parameters used to generate timings
128 * @irq_status: store the IRQ status value
129 * @notifier_list: notifier callback
130 * @crtc: the CRTC for vblank event
132 * @link: List node to link the structure in lookup list
136 struct device_node *np;
138 struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
141 struct raw_notifier_head notifier_list;
142 struct drm_crtc *crtc;
143 struct sti_vtg *slave;
144 struct list_head link;
147 static void vtg_register(struct sti_vtg *vtg)
149 list_add_tail(&vtg->link, &vtg_lookup);
152 struct sti_vtg *of_vtg_find(struct device_node *np)
156 list_for_each_entry(vtg, &vtg_lookup, link) {
163 static void vtg_reset(struct sti_vtg *vtg)
165 /* reset slave and then master */
167 vtg_reset(vtg->slave);
169 writel(1, vtg->regs + VTG_DRST_AUTOC);
172 static void vtg_set_output_window(void __iomem *regs,
173 const struct drm_display_mode *mode)
175 u32 video_top_field_start;
176 u32 video_top_field_stop;
177 u32 video_bottom_field_start;
178 u32 video_bottom_field_stop;
179 u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
180 u32 ystart = sti_vtg_get_line_number(*mode, 0);
181 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
182 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
184 /* Set output window to fit the display mode selected */
185 video_top_field_start = (ystart << 16) | xstart;
186 video_top_field_stop = (ystop << 16) | xstop;
188 /* Only progressive supported for now */
189 video_bottom_field_start = video_top_field_start;
190 video_bottom_field_stop = video_top_field_stop;
192 writel(video_top_field_start, regs + VTG_VID_TFO);
193 writel(video_top_field_stop, regs + VTG_VID_TFS);
194 writel(video_bottom_field_start, regs + VTG_VID_BFO);
195 writel(video_bottom_field_stop, regs + VTG_VID_BFS);
198 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
200 const struct drm_display_mode *mode)
202 long clocksperline, start, stop;
203 u32 risesync_top, fallsync_top;
204 u32 risesync_offs_top, fallsync_offs_top;
206 clocksperline = mode->htotal;
208 /* Get the hsync position */
210 stop = mode->hsync_end - mode->hsync_start;
216 start += clocksperline;
217 else if (start >= clocksperline)
218 start -= clocksperline;
221 stop += clocksperline;
222 else if (stop >= clocksperline)
223 stop -= clocksperline;
225 sync->hsync = (stop << 16) | start;
227 /* Get the vsync position */
230 fallsync_top = risesync_top;
231 fallsync_top += mode->vsync_end - mode->vsync_start;
233 fallsync_offs_top = (u32)delay;
234 risesync_offs_top = (u32)delay;
236 risesync_top = mode->vtotal;
237 fallsync_top = mode->vsync_end - mode->vsync_start;
239 fallsync_offs_top = clocksperline + delay;
240 risesync_offs_top = clocksperline + delay;
243 sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
244 sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
246 /* Only progressive supported for now */
247 sync->vsync_line_bot = sync->vsync_line_top;
248 sync->vsync_off_bot = sync->vsync_off_top;
251 static void vtg_set_mode(struct sti_vtg *vtg,
253 struct sti_vtg_sync_params *sync,
254 const struct drm_display_mode *mode)
259 vtg_set_mode(vtg->slave, VTG_MODE_SLAVE_BY_EXT0,
260 vtg->sync_params, mode);
262 /* Set the number of clock cycles per line */
263 writel(mode->htotal, vtg->regs + VTG_CLKLN);
265 /* Set Half Line Per Field (only progressive supported for now) */
266 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
268 /* Program output window */
269 vtg_set_output_window(vtg->regs, mode);
271 /* Set hsync and vsync position for HDMI */
272 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
274 /* Set hsync and vsync position for HD DCS */
275 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
277 /* Set hsync and vsync position for HDF */
278 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
280 /* Set hsync and vsync position for DVO */
281 vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], 0, mode);
283 /* Progam the syncs outputs */
284 for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
285 writel(sync[i].hsync,
286 vtg->regs + vtg_regs_offs[i].h_hd);
287 writel(sync[i].vsync_line_top,
288 vtg->regs + vtg_regs_offs[i].top_v_vd);
289 writel(sync[i].vsync_line_bot,
290 vtg->regs + vtg_regs_offs[i].bot_v_vd);
291 writel(sync[i].vsync_off_top,
292 vtg->regs + vtg_regs_offs[i].top_v_hd);
293 writel(sync[i].vsync_off_bot,
294 vtg->regs + vtg_regs_offs[i].bot_v_hd);
298 writel(type, vtg->regs + VTG_MODE);
301 static void vtg_enable_irq(struct sti_vtg *vtg)
303 /* clear interrupt status and mask */
304 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
305 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
306 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
309 void sti_vtg_set_config(struct sti_vtg *vtg,
310 const struct drm_display_mode *mode)
312 /* write configuration */
313 vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
317 /* enable irq for the vtg vblank synchro */
319 vtg_enable_irq(vtg->slave);
325 * sti_vtg_get_line_number
327 * @mode: display mode to be used
330 * Return the line number according to the display mode taking
331 * into account the Sync and Back Porch information.
332 * Video frame line numbers start at 1, y starts at 0.
333 * In interlaced modes the start line is the field line number of the odd
334 * field, but y is still defined as a progressive frame.
336 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
338 u32 start_line = mode.vtotal - mode.vsync_start + 1;
340 if (mode.flags & DRM_MODE_FLAG_INTERLACE)
343 return start_line + y;
347 * sti_vtg_get_pixel_number
349 * @mode: display mode to be used
352 * Return the pixel number according to the display mode taking
353 * into account the Sync and Back Porch information.
354 * Pixels are counted from 0.
356 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
358 return mode.htotal - mode.hsync_start + x;
361 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
362 struct drm_crtc *crtc)
365 return sti_vtg_register_client(vtg->slave, nb, crtc);
368 return raw_notifier_chain_register(&vtg->notifier_list, nb);
371 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
374 return sti_vtg_unregister_client(vtg->slave, nb);
376 return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
379 static irqreturn_t vtg_irq_thread(int irq, void *arg)
381 struct sti_vtg *vtg = arg;
384 event = (vtg->irq_status & VTG_IRQ_TOP) ?
385 VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
387 raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
392 static irqreturn_t vtg_irq(int irq, void *arg)
394 struct sti_vtg *vtg = arg;
396 vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
398 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
400 /* force sync bus write */
401 readl(vtg->regs + VTG_HOST_ITS);
403 return IRQ_WAKE_THREAD;
406 static int vtg_probe(struct platform_device *pdev)
408 struct device *dev = &pdev->dev;
409 struct device_node *np;
411 struct resource *res;
414 vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
419 vtg->np = pdev->dev.of_node;
421 /* Get Memory ressources */
422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
424 DRM_ERROR("Get memory resource failed\n");
427 vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
429 np = of_parse_phandle(pdev->dev.of_node, "st,slave", 0);
431 vtg->slave = of_vtg_find(np);
434 return -EPROBE_DEFER;
436 vtg->irq = platform_get_irq(pdev, 0);
437 if (IS_ERR_VALUE(vtg->irq)) {
438 DRM_ERROR("Failed to get VTG interrupt\n");
442 RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
444 ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
445 vtg_irq_thread, IRQF_ONESHOT,
447 if (IS_ERR_VALUE(ret)) {
448 DRM_ERROR("Failed to register VTG interrupt\n");
454 platform_set_drvdata(pdev, vtg);
456 DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev));
461 static int vtg_remove(struct platform_device *pdev)
466 static const struct of_device_id vtg_of_match[] = {
467 { .compatible = "st,vtg", },
470 MODULE_DEVICE_TABLE(of, vtg_of_match);
472 struct platform_driver sti_vtg_driver = {
475 .owner = THIS_MODULE,
476 .of_match_table = vtg_of_match,
479 .remove = vtg_remove,
482 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
483 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
484 MODULE_LICENSE("GPL");