2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
36 #include <linux/reset.h>
37 #include <linux/delay.h>
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_gem.h"
41 #include "rockchip_drm_fb.h"
42 #include "rockchip_drm_psr.h"
43 #include "rockchip_drm_vop.h"
45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, true)
48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
49 vop_mask_write(x, off, mask, shift, v, write_mask, false)
51 #define REG_SET(x, base, reg, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, \
53 reg.mask, reg.shift, v, reg.write_mask)
54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
55 __REG_SET_##mode(x, base + reg.offset, \
56 mask, reg.shift, v, reg.write_mask)
58 #define VOP_WIN_SET(x, win, name, v) \
59 REG_SET(x, win->base, win->phy->name, v, RELAXED)
60 #define VOP_SCL_SET(x, win, name, v) \
61 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
62 #define VOP_SCL_SET_EXT(x, win, name, v) \
63 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
64 #define VOP_CTRL_SET(x, name, v) \
65 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
67 #define VOP_INTR_GET(vop, name) \
68 vop_read_reg(vop, 0, &vop->data->ctrl->name)
70 #define VOP_INTR_SET(vop, name, mask, v) \
71 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
74 int i, reg = 0, mask = 0; \
75 for (i = 0; i < vop->data->intr->nintrs; i++) { \
76 if (vop->data->intr->intrs[i] & type) { \
81 VOP_INTR_SET(vop, name, mask, reg); \
83 #define VOP_INTR_GET_TYPE(vop, name, type) \
84 vop_get_intr_type(vop, &vop->data->intr->name, type)
86 #define VOP_WIN_GET(x, win, name) \
87 vop_read_reg(x, win->base, &win->phy->name)
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
92 #define to_vop(x) container_of(x, struct vop, crtc)
93 #define to_vop_win(x) container_of(x, struct vop_win, base)
100 struct drm_plane base;
101 const struct vop_win_data *data;
106 struct drm_crtc crtc;
108 struct drm_device *drm_dev;
111 /* mutex vsync_ work */
112 struct mutex vsync_mutex;
113 bool vsync_work_pending;
114 struct completion dsp_hold_completion;
116 /* protected by dev->event_lock */
117 struct drm_pending_vblank_event *event;
119 struct drm_flip_work fb_unref_work;
120 unsigned long pending;
122 struct completion line_flag_completion;
124 const struct vop_data *data;
129 /* physical map length of vop register */
132 /* one time only one process allowed to config the register */
134 /* lock vop irq reg */
143 /* vop share memory frequency */
147 struct reset_control *dclk_rst;
149 struct vop_win win[];
152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
154 writel(v, vop->regs + offset);
155 vop->regsbak[offset >> 2] = v;
158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
160 return readl(vop->regs + offset);
163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
164 const struct vop_reg *reg)
166 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
169 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
170 uint32_t mask, uint32_t shift, uint32_t v,
171 bool write_mask, bool relaxed)
177 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
179 uint32_t cached_val = vop->regsbak[offset >> 2];
181 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
182 vop->regsbak[offset >> 2] = v;
186 writel_relaxed(v, vop->regs + offset);
188 writel(v, vop->regs + offset);
191 static inline uint32_t vop_get_intr_type(struct vop *vop,
192 const struct vop_reg *reg, int type)
195 uint32_t regs = vop_read_reg(vop, 0, reg);
197 for (i = 0; i < vop->data->intr->nintrs; i++) {
198 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
199 ret |= vop->data->intr->intrs[i];
205 static inline void vop_cfg_done(struct vop *vop)
207 VOP_CTRL_SET(vop, cfg_done, 1);
210 static bool has_rb_swapped(uint32_t format)
213 case DRM_FORMAT_XBGR8888:
214 case DRM_FORMAT_ABGR8888:
215 case DRM_FORMAT_BGR888:
216 case DRM_FORMAT_BGR565:
223 static enum vop_data_format vop_convert_format(uint32_t format)
226 case DRM_FORMAT_XRGB8888:
227 case DRM_FORMAT_ARGB8888:
228 case DRM_FORMAT_XBGR8888:
229 case DRM_FORMAT_ABGR8888:
230 return VOP_FMT_ARGB8888;
231 case DRM_FORMAT_RGB888:
232 case DRM_FORMAT_BGR888:
233 return VOP_FMT_RGB888;
234 case DRM_FORMAT_RGB565:
235 case DRM_FORMAT_BGR565:
236 return VOP_FMT_RGB565;
237 case DRM_FORMAT_NV12:
238 return VOP_FMT_YUV420SP;
239 case DRM_FORMAT_NV16:
240 return VOP_FMT_YUV422SP;
241 case DRM_FORMAT_NV24:
242 return VOP_FMT_YUV444SP;
244 DRM_ERROR("unsupported format[%08x]\n", format);
249 static bool is_yuv_support(uint32_t format)
252 case DRM_FORMAT_NV12:
253 case DRM_FORMAT_NV16:
254 case DRM_FORMAT_NV24:
261 static bool is_alpha_support(uint32_t format)
264 case DRM_FORMAT_ARGB8888:
265 case DRM_FORMAT_ABGR8888:
272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
273 uint32_t dst, bool is_horizontal,
274 int vsu_mode, int *vskiplines)
276 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279 if (mode == SCALE_UP)
280 val = GET_SCL_FT_BIC(src, dst);
281 else if (mode == SCALE_DOWN)
282 val = GET_SCL_FT_BILI_DN(src, dst);
284 if (mode == SCALE_UP) {
285 if (vsu_mode == SCALE_UP_BIL)
286 val = GET_SCL_FT_BILI_UP(src, dst);
288 val = GET_SCL_FT_BIC(src, dst);
289 } else if (mode == SCALE_DOWN) {
291 *vskiplines = scl_get_vskiplines(src, dst);
292 val = scl_get_bili_dn_vskip(src, dst,
295 val = GET_SCL_FT_BILI_DN(src, dst);
303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
304 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
305 uint32_t dst_h, uint32_t pixel_format)
307 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
308 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
309 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
310 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
311 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
312 bool is_yuv = is_yuv_support(pixel_format);
313 uint16_t cbcr_src_w = src_w / hsub;
314 uint16_t cbcr_src_h = src_h / vsub;
321 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
325 if (!win->phy->scl->ext) {
326 VOP_SCL_SET(vop, win, scale_yrgb_x,
327 scl_cal_scale2(src_w, dst_w));
328 VOP_SCL_SET(vop, win, scale_yrgb_y,
329 scl_cal_scale2(src_h, dst_h));
331 VOP_SCL_SET(vop, win, scale_cbcr_x,
332 scl_cal_scale2(cbcr_src_w, dst_w));
333 VOP_SCL_SET(vop, win, scale_cbcr_y,
334 scl_cal_scale2(cbcr_src_h, dst_h));
339 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
340 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
343 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
344 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
345 if (cbcr_hor_scl_mode == SCALE_DOWN)
346 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
348 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
350 if (yrgb_hor_scl_mode == SCALE_DOWN)
351 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
353 lb_mode = scl_vop_cal_lb_mode(src_w, false);
356 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
357 if (lb_mode == LB_RGB_3840X2) {
358 if (yrgb_ver_scl_mode != SCALE_NONE) {
359 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
362 if (cbcr_ver_scl_mode != SCALE_NONE) {
363 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
366 vsu_mode = SCALE_UP_BIL;
367 } else if (lb_mode == LB_RGB_2560X4) {
368 vsu_mode = SCALE_UP_BIL;
370 vsu_mode = SCALE_UP_BIC;
373 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
375 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
376 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
377 false, vsu_mode, &vskiplines);
378 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
380 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
381 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
383 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
384 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
385 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
386 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
387 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
389 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
390 dst_w, true, 0, NULL);
391 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
392 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
393 dst_h, false, vsu_mode, &vskiplines);
394 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
396 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
397 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
398 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
399 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
400 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
401 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
402 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
410 if (WARN_ON(!vop->is_enabled))
413 spin_lock_irqsave(&vop->irq_lock, flags);
415 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
416 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
418 spin_unlock_irqrestore(&vop->irq_lock, flags);
421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
425 if (WARN_ON(!vop->is_enabled))
428 spin_lock_irqsave(&vop->irq_lock, flags);
430 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
432 spin_unlock_irqrestore(&vop->irq_lock, flags);
436 * (1) each frame starts at the start of the Vsync pulse which is signaled by
437 * the "FRAME_SYNC" interrupt.
438 * (2) the active data region of each frame ends at dsp_vact_end
439 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
440 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
442 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
444 * LINE_FLAG -------------------------------+
448 * | Vsync | Vbp | Vactive | Vfp |
452 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
453 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
454 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
455 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
457 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
459 uint32_t line_flag_irq;
462 spin_lock_irqsave(&vop->irq_lock, flags);
464 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
466 spin_unlock_irqrestore(&vop->irq_lock, flags);
468 return !!line_flag_irq;
471 static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
475 if (WARN_ON(!vop->is_enabled))
478 spin_lock_irqsave(&vop->irq_lock, flags);
480 VOP_CTRL_SET(vop, line_flag_num[0], line_num);
481 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
482 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
484 spin_unlock_irqrestore(&vop->irq_lock, flags);
487 static void vop_line_flag_irq_disable(struct vop *vop)
491 if (WARN_ON(!vop->is_enabled))
494 spin_lock_irqsave(&vop->irq_lock, flags);
496 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
498 spin_unlock_irqrestore(&vop->irq_lock, flags);
501 static int vop_enable(struct drm_crtc *crtc)
503 struct vop *vop = to_vop(crtc);
506 ret = pm_runtime_get_sync(vop->dev);
508 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
512 ret = clk_enable(vop->hclk);
513 if (WARN_ON(ret < 0))
514 goto err_put_pm_runtime;
516 ret = clk_enable(vop->dclk);
517 if (WARN_ON(ret < 0))
518 goto err_disable_hclk;
520 ret = clk_enable(vop->aclk);
521 if (WARN_ON(ret < 0))
522 goto err_disable_dclk;
525 * Slave iommu shares power, irq and clock with vop. It was associated
526 * automatically with this master device via common driver code.
527 * Now that we have enabled the clock we attach it to the shared drm
530 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
532 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
533 goto err_disable_aclk;
536 memcpy(vop->regs, vop->regsbak, vop->len);
540 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
542 vop->is_enabled = true;
544 spin_lock(&vop->reg_lock);
546 VOP_CTRL_SET(vop, standby, 0);
548 spin_unlock(&vop->reg_lock);
550 enable_irq(vop->irq);
552 drm_crtc_vblank_on(crtc);
557 clk_disable(vop->aclk);
559 clk_disable(vop->dclk);
561 clk_disable(vop->hclk);
563 pm_runtime_put_sync(vop->dev);
567 static void vop_crtc_disable(struct drm_crtc *crtc)
569 struct vop *vop = to_vop(crtc);
574 rockchip_drm_psr_deactivate(&vop->crtc);
577 * We need to make sure that all windows are disabled before we
578 * disable that crtc. Otherwise we might try to scan from a destroyed
581 for (i = 0; i < vop->data->win_size; i++) {
582 struct vop_win *vop_win = &vop->win[i];
583 const struct vop_win_data *win = vop_win->data;
585 spin_lock(&vop->reg_lock);
586 VOP_WIN_SET(vop, win, enable, 0);
587 spin_unlock(&vop->reg_lock);
592 drm_crtc_vblank_off(crtc);
595 * Vop standby will take effect at end of current frame,
596 * if dsp hold valid irq happen, it means standby complete.
598 * we must wait standby complete when we want to disable aclk,
599 * if not, memory bus maybe dead.
601 reinit_completion(&vop->dsp_hold_completion);
602 vop_dsp_hold_valid_irq_enable(vop);
604 spin_lock(&vop->reg_lock);
606 VOP_CTRL_SET(vop, standby, 1);
608 spin_unlock(&vop->reg_lock);
610 wait_for_completion(&vop->dsp_hold_completion);
612 vop_dsp_hold_valid_irq_disable(vop);
614 disable_irq(vop->irq);
616 vop->is_enabled = false;
619 * vop standby complete, so iommu detach is safe.
621 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
623 clk_disable(vop->dclk);
624 clk_disable(vop->aclk);
625 clk_disable(vop->hclk);
626 pm_runtime_put(vop->dev);
628 if (crtc->state->event && !crtc->state->active) {
629 spin_lock_irq(&crtc->dev->event_lock);
630 drm_crtc_send_vblank_event(crtc, crtc->state->event);
631 spin_unlock_irq(&crtc->dev->event_lock);
633 crtc->state->event = NULL;
637 static void vop_plane_destroy(struct drm_plane *plane)
639 drm_plane_cleanup(plane);
642 static int vop_plane_atomic_check(struct drm_plane *plane,
643 struct drm_plane_state *state)
645 struct drm_crtc *crtc = state->crtc;
646 struct drm_crtc_state *crtc_state;
647 struct drm_framebuffer *fb = state->fb;
648 struct vop_win *vop_win = to_vop_win(plane);
649 const struct vop_win_data *win = vop_win->data;
651 struct drm_rect clip;
652 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
653 DRM_PLANE_HELPER_NO_SCALING;
654 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
655 DRM_PLANE_HELPER_NO_SCALING;
660 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
661 if (WARN_ON(!crtc_state))
666 clip.x2 = crtc_state->adjusted_mode.hdisplay;
667 clip.y2 = crtc_state->adjusted_mode.vdisplay;
669 ret = drm_plane_helper_check_state(state, &clip,
670 min_scale, max_scale,
678 ret = vop_convert_format(fb->format->format);
683 * Src.x1 can be odd when do clip, but yuv plane start point
684 * need align with 2 pixel.
686 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
692 static void vop_plane_atomic_disable(struct drm_plane *plane,
693 struct drm_plane_state *old_state)
695 struct vop_win *vop_win = to_vop_win(plane);
696 const struct vop_win_data *win = vop_win->data;
697 struct vop *vop = to_vop(old_state->crtc);
699 if (!old_state->crtc)
702 spin_lock(&vop->reg_lock);
704 VOP_WIN_SET(vop, win, enable, 0);
706 spin_unlock(&vop->reg_lock);
709 static void vop_plane_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
712 struct drm_plane_state *state = plane->state;
713 struct drm_crtc *crtc = state->crtc;
714 struct vop_win *vop_win = to_vop_win(plane);
715 const struct vop_win_data *win = vop_win->data;
716 struct vop *vop = to_vop(state->crtc);
717 struct drm_framebuffer *fb = state->fb;
718 unsigned int actual_w, actual_h;
719 unsigned int dsp_stx, dsp_sty;
720 uint32_t act_info, dsp_info, dsp_st;
721 struct drm_rect *src = &state->src;
722 struct drm_rect *dest = &state->dst;
723 struct drm_gem_object *obj, *uv_obj;
724 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
725 unsigned long offset;
732 * can't update plane when vop is disabled.
737 if (WARN_ON(!vop->is_enabled))
740 if (!state->visible) {
741 vop_plane_atomic_disable(plane, old_state);
745 obj = rockchip_fb_get_gem_obj(fb, 0);
746 rk_obj = to_rockchip_obj(obj);
748 actual_w = drm_rect_width(src) >> 16;
749 actual_h = drm_rect_height(src) >> 16;
750 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
752 dsp_info = (drm_rect_height(dest) - 1) << 16;
753 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
755 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
756 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
757 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
759 offset = (src->x1 >> 16) * fb->format->cpp[0];
760 offset += (src->y1 >> 16) * fb->pitches[0];
761 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
763 format = vop_convert_format(fb->format->format);
765 spin_lock(&vop->reg_lock);
767 VOP_WIN_SET(vop, win, format, format);
768 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
769 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
770 if (is_yuv_support(fb->format->format)) {
771 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
772 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
773 int bpp = fb->format->cpp[1];
775 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
776 rk_uv_obj = to_rockchip_obj(uv_obj);
778 offset = (src->x1 >> 16) * bpp / hsub;
779 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
781 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
782 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
783 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
787 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
788 drm_rect_width(dest), drm_rect_height(dest),
791 VOP_WIN_SET(vop, win, act_info, act_info);
792 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
793 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
795 rb_swap = has_rb_swapped(fb->format->format);
796 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
798 if (is_alpha_support(fb->format->format)) {
799 VOP_WIN_SET(vop, win, dst_alpha_ctl,
800 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
801 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
802 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
803 SRC_BLEND_M0(ALPHA_PER_PIX) |
804 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
805 SRC_FACTOR_M0(ALPHA_ONE);
806 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
808 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
811 VOP_WIN_SET(vop, win, enable, 1);
812 spin_unlock(&vop->reg_lock);
815 static const struct drm_plane_helper_funcs plane_helper_funcs = {
816 .atomic_check = vop_plane_atomic_check,
817 .atomic_update = vop_plane_atomic_update,
818 .atomic_disable = vop_plane_atomic_disable,
821 static const struct drm_plane_funcs vop_plane_funcs = {
822 .update_plane = drm_atomic_helper_update_plane,
823 .disable_plane = drm_atomic_helper_disable_plane,
824 .destroy = vop_plane_destroy,
825 .reset = drm_atomic_helper_plane_reset,
826 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
827 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
830 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
832 struct vop *vop = to_vop(crtc);
835 if (WARN_ON(!vop->is_enabled))
838 spin_lock_irqsave(&vop->irq_lock, flags);
840 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
841 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
843 spin_unlock_irqrestore(&vop->irq_lock, flags);
848 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
850 struct vop *vop = to_vop(crtc);
853 if (WARN_ON(!vop->is_enabled))
856 spin_lock_irqsave(&vop->irq_lock, flags);
858 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
860 spin_unlock_irqrestore(&vop->irq_lock, flags);
863 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
864 const struct drm_display_mode *mode,
865 struct drm_display_mode *adjusted_mode)
867 struct vop *vop = to_vop(crtc);
869 adjusted_mode->clock =
870 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
875 static void vop_crtc_enable(struct drm_crtc *crtc)
877 struct vop *vop = to_vop(crtc);
878 const struct vop_data *vop_data = vop->data;
879 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
880 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
881 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
882 u16 hdisplay = adjusted_mode->hdisplay;
883 u16 htotal = adjusted_mode->htotal;
884 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
885 u16 hact_end = hact_st + hdisplay;
886 u16 vdisplay = adjusted_mode->vdisplay;
887 u16 vtotal = adjusted_mode->vtotal;
888 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
889 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
890 u16 vact_end = vact_st + vdisplay;
891 uint32_t pin_pol, val;
896 ret = vop_enable(crtc);
898 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
903 * If dclk rate is zero, mean that scanout is stop,
904 * we don't need wait any more.
906 if (clk_get_rate(vop->dclk)) {
908 * Rk3288 vop timing register is immediately, when configure
909 * display timing on display time, may cause tearing.
911 * Vop standby will take effect at end of current frame,
912 * if dsp hold valid irq happen, it means standby complete.
915 * standby and wait complete --> |----
919 * configure display timing --> |
924 reinit_completion(&vop->dsp_hold_completion);
925 vop_dsp_hold_valid_irq_enable(vop);
927 spin_lock(&vop->reg_lock);
929 VOP_CTRL_SET(vop, standby, 1);
931 spin_unlock(&vop->reg_lock);
933 wait_for_completion(&vop->dsp_hold_completion);
935 vop_dsp_hold_valid_irq_disable(vop);
938 pin_pol = BIT(DCLK_INVERT);
939 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
940 BIT(HSYNC_POSITIVE) : 0;
941 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
942 BIT(VSYNC_POSITIVE) : 0;
943 VOP_CTRL_SET(vop, pin_pol, pin_pol);
945 switch (s->output_type) {
946 case DRM_MODE_CONNECTOR_LVDS:
947 VOP_CTRL_SET(vop, rgb_en, 1);
948 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
950 case DRM_MODE_CONNECTOR_eDP:
951 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
952 VOP_CTRL_SET(vop, edp_en, 1);
954 case DRM_MODE_CONNECTOR_HDMIA:
955 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
956 VOP_CTRL_SET(vop, hdmi_en, 1);
958 case DRM_MODE_CONNECTOR_DSI:
959 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
960 VOP_CTRL_SET(vop, mipi_en, 1);
962 case DRM_MODE_CONNECTOR_DisplayPort:
963 pin_pol &= ~BIT(DCLK_INVERT);
964 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
965 VOP_CTRL_SET(vop, dp_en, 1);
968 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
973 * if vop is not support RGB10 output, need force RGB10 to RGB888.
975 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
976 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
977 s->output_mode = ROCKCHIP_OUT_MODE_P888;
978 VOP_CTRL_SET(vop, out_mode, s->output_mode);
980 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
983 VOP_CTRL_SET(vop, hact_st_end, val);
984 VOP_CTRL_SET(vop, hpost_st_end, val);
986 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
989 VOP_CTRL_SET(vop, vact_st_end, val);
990 VOP_CTRL_SET(vop, vpost_st_end, val);
992 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
994 VOP_CTRL_SET(vop, standby, 0);
996 rockchip_drm_psr_activate(&vop->crtc);
999 static bool vop_fs_irq_is_pending(struct vop *vop)
1001 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1004 static void vop_wait_for_irq_handler(struct vop *vop)
1010 * Spin until frame start interrupt status bit goes low, which means
1011 * that interrupt handler was invoked and cleared it. The timeout of
1012 * 10 msecs is really too long, but it is just a safety measure if
1013 * something goes really wrong. The wait will only happen in the very
1014 * unlikely case of a vblank happening exactly at the same time and
1015 * shouldn't exceed microseconds range.
1017 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1018 !pending, 0, 10 * 1000);
1020 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1022 synchronize_irq(vop->irq);
1025 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1026 struct drm_crtc_state *old_crtc_state)
1028 struct drm_atomic_state *old_state = old_crtc_state->state;
1029 struct drm_plane_state *old_plane_state;
1030 struct vop *vop = to_vop(crtc);
1031 struct drm_plane *plane;
1034 if (WARN_ON(!vop->is_enabled))
1037 spin_lock(&vop->reg_lock);
1041 spin_unlock(&vop->reg_lock);
1044 * There is a (rather unlikely) possiblity that a vblank interrupt
1045 * fired before we set the cfg_done bit. To avoid spuriously
1046 * signalling flip completion we need to wait for it to finish.
1048 vop_wait_for_irq_handler(vop);
1050 spin_lock_irq(&crtc->dev->event_lock);
1051 if (crtc->state->event) {
1052 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1053 WARN_ON(vop->event);
1055 vop->event = crtc->state->event;
1056 crtc->state->event = NULL;
1058 spin_unlock_irq(&crtc->dev->event_lock);
1060 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1061 if (!old_plane_state->fb)
1064 if (old_plane_state->fb == plane->state->fb)
1067 drm_framebuffer_reference(old_plane_state->fb);
1068 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1069 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1070 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1074 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1075 struct drm_crtc_state *old_crtc_state)
1077 rockchip_drm_psr_flush(crtc);
1080 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1081 .enable = vop_crtc_enable,
1082 .disable = vop_crtc_disable,
1083 .mode_fixup = vop_crtc_mode_fixup,
1084 .atomic_flush = vop_crtc_atomic_flush,
1085 .atomic_begin = vop_crtc_atomic_begin,
1088 static void vop_crtc_destroy(struct drm_crtc *crtc)
1090 drm_crtc_cleanup(crtc);
1093 static void vop_crtc_reset(struct drm_crtc *crtc)
1096 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1099 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1101 crtc->state->crtc = crtc;
1104 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1106 struct rockchip_crtc_state *rockchip_state;
1108 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1109 if (!rockchip_state)
1112 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1113 return &rockchip_state->base;
1116 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1117 struct drm_crtc_state *state)
1119 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1121 __drm_atomic_helper_crtc_destroy_state(&s->base);
1125 #ifdef CONFIG_DRM_ANALOGIX_DP
1126 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1128 struct drm_crtc *crtc = &vop->crtc;
1129 struct drm_connector *connector;
1131 mutex_lock(&crtc->dev->mode_config.mutex);
1132 drm_for_each_connector(connector, crtc->dev)
1133 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1134 mutex_unlock(&crtc->dev->mode_config.mutex);
1137 mutex_unlock(&crtc->dev->mode_config.mutex);
1142 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1143 const char *source_name, size_t *values_cnt)
1145 struct vop *vop = to_vop(crtc);
1146 struct drm_connector *connector;
1149 connector = vop_get_edp_connector(vop);
1155 if (source_name && strcmp(source_name, "auto") == 0)
1156 ret = analogix_dp_start_crc(connector);
1157 else if (!source_name)
1158 ret = analogix_dp_stop_crc(connector);
1165 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1166 const char *source_name, size_t *values_cnt)
1172 static const struct drm_crtc_funcs vop_crtc_funcs = {
1173 .set_config = drm_atomic_helper_set_config,
1174 .page_flip = drm_atomic_helper_page_flip,
1175 .destroy = vop_crtc_destroy,
1176 .reset = vop_crtc_reset,
1177 .atomic_duplicate_state = vop_crtc_duplicate_state,
1178 .atomic_destroy_state = vop_crtc_destroy_state,
1179 .enable_vblank = vop_crtc_enable_vblank,
1180 .disable_vblank = vop_crtc_disable_vblank,
1181 .set_crc_source = vop_crtc_set_crc_source,
1184 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1186 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1187 struct drm_framebuffer *fb = val;
1189 drm_crtc_vblank_put(&vop->crtc);
1190 drm_framebuffer_unreference(fb);
1193 static void vop_handle_vblank(struct vop *vop)
1195 struct drm_device *drm = vop->drm_dev;
1196 struct drm_crtc *crtc = &vop->crtc;
1197 unsigned long flags;
1199 spin_lock_irqsave(&drm->event_lock, flags);
1201 drm_crtc_send_vblank_event(crtc, vop->event);
1202 drm_crtc_vblank_put(crtc);
1205 spin_unlock_irqrestore(&drm->event_lock, flags);
1207 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1208 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1211 static irqreturn_t vop_isr(int irq, void *data)
1213 struct vop *vop = data;
1214 struct drm_crtc *crtc = &vop->crtc;
1215 uint32_t active_irqs;
1216 unsigned long flags;
1220 * interrupt register has interrupt status, enable and clear bits, we
1221 * must hold irq_lock to avoid a race with enable/disable_vblank().
1223 spin_lock_irqsave(&vop->irq_lock, flags);
1225 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1226 /* Clear all active interrupt sources */
1228 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1230 spin_unlock_irqrestore(&vop->irq_lock, flags);
1232 /* This is expected for vop iommu irqs, since the irq is shared */
1236 if (active_irqs & DSP_HOLD_VALID_INTR) {
1237 complete(&vop->dsp_hold_completion);
1238 active_irqs &= ~DSP_HOLD_VALID_INTR;
1242 if (active_irqs & LINE_FLAG_INTR) {
1243 complete(&vop->line_flag_completion);
1244 active_irqs &= ~LINE_FLAG_INTR;
1248 if (active_irqs & FS_INTR) {
1249 drm_crtc_handle_vblank(crtc);
1250 vop_handle_vblank(vop);
1251 active_irqs &= ~FS_INTR;
1255 /* Unhandled irqs are spurious. */
1257 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1263 static int vop_create_crtc(struct vop *vop)
1265 const struct vop_data *vop_data = vop->data;
1266 struct device *dev = vop->dev;
1267 struct drm_device *drm_dev = vop->drm_dev;
1268 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1269 struct drm_crtc *crtc = &vop->crtc;
1270 struct device_node *port;
1275 * Create drm_plane for primary and cursor planes first, since we need
1276 * to pass them to drm_crtc_init_with_planes, which sets the
1277 * "possible_crtcs" to the newly initialized crtc.
1279 for (i = 0; i < vop_data->win_size; i++) {
1280 struct vop_win *vop_win = &vop->win[i];
1281 const struct vop_win_data *win_data = vop_win->data;
1283 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1284 win_data->type != DRM_PLANE_TYPE_CURSOR)
1287 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1288 0, &vop_plane_funcs,
1289 win_data->phy->data_formats,
1290 win_data->phy->nformats,
1291 win_data->type, NULL);
1293 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1295 goto err_cleanup_planes;
1298 plane = &vop_win->base;
1299 drm_plane_helper_add(plane, &plane_helper_funcs);
1300 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1302 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1306 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1307 &vop_crtc_funcs, NULL);
1309 goto err_cleanup_planes;
1311 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1314 * Create drm_planes for overlay windows with possible_crtcs restricted
1315 * to the newly created crtc.
1317 for (i = 0; i < vop_data->win_size; i++) {
1318 struct vop_win *vop_win = &vop->win[i];
1319 const struct vop_win_data *win_data = vop_win->data;
1320 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1322 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1325 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1328 win_data->phy->data_formats,
1329 win_data->phy->nformats,
1330 win_data->type, NULL);
1332 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1334 goto err_cleanup_crtc;
1336 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1339 port = of_get_child_by_name(dev->of_node, "port");
1341 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1342 dev->of_node->full_name);
1344 goto err_cleanup_crtc;
1347 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1348 vop_fb_unref_worker);
1350 init_completion(&vop->dsp_hold_completion);
1351 init_completion(&vop->line_flag_completion);
1357 drm_crtc_cleanup(crtc);
1359 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1361 drm_plane_cleanup(plane);
1365 static void vop_destroy_crtc(struct vop *vop)
1367 struct drm_crtc *crtc = &vop->crtc;
1368 struct drm_device *drm_dev = vop->drm_dev;
1369 struct drm_plane *plane, *tmp;
1371 of_node_put(crtc->port);
1374 * We need to cleanup the planes now. Why?
1376 * The planes are "&vop->win[i].base". That means the memory is
1377 * all part of the big "struct vop" chunk of memory. That memory
1378 * was devm allocated and associated with this component. We need to
1379 * free it ourselves before vop_unbind() finishes.
1381 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1383 vop_plane_destroy(plane);
1386 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1387 * references the CRTC.
1389 drm_crtc_cleanup(crtc);
1390 drm_flip_work_cleanup(&vop->fb_unref_work);
1393 static int vop_initial(struct vop *vop)
1395 const struct vop_data *vop_data = vop->data;
1396 const struct vop_reg_data *init_table = vop_data->init_table;
1397 struct reset_control *ahb_rst;
1400 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1401 if (IS_ERR(vop->hclk)) {
1402 dev_err(vop->dev, "failed to get hclk source\n");
1403 return PTR_ERR(vop->hclk);
1405 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1406 if (IS_ERR(vop->aclk)) {
1407 dev_err(vop->dev, "failed to get aclk source\n");
1408 return PTR_ERR(vop->aclk);
1410 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1411 if (IS_ERR(vop->dclk)) {
1412 dev_err(vop->dev, "failed to get dclk source\n");
1413 return PTR_ERR(vop->dclk);
1416 ret = pm_runtime_get_sync(vop->dev);
1418 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1422 ret = clk_prepare(vop->dclk);
1424 dev_err(vop->dev, "failed to prepare dclk\n");
1425 goto err_put_pm_runtime;
1428 /* Enable both the hclk and aclk to setup the vop */
1429 ret = clk_prepare_enable(vop->hclk);
1431 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1432 goto err_unprepare_dclk;
1435 ret = clk_prepare_enable(vop->aclk);
1437 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1438 goto err_disable_hclk;
1442 * do hclk_reset, reset all vop registers.
1444 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1445 if (IS_ERR(ahb_rst)) {
1446 dev_err(vop->dev, "failed to get ahb reset\n");
1447 ret = PTR_ERR(ahb_rst);
1448 goto err_disable_aclk;
1450 reset_control_assert(ahb_rst);
1451 usleep_range(10, 20);
1452 reset_control_deassert(ahb_rst);
1454 memcpy(vop->regsbak, vop->regs, vop->len);
1456 for (i = 0; i < vop_data->table_size; i++)
1457 vop_writel(vop, init_table[i].offset, init_table[i].value);
1459 for (i = 0; i < vop_data->win_size; i++) {
1460 const struct vop_win_data *win = &vop_data->win[i];
1462 VOP_WIN_SET(vop, win, enable, 0);
1468 * do dclk_reset, let all config take affect.
1470 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1471 if (IS_ERR(vop->dclk_rst)) {
1472 dev_err(vop->dev, "failed to get dclk reset\n");
1473 ret = PTR_ERR(vop->dclk_rst);
1474 goto err_disable_aclk;
1476 reset_control_assert(vop->dclk_rst);
1477 usleep_range(10, 20);
1478 reset_control_deassert(vop->dclk_rst);
1480 clk_disable(vop->hclk);
1481 clk_disable(vop->aclk);
1483 vop->is_enabled = false;
1485 pm_runtime_put_sync(vop->dev);
1490 clk_disable_unprepare(vop->aclk);
1492 clk_disable_unprepare(vop->hclk);
1494 clk_unprepare(vop->dclk);
1496 pm_runtime_put_sync(vop->dev);
1501 * Initialize the vop->win array elements.
1503 static void vop_win_init(struct vop *vop)
1505 const struct vop_data *vop_data = vop->data;
1508 for (i = 0; i < vop_data->win_size; i++) {
1509 struct vop_win *vop_win = &vop->win[i];
1510 const struct vop_win_data *win_data = &vop_data->win[i];
1512 vop_win->data = win_data;
1518 * rockchip_drm_wait_line_flag - acqiure the give line flag event
1519 * @crtc: CRTC to enable line flag
1520 * @line_num: interested line number
1521 * @mstimeout: millisecond for timeout
1523 * Driver would hold here until the interested line flag interrupt have
1524 * happened or timeout to wait.
1527 * Zero on success, negative errno on failure.
1529 int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
1530 unsigned int mstimeout)
1532 struct vop *vop = to_vop(crtc);
1533 unsigned long jiffies_left;
1535 if (!crtc || !vop->is_enabled)
1538 if (line_num > crtc->mode.vtotal || mstimeout <= 0)
1541 if (vop_line_flag_irq_is_enabled(vop))
1544 reinit_completion(&vop->line_flag_completion);
1545 vop_line_flag_irq_enable(vop, line_num);
1547 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1548 msecs_to_jiffies(mstimeout));
1549 vop_line_flag_irq_disable(vop);
1551 if (jiffies_left == 0) {
1552 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1558 EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
1560 static int vop_bind(struct device *dev, struct device *master, void *data)
1562 struct platform_device *pdev = to_platform_device(dev);
1563 const struct vop_data *vop_data;
1564 struct drm_device *drm_dev = data;
1566 struct resource *res;
1570 vop_data = of_device_get_match_data(dev);
1574 /* Allocate vop struct and its vop_win array */
1575 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1576 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1581 vop->data = vop_data;
1582 vop->drm_dev = drm_dev;
1583 dev_set_drvdata(dev, vop);
1587 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1588 vop->len = resource_size(res);
1589 vop->regs = devm_ioremap_resource(dev, res);
1590 if (IS_ERR(vop->regs))
1591 return PTR_ERR(vop->regs);
1593 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1597 irq = platform_get_irq(pdev, 0);
1599 dev_err(dev, "cannot find irq for vop\n");
1602 vop->irq = (unsigned int)irq;
1604 spin_lock_init(&vop->reg_lock);
1605 spin_lock_init(&vop->irq_lock);
1607 mutex_init(&vop->vsync_mutex);
1609 ret = devm_request_irq(dev, vop->irq, vop_isr,
1610 IRQF_SHARED, dev_name(dev), vop);
1614 /* IRQ is initially disabled; it gets enabled in power_on */
1615 disable_irq(vop->irq);
1617 ret = vop_create_crtc(vop);
1619 goto err_enable_irq;
1621 pm_runtime_enable(&pdev->dev);
1623 ret = vop_initial(vop);
1625 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1626 goto err_disable_pm_runtime;
1631 err_disable_pm_runtime:
1632 pm_runtime_disable(&pdev->dev);
1633 vop_destroy_crtc(vop);
1635 enable_irq(vop->irq); /* To balance out the disable_irq above */
1639 static void vop_unbind(struct device *dev, struct device *master, void *data)
1641 struct vop *vop = dev_get_drvdata(dev);
1643 pm_runtime_disable(dev);
1644 vop_destroy_crtc(vop);
1646 clk_unprepare(vop->aclk);
1647 clk_unprepare(vop->hclk);
1648 clk_unprepare(vop->dclk);
1651 const struct component_ops vop_component_ops = {
1653 .unbind = vop_unbind,
1655 EXPORT_SYMBOL_GPL(vop_component_ops);