2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
36 #include <linux/reset.h>
37 #include <linux/delay.h>
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_gem.h"
41 #include "rockchip_drm_fb.h"
42 #include "rockchip_drm_psr.h"
43 #include "rockchip_drm_vop.h"
45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, true)
48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
49 vop_mask_write(x, off, mask, shift, v, write_mask, false)
51 #define REG_SET(x, base, reg, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, \
53 reg.mask, reg.shift, v, reg.write_mask)
54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
55 __REG_SET_##mode(x, base + reg.offset, \
56 mask, reg.shift, v, reg.write_mask)
58 #define VOP_WIN_SET(x, win, name, v) \
59 REG_SET(x, win->base, win->phy->name, v, RELAXED)
60 #define VOP_SCL_SET(x, win, name, v) \
61 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
62 #define VOP_SCL_SET_EXT(x, win, name, v) \
63 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
64 #define VOP_CTRL_SET(x, name, v) \
65 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
67 #define VOP_INTR_GET(vop, name) \
68 vop_read_reg(vop, 0, &vop->data->ctrl->name)
70 #define VOP_INTR_SET(vop, name, mask, v) \
71 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
74 int i, reg = 0, mask = 0; \
75 for (i = 0; i < vop->data->intr->nintrs; i++) { \
76 if (vop->data->intr->intrs[i] & type) { \
81 VOP_INTR_SET(vop, name, mask, reg); \
83 #define VOP_INTR_GET_TYPE(vop, name, type) \
84 vop_get_intr_type(vop, &vop->data->intr->name, type)
86 #define VOP_WIN_GET(x, win, name) \
87 vop_read_reg(x, win->base, &win->phy->name)
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
92 #define to_vop(x) container_of(x, struct vop, crtc)
93 #define to_vop_win(x) container_of(x, struct vop_win, base)
100 struct drm_plane base;
101 const struct vop_win_data *data;
106 struct drm_crtc crtc;
108 struct drm_device *drm_dev;
111 /* mutex vsync_ work */
112 struct mutex vsync_mutex;
113 bool vsync_work_pending;
114 struct completion dsp_hold_completion;
116 /* protected by dev->event_lock */
117 struct drm_pending_vblank_event *event;
119 struct drm_flip_work fb_unref_work;
120 unsigned long pending;
122 struct completion line_flag_completion;
124 const struct vop_data *data;
129 /* physical map length of vop register */
132 /* one time only one process allowed to config the register */
134 /* lock vop irq reg */
143 /* vop share memory frequency */
147 struct reset_control *dclk_rst;
149 struct vop_win win[];
152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
154 writel(v, vop->regs + offset);
155 vop->regsbak[offset >> 2] = v;
158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
160 return readl(vop->regs + offset);
163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
164 const struct vop_reg *reg)
166 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
169 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
170 uint32_t mask, uint32_t shift, uint32_t v,
171 bool write_mask, bool relaxed)
177 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
179 uint32_t cached_val = vop->regsbak[offset >> 2];
181 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
182 vop->regsbak[offset >> 2] = v;
186 writel_relaxed(v, vop->regs + offset);
188 writel(v, vop->regs + offset);
191 static inline uint32_t vop_get_intr_type(struct vop *vop,
192 const struct vop_reg *reg, int type)
195 uint32_t regs = vop_read_reg(vop, 0, reg);
197 for (i = 0; i < vop->data->intr->nintrs; i++) {
198 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
199 ret |= vop->data->intr->intrs[i];
205 static inline void vop_cfg_done(struct vop *vop)
207 VOP_CTRL_SET(vop, cfg_done, 1);
210 static bool has_rb_swapped(uint32_t format)
213 case DRM_FORMAT_XBGR8888:
214 case DRM_FORMAT_ABGR8888:
215 case DRM_FORMAT_BGR888:
216 case DRM_FORMAT_BGR565:
223 static enum vop_data_format vop_convert_format(uint32_t format)
226 case DRM_FORMAT_XRGB8888:
227 case DRM_FORMAT_ARGB8888:
228 case DRM_FORMAT_XBGR8888:
229 case DRM_FORMAT_ABGR8888:
230 return VOP_FMT_ARGB8888;
231 case DRM_FORMAT_RGB888:
232 case DRM_FORMAT_BGR888:
233 return VOP_FMT_RGB888;
234 case DRM_FORMAT_RGB565:
235 case DRM_FORMAT_BGR565:
236 return VOP_FMT_RGB565;
237 case DRM_FORMAT_NV12:
238 return VOP_FMT_YUV420SP;
239 case DRM_FORMAT_NV16:
240 return VOP_FMT_YUV422SP;
241 case DRM_FORMAT_NV24:
242 return VOP_FMT_YUV444SP;
244 DRM_ERROR("unsupported format[%08x]\n", format);
249 static bool is_yuv_support(uint32_t format)
252 case DRM_FORMAT_NV12:
253 case DRM_FORMAT_NV16:
254 case DRM_FORMAT_NV24:
261 static bool is_alpha_support(uint32_t format)
264 case DRM_FORMAT_ARGB8888:
265 case DRM_FORMAT_ABGR8888:
272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
273 uint32_t dst, bool is_horizontal,
274 int vsu_mode, int *vskiplines)
276 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279 if (mode == SCALE_UP)
280 val = GET_SCL_FT_BIC(src, dst);
281 else if (mode == SCALE_DOWN)
282 val = GET_SCL_FT_BILI_DN(src, dst);
284 if (mode == SCALE_UP) {
285 if (vsu_mode == SCALE_UP_BIL)
286 val = GET_SCL_FT_BILI_UP(src, dst);
288 val = GET_SCL_FT_BIC(src, dst);
289 } else if (mode == SCALE_DOWN) {
291 *vskiplines = scl_get_vskiplines(src, dst);
292 val = scl_get_bili_dn_vskip(src, dst,
295 val = GET_SCL_FT_BILI_DN(src, dst);
303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
304 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
305 uint32_t dst_h, uint32_t pixel_format)
307 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
308 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
309 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
310 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
311 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
312 bool is_yuv = is_yuv_support(pixel_format);
313 uint16_t cbcr_src_w = src_w / hsub;
314 uint16_t cbcr_src_h = src_h / vsub;
321 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
325 if (!win->phy->scl->ext) {
326 VOP_SCL_SET(vop, win, scale_yrgb_x,
327 scl_cal_scale2(src_w, dst_w));
328 VOP_SCL_SET(vop, win, scale_yrgb_y,
329 scl_cal_scale2(src_h, dst_h));
331 VOP_SCL_SET(vop, win, scale_cbcr_x,
332 scl_cal_scale2(cbcr_src_w, dst_w));
333 VOP_SCL_SET(vop, win, scale_cbcr_y,
334 scl_cal_scale2(cbcr_src_h, dst_h));
339 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
340 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
343 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
344 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
345 if (cbcr_hor_scl_mode == SCALE_DOWN)
346 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
348 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
350 if (yrgb_hor_scl_mode == SCALE_DOWN)
351 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
353 lb_mode = scl_vop_cal_lb_mode(src_w, false);
356 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
357 if (lb_mode == LB_RGB_3840X2) {
358 if (yrgb_ver_scl_mode != SCALE_NONE) {
359 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
362 if (cbcr_ver_scl_mode != SCALE_NONE) {
363 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
366 vsu_mode = SCALE_UP_BIL;
367 } else if (lb_mode == LB_RGB_2560X4) {
368 vsu_mode = SCALE_UP_BIL;
370 vsu_mode = SCALE_UP_BIC;
373 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
375 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
376 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
377 false, vsu_mode, &vskiplines);
378 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
380 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
381 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
383 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
384 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
385 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
386 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
387 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
389 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
390 dst_w, true, 0, NULL);
391 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
392 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
393 dst_h, false, vsu_mode, &vskiplines);
394 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
396 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
397 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
398 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
399 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
400 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
401 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
402 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
410 if (WARN_ON(!vop->is_enabled))
413 spin_lock_irqsave(&vop->irq_lock, flags);
415 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
416 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
418 spin_unlock_irqrestore(&vop->irq_lock, flags);
421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
425 if (WARN_ON(!vop->is_enabled))
428 spin_lock_irqsave(&vop->irq_lock, flags);
430 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
432 spin_unlock_irqrestore(&vop->irq_lock, flags);
436 * (1) each frame starts at the start of the Vsync pulse which is signaled by
437 * the "FRAME_SYNC" interrupt.
438 * (2) the active data region of each frame ends at dsp_vact_end
439 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
440 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
442 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
444 * LINE_FLAG -------------------------------+
448 * | Vsync | Vbp | Vactive | Vfp |
452 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
453 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
454 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
455 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
457 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
459 uint32_t line_flag_irq;
462 spin_lock_irqsave(&vop->irq_lock, flags);
464 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
466 spin_unlock_irqrestore(&vop->irq_lock, flags);
468 return !!line_flag_irq;
471 static void vop_line_flag_irq_enable(struct vop *vop)
475 if (WARN_ON(!vop->is_enabled))
478 spin_lock_irqsave(&vop->irq_lock, flags);
480 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
481 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
483 spin_unlock_irqrestore(&vop->irq_lock, flags);
486 static void vop_line_flag_irq_disable(struct vop *vop)
490 if (WARN_ON(!vop->is_enabled))
493 spin_lock_irqsave(&vop->irq_lock, flags);
495 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
497 spin_unlock_irqrestore(&vop->irq_lock, flags);
500 static int vop_enable(struct drm_crtc *crtc)
502 struct vop *vop = to_vop(crtc);
505 ret = pm_runtime_get_sync(vop->dev);
507 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
511 ret = clk_enable(vop->hclk);
512 if (WARN_ON(ret < 0))
513 goto err_put_pm_runtime;
515 ret = clk_enable(vop->dclk);
516 if (WARN_ON(ret < 0))
517 goto err_disable_hclk;
519 ret = clk_enable(vop->aclk);
520 if (WARN_ON(ret < 0))
521 goto err_disable_dclk;
524 * Slave iommu shares power, irq and clock with vop. It was associated
525 * automatically with this master device via common driver code.
526 * Now that we have enabled the clock we attach it to the shared drm
529 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
531 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
532 goto err_disable_aclk;
535 memcpy(vop->regs, vop->regsbak, vop->len);
539 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
541 vop->is_enabled = true;
543 spin_lock(&vop->reg_lock);
545 VOP_CTRL_SET(vop, standby, 0);
547 spin_unlock(&vop->reg_lock);
549 enable_irq(vop->irq);
551 drm_crtc_vblank_on(crtc);
556 clk_disable(vop->aclk);
558 clk_disable(vop->dclk);
560 clk_disable(vop->hclk);
562 pm_runtime_put_sync(vop->dev);
566 static void vop_crtc_disable(struct drm_crtc *crtc)
568 struct vop *vop = to_vop(crtc);
573 rockchip_drm_psr_deactivate(&vop->crtc);
576 * We need to make sure that all windows are disabled before we
577 * disable that crtc. Otherwise we might try to scan from a destroyed
580 for (i = 0; i < vop->data->win_size; i++) {
581 struct vop_win *vop_win = &vop->win[i];
582 const struct vop_win_data *win = vop_win->data;
584 spin_lock(&vop->reg_lock);
585 VOP_WIN_SET(vop, win, enable, 0);
586 spin_unlock(&vop->reg_lock);
591 drm_crtc_vblank_off(crtc);
594 * Vop standby will take effect at end of current frame,
595 * if dsp hold valid irq happen, it means standby complete.
597 * we must wait standby complete when we want to disable aclk,
598 * if not, memory bus maybe dead.
600 reinit_completion(&vop->dsp_hold_completion);
601 vop_dsp_hold_valid_irq_enable(vop);
603 spin_lock(&vop->reg_lock);
605 VOP_CTRL_SET(vop, standby, 1);
607 spin_unlock(&vop->reg_lock);
609 wait_for_completion(&vop->dsp_hold_completion);
611 vop_dsp_hold_valid_irq_disable(vop);
613 disable_irq(vop->irq);
615 vop->is_enabled = false;
618 * vop standby complete, so iommu detach is safe.
620 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
622 clk_disable(vop->dclk);
623 clk_disable(vop->aclk);
624 clk_disable(vop->hclk);
625 pm_runtime_put(vop->dev);
627 if (crtc->state->event && !crtc->state->active) {
628 spin_lock_irq(&crtc->dev->event_lock);
629 drm_crtc_send_vblank_event(crtc, crtc->state->event);
630 spin_unlock_irq(&crtc->dev->event_lock);
632 crtc->state->event = NULL;
636 static void vop_plane_destroy(struct drm_plane *plane)
638 drm_plane_cleanup(plane);
641 static int vop_plane_atomic_check(struct drm_plane *plane,
642 struct drm_plane_state *state)
644 struct drm_crtc *crtc = state->crtc;
645 struct drm_crtc_state *crtc_state;
646 struct drm_framebuffer *fb = state->fb;
647 struct vop_win *vop_win = to_vop_win(plane);
648 const struct vop_win_data *win = vop_win->data;
650 struct drm_rect clip;
651 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
652 DRM_PLANE_HELPER_NO_SCALING;
653 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
654 DRM_PLANE_HELPER_NO_SCALING;
659 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
660 if (WARN_ON(!crtc_state))
665 clip.x2 = crtc_state->adjusted_mode.hdisplay;
666 clip.y2 = crtc_state->adjusted_mode.vdisplay;
668 ret = drm_plane_helper_check_state(state, &clip,
669 min_scale, max_scale,
677 ret = vop_convert_format(fb->format->format);
682 * Src.x1 can be odd when do clip, but yuv plane start point
683 * need align with 2 pixel.
685 if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
691 static void vop_plane_atomic_disable(struct drm_plane *plane,
692 struct drm_plane_state *old_state)
694 struct vop_win *vop_win = to_vop_win(plane);
695 const struct vop_win_data *win = vop_win->data;
696 struct vop *vop = to_vop(old_state->crtc);
698 if (!old_state->crtc)
701 spin_lock(&vop->reg_lock);
703 VOP_WIN_SET(vop, win, enable, 0);
705 spin_unlock(&vop->reg_lock);
708 static void vop_plane_atomic_update(struct drm_plane *plane,
709 struct drm_plane_state *old_state)
711 struct drm_plane_state *state = plane->state;
712 struct drm_crtc *crtc = state->crtc;
713 struct vop_win *vop_win = to_vop_win(plane);
714 const struct vop_win_data *win = vop_win->data;
715 struct vop *vop = to_vop(state->crtc);
716 struct drm_framebuffer *fb = state->fb;
717 unsigned int actual_w, actual_h;
718 unsigned int dsp_stx, dsp_sty;
719 uint32_t act_info, dsp_info, dsp_st;
720 struct drm_rect *src = &state->src;
721 struct drm_rect *dest = &state->dst;
722 struct drm_gem_object *obj, *uv_obj;
723 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
724 unsigned long offset;
731 * can't update plane when vop is disabled.
736 if (WARN_ON(!vop->is_enabled))
739 if (!state->visible) {
740 vop_plane_atomic_disable(plane, old_state);
744 obj = rockchip_fb_get_gem_obj(fb, 0);
745 rk_obj = to_rockchip_obj(obj);
747 actual_w = drm_rect_width(src) >> 16;
748 actual_h = drm_rect_height(src) >> 16;
749 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
751 dsp_info = (drm_rect_height(dest) - 1) << 16;
752 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
754 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
755 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
756 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
758 offset = (src->x1 >> 16) * fb->format->cpp[0];
759 offset += (src->y1 >> 16) * fb->pitches[0];
760 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
762 format = vop_convert_format(fb->format->format);
764 spin_lock(&vop->reg_lock);
766 VOP_WIN_SET(vop, win, format, format);
767 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
768 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
769 if (is_yuv_support(fb->format->format)) {
770 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
771 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
772 int bpp = fb->format->cpp[1];
774 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
775 rk_uv_obj = to_rockchip_obj(uv_obj);
777 offset = (src->x1 >> 16) * bpp / hsub;
778 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
780 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
781 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
782 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
786 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
787 drm_rect_width(dest), drm_rect_height(dest),
790 VOP_WIN_SET(vop, win, act_info, act_info);
791 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
792 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
794 rb_swap = has_rb_swapped(fb->format->format);
795 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
797 if (is_alpha_support(fb->format->format)) {
798 VOP_WIN_SET(vop, win, dst_alpha_ctl,
799 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
800 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
801 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
802 SRC_BLEND_M0(ALPHA_PER_PIX) |
803 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
804 SRC_FACTOR_M0(ALPHA_ONE);
805 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
807 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
810 VOP_WIN_SET(vop, win, enable, 1);
811 spin_unlock(&vop->reg_lock);
814 static const struct drm_plane_helper_funcs plane_helper_funcs = {
815 .atomic_check = vop_plane_atomic_check,
816 .atomic_update = vop_plane_atomic_update,
817 .atomic_disable = vop_plane_atomic_disable,
820 static const struct drm_plane_funcs vop_plane_funcs = {
821 .update_plane = drm_atomic_helper_update_plane,
822 .disable_plane = drm_atomic_helper_disable_plane,
823 .destroy = vop_plane_destroy,
824 .reset = drm_atomic_helper_plane_reset,
825 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
826 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
829 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
831 struct vop *vop = to_vop(crtc);
834 if (WARN_ON(!vop->is_enabled))
837 spin_lock_irqsave(&vop->irq_lock, flags);
839 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
840 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
842 spin_unlock_irqrestore(&vop->irq_lock, flags);
847 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
849 struct vop *vop = to_vop(crtc);
852 if (WARN_ON(!vop->is_enabled))
855 spin_lock_irqsave(&vop->irq_lock, flags);
857 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
859 spin_unlock_irqrestore(&vop->irq_lock, flags);
862 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
863 const struct drm_display_mode *mode,
864 struct drm_display_mode *adjusted_mode)
866 struct vop *vop = to_vop(crtc);
868 adjusted_mode->clock =
869 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
874 static void vop_crtc_enable(struct drm_crtc *crtc)
876 struct vop *vop = to_vop(crtc);
877 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
878 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
879 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
880 u16 hdisplay = adjusted_mode->hdisplay;
881 u16 htotal = adjusted_mode->htotal;
882 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
883 u16 hact_end = hact_st + hdisplay;
884 u16 vdisplay = adjusted_mode->vdisplay;
885 u16 vtotal = adjusted_mode->vtotal;
886 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
887 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
888 u16 vact_end = vact_st + vdisplay;
889 uint32_t pin_pol, val;
894 ret = vop_enable(crtc);
896 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
901 * If dclk rate is zero, mean that scanout is stop,
902 * we don't need wait any more.
904 if (clk_get_rate(vop->dclk)) {
906 * Rk3288 vop timing register is immediately, when configure
907 * display timing on display time, may cause tearing.
909 * Vop standby will take effect at end of current frame,
910 * if dsp hold valid irq happen, it means standby complete.
913 * standby and wait complete --> |----
917 * configure display timing --> |
922 reinit_completion(&vop->dsp_hold_completion);
923 vop_dsp_hold_valid_irq_enable(vop);
925 spin_lock(&vop->reg_lock);
927 VOP_CTRL_SET(vop, standby, 1);
929 spin_unlock(&vop->reg_lock);
931 wait_for_completion(&vop->dsp_hold_completion);
933 vop_dsp_hold_valid_irq_disable(vop);
936 pin_pol = BIT(DCLK_INVERT);
937 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
938 BIT(HSYNC_POSITIVE) : 0;
939 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
940 BIT(VSYNC_POSITIVE) : 0;
941 VOP_CTRL_SET(vop, pin_pol, pin_pol);
943 switch (s->output_type) {
944 case DRM_MODE_CONNECTOR_LVDS:
945 VOP_CTRL_SET(vop, rgb_en, 1);
946 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
948 case DRM_MODE_CONNECTOR_eDP:
949 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
950 VOP_CTRL_SET(vop, edp_en, 1);
952 case DRM_MODE_CONNECTOR_HDMIA:
953 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
954 VOP_CTRL_SET(vop, hdmi_en, 1);
956 case DRM_MODE_CONNECTOR_DSI:
957 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
958 VOP_CTRL_SET(vop, mipi_en, 1);
960 case DRM_MODE_CONNECTOR_DisplayPort:
961 pin_pol &= ~BIT(DCLK_INVERT);
962 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
963 VOP_CTRL_SET(vop, dp_en, 1);
966 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
969 VOP_CTRL_SET(vop, out_mode, s->output_mode);
971 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
974 VOP_CTRL_SET(vop, hact_st_end, val);
975 VOP_CTRL_SET(vop, hpost_st_end, val);
977 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
980 VOP_CTRL_SET(vop, vact_st_end, val);
981 VOP_CTRL_SET(vop, vpost_st_end, val);
983 VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
985 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
987 VOP_CTRL_SET(vop, standby, 0);
989 rockchip_drm_psr_activate(&vop->crtc);
992 static bool vop_fs_irq_is_pending(struct vop *vop)
994 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
997 static void vop_wait_for_irq_handler(struct vop *vop)
1003 * Spin until frame start interrupt status bit goes low, which means
1004 * that interrupt handler was invoked and cleared it. The timeout of
1005 * 10 msecs is really too long, but it is just a safety measure if
1006 * something goes really wrong. The wait will only happen in the very
1007 * unlikely case of a vblank happening exactly at the same time and
1008 * shouldn't exceed microseconds range.
1010 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1011 !pending, 0, 10 * 1000);
1013 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1015 synchronize_irq(vop->irq);
1018 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1019 struct drm_crtc_state *old_crtc_state)
1021 struct drm_atomic_state *old_state = old_crtc_state->state;
1022 struct drm_plane_state *old_plane_state;
1023 struct vop *vop = to_vop(crtc);
1024 struct drm_plane *plane;
1027 if (WARN_ON(!vop->is_enabled))
1030 spin_lock(&vop->reg_lock);
1034 spin_unlock(&vop->reg_lock);
1037 * There is a (rather unlikely) possiblity that a vblank interrupt
1038 * fired before we set the cfg_done bit. To avoid spuriously
1039 * signalling flip completion we need to wait for it to finish.
1041 vop_wait_for_irq_handler(vop);
1043 spin_lock_irq(&crtc->dev->event_lock);
1044 if (crtc->state->event) {
1045 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1046 WARN_ON(vop->event);
1048 vop->event = crtc->state->event;
1049 crtc->state->event = NULL;
1051 spin_unlock_irq(&crtc->dev->event_lock);
1053 for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1054 if (!old_plane_state->fb)
1057 if (old_plane_state->fb == plane->state->fb)
1060 drm_framebuffer_reference(old_plane_state->fb);
1061 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1062 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1063 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1067 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1068 struct drm_crtc_state *old_crtc_state)
1070 rockchip_drm_psr_flush(crtc);
1073 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1074 .enable = vop_crtc_enable,
1075 .disable = vop_crtc_disable,
1076 .mode_fixup = vop_crtc_mode_fixup,
1077 .atomic_flush = vop_crtc_atomic_flush,
1078 .atomic_begin = vop_crtc_atomic_begin,
1081 static void vop_crtc_destroy(struct drm_crtc *crtc)
1083 drm_crtc_cleanup(crtc);
1086 static void vop_crtc_reset(struct drm_crtc *crtc)
1089 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1092 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1094 crtc->state->crtc = crtc;
1097 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1099 struct rockchip_crtc_state *rockchip_state;
1101 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1102 if (!rockchip_state)
1105 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1106 return &rockchip_state->base;
1109 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1110 struct drm_crtc_state *state)
1112 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1114 __drm_atomic_helper_crtc_destroy_state(&s->base);
1118 #ifdef CONFIG_DRM_ANALOGIX_DP
1119 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1121 struct drm_connector *connector;
1122 struct drm_connector_list_iter conn_iter;
1124 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1125 drm_for_each_connector_iter(connector, &conn_iter) {
1126 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1127 drm_connector_list_iter_end(&conn_iter);
1131 drm_connector_list_iter_end(&conn_iter);
1136 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1137 const char *source_name, size_t *values_cnt)
1139 struct vop *vop = to_vop(crtc);
1140 struct drm_connector *connector;
1143 connector = vop_get_edp_connector(vop);
1149 if (source_name && strcmp(source_name, "auto") == 0)
1150 ret = analogix_dp_start_crc(connector);
1151 else if (!source_name)
1152 ret = analogix_dp_stop_crc(connector);
1159 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1160 const char *source_name, size_t *values_cnt)
1166 static const struct drm_crtc_funcs vop_crtc_funcs = {
1167 .set_config = drm_atomic_helper_set_config,
1168 .page_flip = drm_atomic_helper_page_flip,
1169 .destroy = vop_crtc_destroy,
1170 .reset = vop_crtc_reset,
1171 .atomic_duplicate_state = vop_crtc_duplicate_state,
1172 .atomic_destroy_state = vop_crtc_destroy_state,
1173 .enable_vblank = vop_crtc_enable_vblank,
1174 .disable_vblank = vop_crtc_disable_vblank,
1175 .set_crc_source = vop_crtc_set_crc_source,
1178 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1180 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1181 struct drm_framebuffer *fb = val;
1183 drm_crtc_vblank_put(&vop->crtc);
1184 drm_framebuffer_unreference(fb);
1187 static void vop_handle_vblank(struct vop *vop)
1189 struct drm_device *drm = vop->drm_dev;
1190 struct drm_crtc *crtc = &vop->crtc;
1191 unsigned long flags;
1193 spin_lock_irqsave(&drm->event_lock, flags);
1195 drm_crtc_send_vblank_event(crtc, vop->event);
1196 drm_crtc_vblank_put(crtc);
1199 spin_unlock_irqrestore(&drm->event_lock, flags);
1201 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1202 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1205 static irqreturn_t vop_isr(int irq, void *data)
1207 struct vop *vop = data;
1208 struct drm_crtc *crtc = &vop->crtc;
1209 uint32_t active_irqs;
1210 unsigned long flags;
1214 * interrupt register has interrupt status, enable and clear bits, we
1215 * must hold irq_lock to avoid a race with enable/disable_vblank().
1217 spin_lock_irqsave(&vop->irq_lock, flags);
1219 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1220 /* Clear all active interrupt sources */
1222 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1224 spin_unlock_irqrestore(&vop->irq_lock, flags);
1226 /* This is expected for vop iommu irqs, since the irq is shared */
1230 if (active_irqs & DSP_HOLD_VALID_INTR) {
1231 complete(&vop->dsp_hold_completion);
1232 active_irqs &= ~DSP_HOLD_VALID_INTR;
1236 if (active_irqs & LINE_FLAG_INTR) {
1237 complete(&vop->line_flag_completion);
1238 active_irqs &= ~LINE_FLAG_INTR;
1242 if (active_irqs & FS_INTR) {
1243 drm_crtc_handle_vblank(crtc);
1244 vop_handle_vblank(vop);
1245 active_irqs &= ~FS_INTR;
1249 /* Unhandled irqs are spurious. */
1251 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1257 static int vop_create_crtc(struct vop *vop)
1259 const struct vop_data *vop_data = vop->data;
1260 struct device *dev = vop->dev;
1261 struct drm_device *drm_dev = vop->drm_dev;
1262 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1263 struct drm_crtc *crtc = &vop->crtc;
1264 struct device_node *port;
1269 * Create drm_plane for primary and cursor planes first, since we need
1270 * to pass them to drm_crtc_init_with_planes, which sets the
1271 * "possible_crtcs" to the newly initialized crtc.
1273 for (i = 0; i < vop_data->win_size; i++) {
1274 struct vop_win *vop_win = &vop->win[i];
1275 const struct vop_win_data *win_data = vop_win->data;
1277 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1278 win_data->type != DRM_PLANE_TYPE_CURSOR)
1281 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1282 0, &vop_plane_funcs,
1283 win_data->phy->data_formats,
1284 win_data->phy->nformats,
1285 win_data->type, NULL);
1287 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1289 goto err_cleanup_planes;
1292 plane = &vop_win->base;
1293 drm_plane_helper_add(plane, &plane_helper_funcs);
1294 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1296 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1300 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1301 &vop_crtc_funcs, NULL);
1303 goto err_cleanup_planes;
1305 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1308 * Create drm_planes for overlay windows with possible_crtcs restricted
1309 * to the newly created crtc.
1311 for (i = 0; i < vop_data->win_size; i++) {
1312 struct vop_win *vop_win = &vop->win[i];
1313 const struct vop_win_data *win_data = vop_win->data;
1314 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1316 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1319 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1322 win_data->phy->data_formats,
1323 win_data->phy->nformats,
1324 win_data->type, NULL);
1326 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1328 goto err_cleanup_crtc;
1330 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1333 port = of_get_child_by_name(dev->of_node, "port");
1335 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1336 dev->of_node->full_name);
1338 goto err_cleanup_crtc;
1341 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1342 vop_fb_unref_worker);
1344 init_completion(&vop->dsp_hold_completion);
1345 init_completion(&vop->line_flag_completion);
1351 drm_crtc_cleanup(crtc);
1353 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1355 drm_plane_cleanup(plane);
1359 static void vop_destroy_crtc(struct vop *vop)
1361 struct drm_crtc *crtc = &vop->crtc;
1362 struct drm_device *drm_dev = vop->drm_dev;
1363 struct drm_plane *plane, *tmp;
1365 of_node_put(crtc->port);
1368 * We need to cleanup the planes now. Why?
1370 * The planes are "&vop->win[i].base". That means the memory is
1371 * all part of the big "struct vop" chunk of memory. That memory
1372 * was devm allocated and associated with this component. We need to
1373 * free it ourselves before vop_unbind() finishes.
1375 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1377 vop_plane_destroy(plane);
1380 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1381 * references the CRTC.
1383 drm_crtc_cleanup(crtc);
1384 drm_flip_work_cleanup(&vop->fb_unref_work);
1387 static int vop_initial(struct vop *vop)
1389 const struct vop_data *vop_data = vop->data;
1390 const struct vop_reg_data *init_table = vop_data->init_table;
1391 struct reset_control *ahb_rst;
1394 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1395 if (IS_ERR(vop->hclk)) {
1396 dev_err(vop->dev, "failed to get hclk source\n");
1397 return PTR_ERR(vop->hclk);
1399 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1400 if (IS_ERR(vop->aclk)) {
1401 dev_err(vop->dev, "failed to get aclk source\n");
1402 return PTR_ERR(vop->aclk);
1404 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1405 if (IS_ERR(vop->dclk)) {
1406 dev_err(vop->dev, "failed to get dclk source\n");
1407 return PTR_ERR(vop->dclk);
1410 ret = pm_runtime_get_sync(vop->dev);
1412 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1416 ret = clk_prepare(vop->dclk);
1418 dev_err(vop->dev, "failed to prepare dclk\n");
1419 goto err_put_pm_runtime;
1422 /* Enable both the hclk and aclk to setup the vop */
1423 ret = clk_prepare_enable(vop->hclk);
1425 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1426 goto err_unprepare_dclk;
1429 ret = clk_prepare_enable(vop->aclk);
1431 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1432 goto err_disable_hclk;
1436 * do hclk_reset, reset all vop registers.
1438 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1439 if (IS_ERR(ahb_rst)) {
1440 dev_err(vop->dev, "failed to get ahb reset\n");
1441 ret = PTR_ERR(ahb_rst);
1442 goto err_disable_aclk;
1444 reset_control_assert(ahb_rst);
1445 usleep_range(10, 20);
1446 reset_control_deassert(ahb_rst);
1448 memcpy(vop->regsbak, vop->regs, vop->len);
1450 for (i = 0; i < vop_data->table_size; i++)
1451 vop_writel(vop, init_table[i].offset, init_table[i].value);
1453 for (i = 0; i < vop_data->win_size; i++) {
1454 const struct vop_win_data *win = &vop_data->win[i];
1456 VOP_WIN_SET(vop, win, enable, 0);
1462 * do dclk_reset, let all config take affect.
1464 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1465 if (IS_ERR(vop->dclk_rst)) {
1466 dev_err(vop->dev, "failed to get dclk reset\n");
1467 ret = PTR_ERR(vop->dclk_rst);
1468 goto err_disable_aclk;
1470 reset_control_assert(vop->dclk_rst);
1471 usleep_range(10, 20);
1472 reset_control_deassert(vop->dclk_rst);
1474 clk_disable(vop->hclk);
1475 clk_disable(vop->aclk);
1477 vop->is_enabled = false;
1479 pm_runtime_put_sync(vop->dev);
1484 clk_disable_unprepare(vop->aclk);
1486 clk_disable_unprepare(vop->hclk);
1488 clk_unprepare(vop->dclk);
1490 pm_runtime_put_sync(vop->dev);
1495 * Initialize the vop->win array elements.
1497 static void vop_win_init(struct vop *vop)
1499 const struct vop_data *vop_data = vop->data;
1502 for (i = 0; i < vop_data->win_size; i++) {
1503 struct vop_win *vop_win = &vop->win[i];
1504 const struct vop_win_data *win_data = &vop_data->win[i];
1506 vop_win->data = win_data;
1512 * rockchip_drm_wait_vact_end
1513 * @crtc: CRTC to enable line flag
1514 * @mstimeout: millisecond for timeout
1516 * Wait for vact_end line flag irq or timeout.
1519 * Zero on success, negative errno on failure.
1521 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1523 struct vop *vop = to_vop(crtc);
1524 unsigned long jiffies_left;
1526 if (!crtc || !vop->is_enabled)
1532 if (vop_line_flag_irq_is_enabled(vop))
1535 reinit_completion(&vop->line_flag_completion);
1536 vop_line_flag_irq_enable(vop);
1538 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1539 msecs_to_jiffies(mstimeout));
1540 vop_line_flag_irq_disable(vop);
1542 if (jiffies_left == 0) {
1543 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1549 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1551 static int vop_bind(struct device *dev, struct device *master, void *data)
1553 struct platform_device *pdev = to_platform_device(dev);
1554 const struct vop_data *vop_data;
1555 struct drm_device *drm_dev = data;
1557 struct resource *res;
1561 vop_data = of_device_get_match_data(dev);
1565 /* Allocate vop struct and its vop_win array */
1566 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1567 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1572 vop->data = vop_data;
1573 vop->drm_dev = drm_dev;
1574 dev_set_drvdata(dev, vop);
1578 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579 vop->len = resource_size(res);
1580 vop->regs = devm_ioremap_resource(dev, res);
1581 if (IS_ERR(vop->regs))
1582 return PTR_ERR(vop->regs);
1584 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1588 irq = platform_get_irq(pdev, 0);
1590 dev_err(dev, "cannot find irq for vop\n");
1593 vop->irq = (unsigned int)irq;
1595 spin_lock_init(&vop->reg_lock);
1596 spin_lock_init(&vop->irq_lock);
1598 mutex_init(&vop->vsync_mutex);
1600 ret = devm_request_irq(dev, vop->irq, vop_isr,
1601 IRQF_SHARED, dev_name(dev), vop);
1605 /* IRQ is initially disabled; it gets enabled in power_on */
1606 disable_irq(vop->irq);
1608 ret = vop_create_crtc(vop);
1610 goto err_enable_irq;
1612 pm_runtime_enable(&pdev->dev);
1614 ret = vop_initial(vop);
1616 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1617 goto err_disable_pm_runtime;
1622 err_disable_pm_runtime:
1623 pm_runtime_disable(&pdev->dev);
1624 vop_destroy_crtc(vop);
1626 enable_irq(vop->irq); /* To balance out the disable_irq above */
1630 static void vop_unbind(struct device *dev, struct device *master, void *data)
1632 struct vop *vop = dev_get_drvdata(dev);
1634 pm_runtime_disable(dev);
1635 vop_destroy_crtc(vop);
1637 clk_unprepare(vop->aclk);
1638 clk_unprepare(vop->hclk);
1639 clk_unprepare(vop->dclk);
1642 const struct component_ops vop_component_ops = {
1644 .unbind = vop_unbind,
1646 EXPORT_SYMBOL_GPL(vop_component_ops);