drivers/gpu/drm/rcar-du/rcar_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * rcar_lvds.c  --  R-Car LVDS Encoder
   4  *
   5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18
  19 #include <drm/drm_atomic.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_bridge.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_panel.h>
  24
  25 #include "rcar_lvds_regs.h"
  26
  27 struct rcar_lvds;
  28
  29 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
  30 enum rcar_lvds_mode {
  31         RCAR_LVDS_MODE_JEIDA = 0,
  32         RCAR_LVDS_MODE_MIRROR = 1,
  33         RCAR_LVDS_MODE_VESA = 4,
  34 };
  35
  36 #define RCAR_LVDS_QUIRK_LANES           BIT(0)  /* LVDS lanes 1 and 3 inverted */
  37 #define RCAR_LVDS_QUIRK_GEN3_LVEN       BIT(1)  /* LVEN bit needs to be set on R8A77970/R8A7799x */
  38 #define RCAR_LVDS_QUIRK_PWD             BIT(2)  /* PWD bit available (all of Gen3 but E3) */
  39 #define RCAR_LVDS_QUIRK_EXT_PLL         BIT(3)  /* Has extended PLL */
  40 #define RCAR_LVDS_QUIRK_DUAL_LINK       BIT(4)  /* Supports dual-link operation */
  41
  42 struct rcar_lvds_device_info {
  43         unsigned int gen;
  44         unsigned int quirks;
  45         void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
  46 };
  47
  48 struct rcar_lvds {
  49         struct device *dev;
  50         const struct rcar_lvds_device_info *info;
  51
  52         struct drm_bridge bridge;
  53
  54         struct drm_bridge *next_bridge;
  55         struct drm_connector connector;
  56         struct drm_panel *panel;
  57
  58         void __iomem *mmio;
  59         struct {
  60                 struct clk *mod;                /* CPG module clock */
  61                 struct clk *extal;              /* External clock */
  62                 struct clk *dotclkin[2];        /* External DU clocks */
  63         } clocks;
  64         bool enabled;
  65
  66         struct drm_display_mode display_mode;
  67         enum rcar_lvds_mode mode;
  68 };
  69
  70 #define bridge_to_rcar_lvds(bridge) \
  71         container_of(bridge, struct rcar_lvds, bridge)
  72
  73 #define connector_to_rcar_lvds(connector) \
  74         container_of(connector, struct rcar_lvds, connector)
  75
  76 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
  77 {
  78         iowrite32(data, lvds->mmio + reg);
  79 }
  80
  81 /* -----------------------------------------------------------------------------
  82  * Connector & Panel
  83  */
  84
  85 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
  86 {
  87         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  88
  89         return drm_panel_get_modes(lvds->panel);
  90 }
  91
  92 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
  93                                             struct drm_connector_state *state)
  94 {
  95         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  96         const struct drm_display_mode *panel_mode;
  97         struct drm_crtc_state *crtc_state;
  98
  99         if (!state->crtc)
 100                 return 0;
 101
 102         if (list_empty(&connector->modes)) {
 103                 dev_dbg(lvds->dev, "connector: empty modes list\n");
 104                 return -EINVAL;
 105         }
 106
 107         panel_mode = list_first_entry(&connector->modes,
 108                                       struct drm_display_mode, head);
 109
 110         /* We're not allowed to modify the resolution. */
 111         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 112         if (IS_ERR(crtc_state))
 113                 return PTR_ERR(crtc_state);
 114
 115         if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
 116             crtc_state->mode.vdisplay != panel_mode->vdisplay)
 117                 return -EINVAL;
 118
 119         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
 120         drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
 121
 122         return 0;
 123 }
 124
 125 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
 126         .get_modes = rcar_lvds_connector_get_modes,
 127         .atomic_check = rcar_lvds_connector_atomic_check,
 128 };
 129
 130 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
 131         .reset = drm_atomic_helper_connector_reset,
 132         .fill_modes = drm_helper_probe_single_connector_modes,
 133         .destroy = drm_connector_cleanup,
 134         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 135         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 136 };
 137
 138 /* -----------------------------------------------------------------------------
 139  * PLL Setup
 140  */
 141
 142 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
 143 {
 144         u32 val;
 145
 146         if (freq < 39000000)
 147                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
 148         else if (freq < 61000000)
 149                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
 150         else if (freq < 121000000)
 151                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
 152         else
 153                 val = LVDPLLCR_PLLDLYCNT_150M;
 154
 155         rcar_lvds_write(lvds, LVDPLLCR, val);
 156 }
 157
 158 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
 159 {
 160         u32 val;
 161
 162         if (freq < 42000000)
 163                 val = LVDPLLCR_PLLDIVCNT_42M;
 164         else if (freq < 85000000)
 165                 val = LVDPLLCR_PLLDIVCNT_85M;
 166         else if (freq < 128000000)
 167                 val = LVDPLLCR_PLLDIVCNT_128M;
 168         else
 169                 val = LVDPLLCR_PLLDIVCNT_148M;
 170
 171         rcar_lvds_write(lvds, LVDPLLCR, val);
 172 }
 173
 174 struct pll_info {
 175         unsigned long diff;
 176         unsigned int pll_m;
 177         unsigned int pll_n;
 178         unsigned int pll_e;
 179         unsigned int div;
 180         u32 clksel;
 181 };
 182
 183 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
 184                                      unsigned long target, struct pll_info *pll,
 185                                      u32 clksel)
 186 {
 187         unsigned long output;
 188         unsigned long fin;
 189         unsigned int m_min;
 190         unsigned int m_max;
 191         unsigned int m;
 192         int error;
 193
 194         if (!clk)
 195                 return;
 196
 197         /*
 198          * The LVDS PLL is made of a pre-divider and a multiplier (strangely
 199          * enough called M and N respectively), followed by a post-divider E.
 200          *
 201          *         ,-----.         ,-----.     ,-----.         ,-----.
 202          * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
 203          *         `-----'     ,-> |     |     `-----'   |     `-----'
 204          *                     |   `-----'               |
 205          *                     |         ,-----.         |
 206          *                     `-------- | 1/N | <-------'
 207          *                               `-----'
 208          *
 209          * The clock output by the PLL is then further divided by a programmable
 210          * divider DIV to achieve the desired target frequency. Finally, an
 211          * optional fixed /7 divider is used to convert the bit clock to a pixel
 212          * clock (as LVDS transmits 7 bits per lane per clock sample).
 213          *
 214          *          ,-------.     ,-----.     |\
 215          * Fout --> | 1/DIV | --> | 1/7 | --> | |
 216          *          `-------'  |  `-----'     | | --> dot clock
 217          *                     `------------> | |
 218          *                                    |/
 219          *
 220          * The /7 divider is optional when the LVDS PLL is used to generate a
 221          * dot clock for the DU RGB output, without using the LVDS encoder. We
 222          * don't support this configuration yet.
 223          *
 224          * The PLL allowed input frequency range is 12 MHz to 192 MHz.
 225          */
 226
 227         fin = clk_get_rate(clk);
 228         if (fin < 12000000 || fin > 192000000)
 229                 return;
 230
 231         /*
 232          * The comparison frequency range is 12 MHz to 24 MHz, which limits the
 233          * allowed values for the pre-divider M (normal range 1-8).
 234          *
 235          * Fpfd = Fin / M
 236          */
 237         m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
 238         m_max = min_t(unsigned int, 8, fin / 12000000);
 239
 240         for (m = m_min; m <= m_max; ++m) {
 241                 unsigned long fpfd;
 242                 unsigned int n_min;
 243                 unsigned int n_max;
 244                 unsigned int n;
 245
 246                 /*
 247                  * The VCO operating range is 900 Mhz to 1800 MHz, which limits
 248                  * the allowed values for the multiplier N (normal range
 249                  * 60-120).
 250                  *
 251                  * Fvco = Fin * N / M
 252                  */
 253                 fpfd = fin / m;
 254                 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
 255                 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
 256
 257                 for (n = n_min; n < n_max; ++n) {
 258                         unsigned long fvco;
 259                         unsigned int e_min;
 260                         unsigned int e;
 261
 262                         /*
 263                          * The output frequency is limited to 1039.5 MHz,
 264                          * limiting again the allowed values for the
 265                          * post-divider E (normal value 1, 2 or 4).
 266                          *
 267                          * Fout = Fvco / E
 268                          */
 269                         fvco = fpfd * n;
 270                         e_min = fvco > 1039500000 ? 1 : 0;
 271
 272                         for (e = e_min; e < 3; ++e) {
 273                                 unsigned long fout;
 274                                 unsigned long diff;
 275                                 unsigned int div;
 276
 277                                 /*
 278                                  * Finally we have a programable divider after
 279                                  * the PLL, followed by a an optional fixed /7
 280                                  * divider.
 281                                  */
 282                                 fout = fvco / (1 << e) / 7;
 283                                 div = DIV_ROUND_CLOSEST(fout, target);
 284                                 diff = abs(fout / div - target);
 285
 286                                 if (diff < pll->diff) {
 287                                         pll->diff = diff;
 288                                         pll->pll_m = m;
 289                                         pll->pll_n = n;
 290                                         pll->pll_e = e;
 291                                         pll->div = div;
 292                                         pll->clksel = clksel;
 293
 294                                         if (diff == 0)
 295                                                 goto done;
 296                                 }
 297                         }
 298                 }
 299         }
 300
 301 done:
 302         output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
 303                / 7 / pll->div;
 304         error = (long)(output - target) * 10000 / (long)target;
 305
 306         dev_dbg(lvds->dev,
 307                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
 308                 clk, fin, output, target, error / 100,
 309                 error < 0 ? -error % 100 : error % 100,
 310                 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
 311 }
 312
 313 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
 314 {
 315         struct pll_info pll = { .diff = (unsigned long)-1 };
 316         u32 lvdpllcr;
 317
 318         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
 319                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(0));
 320         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
 321                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(1));
 322         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
 323                                  LVDPLLCR_CKSEL_EXTAL);
 324
 325         lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
 326                  | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
 327
 328         if (pll.pll_e > 0)
 329                 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
 330                          |  LVDPLLCR_PLLE(pll.pll_e - 1);
 331
 332         rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
 333
 334         if (pll.div > 1)
 335                 /*
 336                  * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
 337                  * divisor reset.
 338                  */
 339                 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
 340                                 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
 341         else
 342                 rcar_lvds_write(lvds, LVDDIV, 0);
 343 }
 344
 345 /* -----------------------------------------------------------------------------
 346  * Bridge
 347  */
 348
 349 static void rcar_lvds_enable(struct drm_bridge *bridge)
 350 {
 351         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 352         const struct drm_display_mode *mode = &lvds->display_mode;
 353         /*
 354          * FIXME: We should really retrieve the CRTC through the state, but how
 355          * do we get a state pointer?
 356          */
 357         struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
 358         u32 lvdhcr;
 359         u32 lvdcr0;
 360         int ret;
 361
 362         WARN_ON(lvds->enabled);
 363
 364         ret = clk_prepare_enable(lvds->clocks.mod);
 365         if (ret < 0)
 366                 return;
 367
 368         /*
 369          * Hardcode the channels and control signals routing for now.
 370          *
 371          * HSYNC -> CTRL0
 372          * VSYNC -> CTRL1
 373          * DISP  -> CTRL2
 374          * 0     -> CTRL3
 375          */
 376         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 377                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 378                         LVDCTRCR_CTR0SEL_HSYNC);
 379
 380         if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
 381                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 382                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 383         else
 384                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 385                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 386
 387         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 388
 389         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
 390                 /* Disable dual-link mode. */
 391                 rcar_lvds_write(lvds, LVDSTRIPE, 0);
 392         }
 393
 394         /* PLL clock configuration. */
 395         lvds->info->pll_setup(lvds, mode->clock * 1000);
 396
 397         /* Set the LVDS mode and select the input. */
 398         lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
 399         if (drm_crtc_index(crtc) == 2)
 400                 lvdcr0 |= LVDCR0_DUSEL;
 401         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 402
 403         /* Turn all the channels on. */
 404         rcar_lvds_write(lvds, LVDCR1,
 405                         LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
 406                         LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 407
 408         if (lvds->info->gen < 3) {
 409                 /* Enable LVDS operation and turn the bias circuitry on. */
 410                 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
 411                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 412         }
 413
 414         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 415                 /*
 416                  * Turn the PLL on (simple PLL only, extended PLL is fully
 417                  * controlled through LVDPLLCR).
 418                  */
 419                 lvdcr0 |= LVDCR0_PLLON;
 420                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 421         }
 422
 423         if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
 424                 /* Set LVDS normal mode. */
 425                 lvdcr0 |= LVDCR0_PWD;
 426                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 427         }
 428
 429         if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
 430                 /* Turn on the LVDS PHY. */
 431                 lvdcr0 |= LVDCR0_LVEN;
 432                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 433         }
 434
 435         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 436                 /* Wait for the PLL startup delay (simple PLL only). */
 437                 usleep_range(100, 150);
 438         }
 439
 440         /* Turn the output on. */
 441         lvdcr0 |= LVDCR0_LVRES;
 442         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 443
 444         if (lvds->panel) {
 445                 drm_panel_prepare(lvds->panel);
 446                 drm_panel_enable(lvds->panel);
 447         }
 448
 449         lvds->enabled = true;
 450 }
 451
 452 static void rcar_lvds_disable(struct drm_bridge *bridge)
 453 {
 454         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 455
 456         WARN_ON(!lvds->enabled);
 457
 458         if (lvds->panel) {
 459                 drm_panel_disable(lvds->panel);
 460                 drm_panel_unprepare(lvds->panel);
 461         }
 462
 463         rcar_lvds_write(lvds, LVDCR0, 0);
 464         rcar_lvds_write(lvds, LVDCR1, 0);
 465         rcar_lvds_write(lvds, LVDPLLCR, 0);
 466
 467         clk_disable_unprepare(lvds->clocks.mod);
 468
 469         lvds->enabled = false;
 470 }
 471
 472 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
 473                                  const struct drm_display_mode *mode,
 474                                  struct drm_display_mode *adjusted_mode)
 475 {
 476         /*
 477          * The internal LVDS encoder has a restricted clock frequency operating
 478          * range (31MHz to 148.5MHz). Clamp the clock accordingly.
 479          */
 480         adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
 481
 482         return true;
 483 }
 484
 485 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
 486 {
 487         struct drm_display_info *info = &lvds->connector.display_info;
 488         enum rcar_lvds_mode mode;
 489
 490         /*
 491          * There is no API yet to retrieve LVDS mode from a bridge, only panels
 492          * are supported.
 493          */
 494         if (!lvds->panel)
 495                 return;
 496
 497         if (!info->num_bus_formats || !info->bus_formats) {
 498                 dev_err(lvds->dev, "no LVDS bus format reported\n");
 499                 return;
 500         }
 501
 502         switch (info->bus_formats[0]) {
 503         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 504         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 505                 mode = RCAR_LVDS_MODE_JEIDA;
 506                 break;
 507         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 508                 mode = RCAR_LVDS_MODE_VESA;
 509                 break;
 510         default:
 511                 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
 512                         info->bus_formats[0]);
 513                 return;
 514         }
 515
 516         if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
 517                 mode |= RCAR_LVDS_MODE_MIRROR;
 518
 519         lvds->mode = mode;
 520 }
 521
 522 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
 523                                struct drm_display_mode *mode,
 524                                struct drm_display_mode *adjusted_mode)
 525 {
 526         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 527
 528         WARN_ON(lvds->enabled);
 529
 530         lvds->display_mode = *adjusted_mode;
 531
 532         rcar_lvds_get_lvds_mode(lvds);
 533 }
 534
 535 static int rcar_lvds_attach(struct drm_bridge *bridge)
 536 {
 537         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 538         struct drm_connector *connector = &lvds->connector;
 539         struct drm_encoder *encoder = bridge->encoder;
 540         int ret;
 541
 542         /* If we have a next bridge just attach it. */
 543         if (lvds->next_bridge)
 544                 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
 545                                          bridge);
 546
 547         /* Otherwise we have a panel, create a connector. */
 548         ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
 549                                  DRM_MODE_CONNECTOR_LVDS);
 550         if (ret < 0)
 551                 return ret;
 552
 553         drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
 554
 555         ret = drm_connector_attach_encoder(connector, encoder);
 556         if (ret < 0)
 557                 return ret;
 558
 559         return drm_panel_attach(lvds->panel, connector);
 560 }
 561
 562 static void rcar_lvds_detach(struct drm_bridge *bridge)
 563 {
 564         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 565
 566         if (lvds->panel)
 567                 drm_panel_detach(lvds->panel);
 568 }
 569
 570 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
 571         .attach = rcar_lvds_attach,
 572         .detach = rcar_lvds_detach,
 573         .enable = rcar_lvds_enable,
 574         .disable = rcar_lvds_disable,
 575         .mode_fixup = rcar_lvds_mode_fixup,
 576         .mode_set = rcar_lvds_mode_set,
 577 };
 578
 579 /* -----------------------------------------------------------------------------
 580  * Probe & Remove
 581  */
 582
 583 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
 584 {
 585         struct device_node *local_output = NULL;
 586         struct device_node *remote_input = NULL;
 587         struct device_node *remote = NULL;
 588         struct device_node *node;
 589         bool is_bridge = false;
 590         int ret = 0;
 591
 592         local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
 593         if (!local_output) {
 594                 dev_dbg(lvds->dev, "unconnected port@1\n");
 595                 return -ENODEV;
 596         }
 597
 598         /*
 599          * Locate the connected entity and infer its type from the number of
 600          * endpoints.
 601          */
 602         remote = of_graph_get_remote_port_parent(local_output);
 603         if (!remote) {
 604                 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
 605                 ret = -ENODEV;
 606                 goto done;
 607         }
 608
 609         if (!of_device_is_available(remote)) {
 610                 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
 611                         remote);
 612                 ret = -ENODEV;
 613                 goto done;
 614         }
 615
 616         remote_input = of_graph_get_remote_endpoint(local_output);
 617
 618         for_each_endpoint_of_node(remote, node) {
 619                 if (node != remote_input) {
 620                         /*
 621                          * We've found one endpoint other than the input, this
 622                          * must be a bridge.
 623                          */
 624                         is_bridge = true;
 625                         of_node_put(node);
 626                         break;
 627                 }
 628         }
 629
 630         if (is_bridge) {
 631                 lvds->next_bridge = of_drm_find_bridge(remote);
 632                 if (!lvds->next_bridge)
 633                         ret = -EPROBE_DEFER;
 634         } else {
 635                 lvds->panel = of_drm_find_panel(remote);
 636                 if (IS_ERR(lvds->panel))
 637                         ret = PTR_ERR(lvds->panel);
 638         }
 639
 640 done:
 641         of_node_put(local_output);
 642         of_node_put(remote_input);
 643         of_node_put(remote);
 644
 645         return ret;
 646 }
 647
 648 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
 649                                        bool optional)
 650 {
 651         struct clk *clk;
 652
 653         clk = devm_clk_get(lvds->dev, name);
 654         if (!IS_ERR(clk))
 655                 return clk;
 656
 657         if (PTR_ERR(clk) == -ENOENT && optional)
 658                 return NULL;
 659
 660         if (PTR_ERR(clk) != -EPROBE_DEFER)
 661                 dev_err(lvds->dev, "failed to get %s clock\n",
 662                         name ? name : "module");
 663
 664         return clk;
 665 }
 666
 667 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
 668 {
 669         lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
 670         if (IS_ERR(lvds->clocks.mod))
 671                 return PTR_ERR(lvds->clocks.mod);
 672
 673         /*
 674          * LVDS encoders without an extended PLL have no external clock inputs.
 675          */
 676         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
 677                 return 0;
 678
 679         lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
 680         if (IS_ERR(lvds->clocks.extal))
 681                 return PTR_ERR(lvds->clocks.extal);
 682
 683         lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
 684         if (IS_ERR(lvds->clocks.dotclkin[0]))
 685                 return PTR_ERR(lvds->clocks.dotclkin[0]);
 686
 687         lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
 688         if (IS_ERR(lvds->clocks.dotclkin[1]))
 689                 return PTR_ERR(lvds->clocks.dotclkin[1]);
 690
 691         /* At least one input to the PLL must be available. */
 692         if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
 693             !lvds->clocks.dotclkin[1]) {
 694                 dev_err(lvds->dev,
 695                         "no input clock (extal, dclkin.0 or dclkin.1)\n");
 696                 return -EINVAL;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int rcar_lvds_probe(struct platform_device *pdev)
 703 {
 704         struct rcar_lvds *lvds;
 705         struct resource *mem;
 706         int ret;
 707
 708         lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 709         if (lvds == NULL)
 710                 return -ENOMEM;
 711
 712         platform_set_drvdata(pdev, lvds);
 713
 714         lvds->dev = &pdev->dev;
 715         lvds->info = of_device_get_match_data(&pdev->dev);
 716         lvds->enabled = false;
 717
 718         ret = rcar_lvds_parse_dt(lvds);
 719         if (ret < 0)
 720                 return ret;
 721
 722         lvds->bridge.driver_private = lvds;
 723         lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 724         lvds->bridge.of_node = pdev->dev.of_node;
 725
 726         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 727         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 728         if (IS_ERR(lvds->mmio))
 729                 return PTR_ERR(lvds->mmio);
 730
 731         ret = rcar_lvds_get_clocks(lvds);
 732         if (ret < 0)
 733                 return ret;
 734
 735         drm_bridge_add(&lvds->bridge);
 736
 737         return 0;
 738 }
 739
 740 static int rcar_lvds_remove(struct platform_device *pdev)
 741 {
 742         struct rcar_lvds *lvds = platform_get_drvdata(pdev);
 743
 744         drm_bridge_remove(&lvds->bridge);
 745
 746         return 0;
 747 }
 748
 749 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
 750         .gen = 2,
 751         .pll_setup = rcar_lvds_pll_setup_gen2,
 752 };
 753
 754 static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
 755         .gen = 2,
 756         .quirks = RCAR_LVDS_QUIRK_LANES,
 757         .pll_setup = rcar_lvds_pll_setup_gen2,
 758 };
 759
 760 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
 761         .gen = 3,
 762         .quirks = RCAR_LVDS_QUIRK_PWD,
 763         .pll_setup = rcar_lvds_pll_setup_gen3,
 764 };
 765
 766 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
 767         .gen = 3,
 768         .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
 769         .pll_setup = rcar_lvds_pll_setup_gen2,
 770 };
 771
 772 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
 773         .gen = 3,
 774         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
 775                 | RCAR_LVDS_QUIRK_DUAL_LINK,
 776         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 777 };
 778
 779 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
 780         .gen = 3,
 781         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
 782                 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
 783         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 784 };
 785
 786 static const struct of_device_id rcar_lvds_of_table[] = {
 787         { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
 788         { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
 789         { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
 790         { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
 791         { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
 792         { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
 793         { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
 794         { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
 795         { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
 796         { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
 797         { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
 798         { }
 799 };
 800
 801 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
 802
 803 static struct platform_driver rcar_lvds_platform_driver = {
 804         .probe          = rcar_lvds_probe,
 805         .remove         = rcar_lvds_remove,
 806         .driver         = {
 807                 .name   = "rcar-lvds",
 808                 .of_match_table = rcar_lvds_of_table,
 809         },
 810 };
 811
 812 module_platform_driver(rcar_lvds_platform_driver);
 813
 814 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 815 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
 816 MODULE_LICENSE("GPL");