drivers/gpu/drm/radeon/sid.h

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #ifndef SI_H
  25 #define SI_H
  26
  27 #define CG_MULT_THERMAL_STATUS                                  0x714
  28 #define         ASIC_MAX_TEMP(x)                                ((x) << 0)
  29 #define         ASIC_MAX_TEMP_MASK                              0x000001ff
  30 #define         ASIC_MAX_TEMP_SHIFT                             0
  31 #define         CTF_TEMP(x)                                     ((x) << 9)
  32 #define         CTF_TEMP_MASK                                   0x0003fe00
  33 #define         CTF_TEMP_SHIFT                                  9
  34
  35 #define SI_MAX_SH_GPRS           256
  36 #define SI_MAX_TEMP_GPRS         16
  37 #define SI_MAX_SH_THREADS        256
  38 #define SI_MAX_SH_STACK_ENTRIES  4096
  39 #define SI_MAX_FRC_EOV_CNT       16384
  40 #define SI_MAX_BACKENDS          8
  41 #define SI_MAX_BACKENDS_MASK     0xFF
  42 #define SI_MAX_BACKENDS_PER_SE_MASK     0x0F
  43 #define SI_MAX_SIMDS             12
  44 #define SI_MAX_SIMDS_MASK        0x0FFF
  45 #define SI_MAX_SIMDS_PER_SE_MASK        0x00FF
  46 #define SI_MAX_PIPES             8
  47 #define SI_MAX_PIPES_MASK        0xFF
  48 #define SI_MAX_PIPES_PER_SIMD_MASK      0x3F
  49 #define SI_MAX_LDS_NUM           0xFFFF
  50 #define SI_MAX_TCC               16
  51 #define SI_MAX_TCC_MASK          0xFFFF
  52
  53 #define VGA_HDP_CONTROL                                 0x328
  54 #define         VGA_MEMORY_DISABLE                              (1 << 4)
  55
  56 #define DMIF_ADDR_CONFIG                                0xBD4
  57
  58 #define SRBM_STATUS                                     0xE50
  59
  60 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
  61 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
  62
  63 #define VM_L2_CNTL                                      0x1400
  64 #define         ENABLE_L2_CACHE                                 (1 << 0)
  65 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
  66 #define         L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)                ((x) << 2)
  67 #define         L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)                ((x) << 4)
  68 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
  69 #define         ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE        (1 << 10)
  70 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 15)
  71 #define         CONTEXT1_IDENTITY_ACCESS_MODE(x)                (((x) & 3) << 19)
  72 #define VM_L2_CNTL2                                     0x1404
  73 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
  74 #define         INVALIDATE_L2_CACHE                             (1 << 1)
  75 #define         INVALIDATE_CACHE_MODE(x)                        ((x) << 26)
  76 #define                 INVALIDATE_PTE_AND_PDE_CACHES           0
  77 #define                 INVALIDATE_ONLY_PTE_CACHES              1
  78 #define                 INVALIDATE_ONLY_PDE_CACHES              2
  79 #define VM_L2_CNTL3                                     0x1408
  80 #define         BANK_SELECT(x)                                  ((x) << 0)
  81 #define         L2_CACHE_UPDATE_MODE(x)                         ((x) << 6)
  82 #define         L2_CACHE_BIGK_FRAGMENT_SIZE(x)                  ((x) << 15)
  83 #define         L2_CACHE_BIGK_ASSOCIATIVITY                     (1 << 20)
  84 #define VM_L2_STATUS                                    0x140C
  85 #define         L2_BUSY                                         (1 << 0)
  86 #define VM_CONTEXT0_CNTL                                0x1410
  87 #define         ENABLE_CONTEXT                                  (1 << 0)
  88 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
  89 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
  90 #define VM_CONTEXT1_CNTL                                0x1414
  91 #define VM_CONTEXT0_CNTL2                               0x1430
  92 #define VM_CONTEXT1_CNTL2                               0x1434
  93 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR                0x1438
  94 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR                0x143c
  95 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR               0x1440
  96 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR               0x1444
  97 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR               0x1448
  98 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR               0x144c
  99 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR               0x1450
 100 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR               0x1454
 101
 102 #define VM_INVALIDATE_REQUEST                           0x1478
 103 #define VM_INVALIDATE_RESPONSE                          0x147c
 104
 105 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
 106 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR       0x151c
 107
 108 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153c
 109 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR                0x1540
 110 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR                0x1544
 111 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR                0x1548
 112 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR                0x154c
 113 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR                0x1550
 114 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR                0x1554
 115 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR                0x1558
 116 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155c
 117 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR               0x1560
 118
 119 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
 120 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR                 0x1580
 121
 122 #define MC_SHARED_CHMAP                                         0x2004
 123 #define         NOOFCHAN_SHIFT                                  12
 124 #define         NOOFCHAN_MASK                                   0x0000f000
 125 #define MC_SHARED_CHREMAP                                       0x2008
 126
 127 #define MC_VM_FB_LOCATION                               0x2024
 128 #define MC_VM_AGP_TOP                                   0x2028
 129 #define MC_VM_AGP_BOT                                   0x202C
 130 #define MC_VM_AGP_BASE                                  0x2030
 131 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
 132 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
 133 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
 134
 135 #define MC_VM_MX_L1_TLB_CNTL                            0x2064
 136 #define         ENABLE_L1_TLB                                   (1 << 0)
 137 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
 138 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
 139 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
 140 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
 141 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
 142 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
 143 #define         ENABLE_ADVANCED_DRIVER_MODEL                    (1 << 6)
 144
 145 #define MC_ARB_RAMCFG                                   0x2760
 146 #define         NOOFBANK_SHIFT                                  0
 147 #define         NOOFBANK_MASK                                   0x00000003
 148 #define         NOOFRANK_SHIFT                                  2
 149 #define         NOOFRANK_MASK                                   0x00000004
 150 #define         NOOFROWS_SHIFT                                  3
 151 #define         NOOFROWS_MASK                                   0x00000038
 152 #define         NOOFCOLS_SHIFT                                  6
 153 #define         NOOFCOLS_MASK                                   0x000000C0
 154 #define         CHANSIZE_SHIFT                                  8
 155 #define         CHANSIZE_MASK                                   0x00000100
 156 #define         CHANSIZE_OVERRIDE                               (1 << 11)
 157 #define         NOOFGROUPS_SHIFT                                12
 158 #define         NOOFGROUPS_MASK                                 0x00001000
 159
 160 #define HDP_HOST_PATH_CNTL                              0x2C00
 161 #define HDP_NONSURFACE_BASE                             0x2C04
 162 #define HDP_NONSURFACE_INFO                             0x2C08
 163 #define HDP_NONSURFACE_SIZE                             0x2C0C
 164
 165 #define HDP_ADDR_CONFIG                                 0x2F48
 166 #define HDP_MISC_CNTL                                   0x2F4C
 167 #define         HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
 168
 169 #define CONFIG_MEMSIZE                                  0x5428
 170
 171 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
 172
 173 #define BIF_FB_EN                                               0x5490
 174 #define         FB_READ_EN                                      (1 << 0)
 175 #define         FB_WRITE_EN                                     (1 << 1)
 176
 177 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
 178
 179 #define DC_LB_MEMORY_SPLIT                                      0x6b0c
 180 #define         DC_LB_MEMORY_CONFIG(x)                          ((x) << 20)
 181
 182 #define PRIORITY_A_CNT                                          0x6b18
 183 #define         PRIORITY_MARK_MASK                              0x7fff
 184 #define         PRIORITY_OFF                                    (1 << 16)
 185 #define         PRIORITY_ALWAYS_ON                              (1 << 20)
 186 #define PRIORITY_B_CNT                                          0x6b1c
 187
 188 #define DPG_PIPE_ARBITRATION_CONTROL3                           0x6cc8
 189 #       define LATENCY_WATERMARK_MASK(x)                        ((x) << 16)
 190 #define DPG_PIPE_LATENCY_CONTROL                                0x6ccc
 191 #       define LATENCY_LOW_WATERMARK(x)                         ((x) << 0)
 192 #       define LATENCY_HIGH_WATERMARK(x)                        ((x) << 16)
 193
 194 #define GRBM_CNTL                                       0x8000
 195 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
 196
 197 #define GRBM_STATUS2                                    0x8008
 198 #define         RLC_RQ_PENDING                                  (1 << 0)
 199 #define         RLC_BUSY                                        (1 << 8)
 200 #define         TC_BUSY                                         (1 << 9)
 201
 202 #define GRBM_STATUS                                     0x8010
 203 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
 204 #define         RING2_RQ_PENDING                                (1 << 4)
 205 #define         SRBM_RQ_PENDING                                 (1 << 5)
 206 #define         RING1_RQ_PENDING                                (1 << 6)
 207 #define         CF_RQ_PENDING                                   (1 << 7)
 208 #define         PF_RQ_PENDING                                   (1 << 8)
 209 #define         GDS_DMA_RQ_PENDING                              (1 << 9)
 210 #define         GRBM_EE_BUSY                                    (1 << 10)
 211 #define         DB_CLEAN                                        (1 << 12)
 212 #define         CB_CLEAN                                        (1 << 13)
 213 #define         TA_BUSY                                         (1 << 14)
 214 #define         GDS_BUSY                                        (1 << 15)
 215 #define         VGT_BUSY                                        (1 << 17)
 216 #define         IA_BUSY_NO_DMA                                  (1 << 18)
 217 #define         IA_BUSY                                         (1 << 19)
 218 #define         SX_BUSY                                         (1 << 20)
 219 #define         SPI_BUSY                                        (1 << 22)
 220 #define         BCI_BUSY                                        (1 << 23)
 221 #define         SC_BUSY                                         (1 << 24)
 222 #define         PA_BUSY                                         (1 << 25)
 223 #define         DB_BUSY                                         (1 << 26)
 224 #define         CP_COHERENCY_BUSY                               (1 << 28)
 225 #define         CP_BUSY                                         (1 << 29)
 226 #define         CB_BUSY                                         (1 << 30)
 227 #define         GUI_ACTIVE                                      (1 << 31)
 228 #define GRBM_STATUS_SE0                                 0x8014
 229 #define GRBM_STATUS_SE1                                 0x8018
 230 #define         SE_DB_CLEAN                                     (1 << 1)
 231 #define         SE_CB_CLEAN                                     (1 << 2)
 232 #define         SE_BCI_BUSY                                     (1 << 22)
 233 #define         SE_VGT_BUSY                                     (1 << 23)
 234 #define         SE_PA_BUSY                                      (1 << 24)
 235 #define         SE_TA_BUSY                                      (1 << 25)
 236 #define         SE_SX_BUSY                                      (1 << 26)
 237 #define         SE_SPI_BUSY                                     (1 << 27)
 238 #define         SE_SC_BUSY                                      (1 << 29)
 239 #define         SE_DB_BUSY                                      (1 << 30)
 240 #define         SE_CB_BUSY                                      (1 << 31)
 241
 242 #define GRBM_SOFT_RESET                                 0x8020
 243 #define         SOFT_RESET_CP                                   (1 << 0)
 244 #define         SOFT_RESET_CB                                   (1 << 1)
 245 #define         SOFT_RESET_RLC                                  (1 << 2)
 246 #define         SOFT_RESET_DB                                   (1 << 3)
 247 #define         SOFT_RESET_GDS                                  (1 << 4)
 248 #define         SOFT_RESET_PA                                   (1 << 5)
 249 #define         SOFT_RESET_SC                                   (1 << 6)
 250 #define         SOFT_RESET_BCI                                  (1 << 7)
 251 #define         SOFT_RESET_SPI                                  (1 << 8)
 252 #define         SOFT_RESET_SX                                   (1 << 10)
 253 #define         SOFT_RESET_TC                                   (1 << 11)
 254 #define         SOFT_RESET_TA                                   (1 << 12)
 255 #define         SOFT_RESET_VGT                                  (1 << 14)
 256 #define         SOFT_RESET_IA                                   (1 << 15)
 257
 258 #define GRBM_GFX_INDEX                                  0x802C
 259
 260 #define CP_ME_CNTL                                      0x86D8
 261 #define         CP_CE_HALT                                      (1 << 24)
 262 #define         CP_PFP_HALT                                     (1 << 26)
 263 #define         CP_ME_HALT                                      (1 << 28)
 264
 265 #define CP_RB0_RPTR                                     0x8700
 266
 267 #define CP_QUEUE_THRESHOLDS                             0x8760
 268 #define         ROQ_IB1_START(x)                                ((x) << 0)
 269 #define         ROQ_IB2_START(x)                                ((x) << 8)
 270 #define CP_MEQ_THRESHOLDS                               0x8764
 271 #define         MEQ1_START(x)                           ((x) << 0)
 272 #define         MEQ2_START(x)                           ((x) << 8)
 273
 274 #define CP_PERFMON_CNTL                                 0x87FC
 275
 276 #define VGT_VTX_VECT_EJECT_REG                          0x88B0
 277
 278 #define VGT_CACHE_INVALIDATION                          0x88C4
 279 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
 280 #define                 VC_ONLY                                         0
 281 #define                 TC_ONLY                                         1
 282 #define                 VC_AND_TC                                       2
 283 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
 284 #define                 NO_AUTO                                         0
 285 #define                 ES_AUTO                                         1
 286 #define                 GS_AUTO                                         2
 287 #define                 ES_AND_GS_AUTO                                  3
 288 #define VGT_ESGS_RING_SIZE                              0x88C8
 289 #define VGT_GSVS_RING_SIZE                              0x88CC
 290
 291 #define VGT_GS_VERTEX_REUSE                             0x88D4
 292
 293 #define VGT_PRIMITIVE_TYPE                              0x8958
 294 #define VGT_INDEX_TYPE                                  0x895C
 295
 296 #define VGT_NUM_INDICES                                 0x8970
 297 #define VGT_NUM_INSTANCES                               0x8974
 298
 299 #define VGT_TF_RING_SIZE                                0x8988
 300
 301 #define VGT_HS_OFFCHIP_PARAM                            0x89B0
 302
 303 #define VGT_TF_MEMORY_BASE                              0x89B8
 304
 305 #define CC_GC_SHADER_ARRAY_CONFIG                       0x89bc
 306 #define GC_USER_SHADER_ARRAY_CONFIG                     0x89c0
 307
 308 #define PA_CL_ENHANCE                                   0x8A14
 309 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
 310 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
 311
 312 #define PA_SU_LINE_STIPPLE_VALUE                        0x8A60
 313
 314 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
 315
 316 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
 317 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
 318 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
 319
 320 #define PA_SC_FIFO_SIZE                                 0x8BCC
 321 #define         SC_FRONTEND_PRIM_FIFO_SIZE(x)                   ((x) << 0)
 322 #define         SC_BACKEND_PRIM_FIFO_SIZE(x)                    ((x) << 6)
 323 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 15)
 324 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 23)
 325
 326 #define PA_SC_ENHANCE                                   0x8BF0
 327
 328 #define SQ_CONFIG                                       0x8C00
 329
 330 #define SQC_CACHES                                      0x8C08
 331
 332 #define SX_DEBUG_1                                      0x9060
 333
 334 #define SPI_STATIC_THREAD_MGMT_1                        0x90E0
 335 #define SPI_STATIC_THREAD_MGMT_2                        0x90E4
 336 #define SPI_STATIC_THREAD_MGMT_3                        0x90E8
 337 #define SPI_PS_MAX_WAVE_ID                              0x90EC
 338
 339 #define SPI_CONFIG_CNTL                                 0x9100
 340
 341 #define SPI_CONFIG_CNTL_1                               0x913C
 342 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
 343 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
 344
 345 #define CGTS_TCC_DISABLE                                0x9148
 346 #define CGTS_USER_TCC_DISABLE                           0x914C
 347 #define         TCC_DISABLE_MASK                                0xFFFF0000
 348 #define         TCC_DISABLE_SHIFT                               16
 349
 350 #define TA_CNTL_AUX                                     0x9508
 351
 352 #define CC_RB_BACKEND_DISABLE                           0x98F4
 353 #define         BACKEND_DISABLE(x)                      ((x) << 16)
 354 #define GB_ADDR_CONFIG                                  0x98F8
 355 #define         NUM_PIPES(x)                            ((x) << 0)
 356 #define         NUM_PIPES_MASK                          0x00000007
 357 #define         NUM_PIPES_SHIFT                         0
 358 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
 359 #define         PIPE_INTERLEAVE_SIZE_MASK               0x00000070
 360 #define         PIPE_INTERLEAVE_SIZE_SHIFT              4
 361 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
 362 #define         NUM_SHADER_ENGINES_MASK                 0x00003000
 363 #define         NUM_SHADER_ENGINES_SHIFT                12
 364 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
 365 #define         SHADER_ENGINE_TILE_SIZE_MASK            0x00070000
 366 #define         SHADER_ENGINE_TILE_SIZE_SHIFT           16
 367 #define         NUM_GPUS(x)                             ((x) << 20)
 368 #define         NUM_GPUS_MASK                           0x00700000
 369 #define         NUM_GPUS_SHIFT                          20
 370 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
 371 #define         MULTI_GPU_TILE_SIZE_MASK                0x03000000
 372 #define         MULTI_GPU_TILE_SIZE_SHIFT               24
 373 #define         ROW_SIZE(x)                             ((x) << 28)
 374 #define         ROW_SIZE_MASK                           0x30000000
 375 #define         ROW_SIZE_SHIFT                          28
 376
 377 #define GB_TILE_MODE0                                   0x9910
 378 #       define MICRO_TILE_MODE(x)                               ((x) << 0)
 379 #              define   ADDR_SURF_DISPLAY_MICRO_TILING          0
 380 #              define   ADDR_SURF_THIN_MICRO_TILING             1
 381 #              define   ADDR_SURF_DEPTH_MICRO_TILING            2
 382 #       define ARRAY_MODE(x)                                    ((x) << 2)
 383 #              define   ARRAY_LINEAR_GENERAL                    0
 384 #              define   ARRAY_LINEAR_ALIGNED                    1
 385 #              define   ARRAY_1D_TILED_THIN1                    2
 386 #              define   ARRAY_2D_TILED_THIN1                    4
 387 #       define PIPE_CONFIG(x)                                   ((x) << 6)
 388 #              define   ADDR_SURF_P2                            0
 389 #              define   ADDR_SURF_P4_8x16                       4
 390 #              define   ADDR_SURF_P4_16x16                      5
 391 #              define   ADDR_SURF_P4_16x32                      6
 392 #              define   ADDR_SURF_P4_32x32                      7
 393 #              define   ADDR_SURF_P8_16x16_8x16                 8
 394 #              define   ADDR_SURF_P8_16x32_8x16                 9
 395 #              define   ADDR_SURF_P8_32x32_8x16                 10
 396 #              define   ADDR_SURF_P8_16x32_16x16                11
 397 #              define   ADDR_SURF_P8_32x32_16x16                12
 398 #              define   ADDR_SURF_P8_32x32_16x32                13
 399 #              define   ADDR_SURF_P8_32x64_32x32                14
 400 #       define TILE_SPLIT(x)                                    ((x) << 11)
 401 #              define   ADDR_SURF_TILE_SPLIT_64B                0
 402 #              define   ADDR_SURF_TILE_SPLIT_128B               1
 403 #              define   ADDR_SURF_TILE_SPLIT_256B               2
 404 #              define   ADDR_SURF_TILE_SPLIT_512B               3
 405 #              define   ADDR_SURF_TILE_SPLIT_1KB                4
 406 #              define   ADDR_SURF_TILE_SPLIT_2KB                5
 407 #              define   ADDR_SURF_TILE_SPLIT_4KB                6
 408 #       define BANK_WIDTH(x)                                    ((x) << 14)
 409 #              define   ADDR_SURF_BANK_WIDTH_1                  0
 410 #              define   ADDR_SURF_BANK_WIDTH_2                  1
 411 #              define   ADDR_SURF_BANK_WIDTH_4                  2
 412 #              define   ADDR_SURF_BANK_WIDTH_8                  3
 413 #       define BANK_HEIGHT(x)                                   ((x) << 16)
 414 #              define   ADDR_SURF_BANK_HEIGHT_1                 0
 415 #              define   ADDR_SURF_BANK_HEIGHT_2                 1
 416 #              define   ADDR_SURF_BANK_HEIGHT_4                 2
 417 #              define   ADDR_SURF_BANK_HEIGHT_8                 3
 418 #       define MACRO_TILE_ASPECT(x)                             ((x) << 18)
 419 #              define   ADDR_SURF_MACRO_ASPECT_1                0
 420 #              define   ADDR_SURF_MACRO_ASPECT_2                1
 421 #              define   ADDR_SURF_MACRO_ASPECT_4                2
 422 #              define   ADDR_SURF_MACRO_ASPECT_8                3
 423 #       define NUM_BANKS(x)                                     ((x) << 20)
 424 #              define   ADDR_SURF_2_BANK                        0
 425 #              define   ADDR_SURF_4_BANK                        1
 426 #              define   ADDR_SURF_8_BANK                        2
 427 #              define   ADDR_SURF_16_BANK                       3
 428
 429 #define CB_PERFCOUNTER0_SELECT0                         0x9a20
 430 #define CB_PERFCOUNTER0_SELECT1                         0x9a24
 431 #define CB_PERFCOUNTER1_SELECT0                         0x9a28
 432 #define CB_PERFCOUNTER1_SELECT1                         0x9a2c
 433 #define CB_PERFCOUNTER2_SELECT0                         0x9a30
 434 #define CB_PERFCOUNTER2_SELECT1                         0x9a34
 435 #define CB_PERFCOUNTER3_SELECT0                         0x9a38
 436 #define CB_PERFCOUNTER3_SELECT1                         0x9a3c
 437
 438 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
 439 #define         BACKEND_DISABLE_MASK                    0x00FF0000
 440 #define         BACKEND_DISABLE_SHIFT                   16
 441
 442 #define TCP_CHAN_STEER_LO                               0xac0c
 443 #define TCP_CHAN_STEER_HI                               0xac10
 444
 445 /*
 446  * PM4
 447  */
 448 #define PACKET_TYPE0    0
 449 #define PACKET_TYPE1    1
 450 #define PACKET_TYPE2    2
 451 #define PACKET_TYPE3    3
 452
 453 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
 454 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
 455 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
 456 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
 457 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
 458                          (((reg) >> 2) & 0xFFFF) |                      \
 459                          ((n) & 0x3FFF) << 16)
 460 #define CP_PACKET2                      0x80000000
 461 #define         PACKET2_PAD_SHIFT               0
 462 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
 463
 464 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
 465
 466 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
 467                          (((op) & 0xFF) << 8) |                         \
 468                          ((n) & 0x3FFF) << 16)
 469
 470 /* Packet 3 types */
 471 #define PACKET3_NOP                                     0x10
 472 #define PACKET3_SET_BASE                                0x11
 473 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
 474 #define                 GDS_PARTITION_BASE              2
 475 #define                 CE_PARTITION_BASE               3
 476 #define PACKET3_CLEAR_STATE                             0x12
 477 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
 478 #define PACKET3_DISPATCH_DIRECT                         0x15
 479 #define PACKET3_DISPATCH_INDIRECT                       0x16
 480 #define PACKET3_ALLOC_GDS                               0x1B
 481 #define PACKET3_WRITE_GDS_RAM                           0x1C
 482 #define PACKET3_ATOMIC_GDS                              0x1D
 483 #define PACKET3_ATOMIC                                  0x1E
 484 #define PACKET3_OCCLUSION_QUERY                         0x1F
 485 #define PACKET3_SET_PREDICATION                         0x20
 486 #define PACKET3_REG_RMW                                 0x21
 487 #define PACKET3_COND_EXEC                               0x22
 488 #define PACKET3_PRED_EXEC                               0x23
 489 #define PACKET3_DRAW_INDIRECT                           0x24
 490 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
 491 #define PACKET3_INDEX_BASE                              0x26
 492 #define PACKET3_DRAW_INDEX_2                            0x27
 493 #define PACKET3_CONTEXT_CONTROL                         0x28
 494 #define PACKET3_INDEX_TYPE                              0x2A
 495 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
 496 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
 497 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
 498 #define PACKET3_NUM_INSTANCES                           0x2F
 499 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
 500 #define PACKET3_INDIRECT_BUFFER_CONST                   0x31
 501 #define PACKET3_INDIRECT_BUFFER                         0x32
 502 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
 503 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
 504 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
 505 #define PACKET3_WRITE_DATA                              0x37
 506 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 507 #define PACKET3_MEM_SEMAPHORE                           0x39
 508 #define PACKET3_MPEG_INDEX                              0x3A
 509 #define PACKET3_COPY_DW                                 0x3B
 510 #define PACKET3_WAIT_REG_MEM                            0x3C
 511 #define PACKET3_MEM_WRITE                               0x3D
 512 #define PACKET3_COPY_DATA                               0x40
 513 #define PACKET3_PFP_SYNC_ME                             0x42
 514 #define PACKET3_SURFACE_SYNC                            0x43
 515 #              define PACKET3_DEST_BASE_0_ENA      (1 << 0)
 516 #              define PACKET3_DEST_BASE_1_ENA      (1 << 1)
 517 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
 518 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
 519 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
 520 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
 521 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
 522 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
 523 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
 524 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
 525 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
 526 #              define PACKET3_DEST_BASE_2_ENA      (1 << 19)
 527 #              define PACKET3_DEST_BASE_3_ENA      (1 << 21)
 528 #              define PACKET3_TCL1_ACTION_ENA      (1 << 22)
 529 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
 530 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
 531 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
 532 #              define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
 533 #              define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
 534 #define PACKET3_ME_INITIALIZE                           0x44
 535 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
 536 #define PACKET3_COND_WRITE                              0x45
 537 #define PACKET3_EVENT_WRITE                             0x46
 538 #define PACKET3_EVENT_WRITE_EOP                         0x47
 539 #define PACKET3_EVENT_WRITE_EOS                         0x48
 540 #define PACKET3_PREAMBLE_CNTL                           0x4A
 541 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
 542 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
 543 #define PACKET3_ONE_REG_WRITE                           0x57
 544 #define PACKET3_LOAD_CONFIG_REG                         0x5F
 545 #define PACKET3_LOAD_CONTEXT_REG                        0x60
 546 #define PACKET3_LOAD_SH_REG                             0x61
 547 #define PACKET3_SET_CONFIG_REG                          0x68
 548 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
 549 #define         PACKET3_SET_CONFIG_REG_END                      0x0000b000
 550 #define PACKET3_SET_CONTEXT_REG                         0x69
 551 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
 552 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
 553 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
 554 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
 555 #define PACKET3_SET_SH_REG                              0x76
 556 #define         PACKET3_SET_SH_REG_START                        0x0000b000
 557 #define         PACKET3_SET_SH_REG_END                          0x0000c000
 558 #define PACKET3_SET_SH_REG_OFFSET                       0x77
 559 #define PACKET3_ME_WRITE                                0x7A
 560 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
 561 #define PACKET3_SCRATCH_RAM_READ                        0x7E
 562 #define PACKET3_CE_WRITE                                0x7F
 563 #define PACKET3_LOAD_CONST_RAM                          0x80
 564 #define PACKET3_WRITE_CONST_RAM                         0x81
 565 #define PACKET3_WRITE_CONST_RAM_OFFSET                  0x82
 566 #define PACKET3_DUMP_CONST_RAM                          0x83
 567 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
 568 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
 569 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
 570 #define PACKET3_WAIT_ON_DE_COUNTER                      0x87
 571 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
 572 #define PACKET3_SET_CE_DE_COUNTERS                      0x89
 573 #define PACKET3_WAIT_ON_AVAIL_BUFFER                    0x8A
 574
 575 #endif