2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
32 #define CG_MULT_THERMAL_STATUS 0x714
33 #define ASIC_MAX_TEMP(x) ((x) << 0)
34 #define ASIC_MAX_TEMP_MASK 0x000001ff
35 #define ASIC_MAX_TEMP_SHIFT 0
36 #define CTF_TEMP(x) ((x) << 9)
37 #define CTF_TEMP_MASK 0x0003fe00
38 #define CTF_TEMP_SHIFT 9
40 #define SI_MAX_SH_GPRS 256
41 #define SI_MAX_TEMP_GPRS 16
42 #define SI_MAX_SH_THREADS 256
43 #define SI_MAX_SH_STACK_ENTRIES 4096
44 #define SI_MAX_FRC_EOV_CNT 16384
45 #define SI_MAX_BACKENDS 8
46 #define SI_MAX_BACKENDS_MASK 0xFF
47 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
48 #define SI_MAX_SIMDS 12
49 #define SI_MAX_SIMDS_MASK 0x0FFF
50 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
51 #define SI_MAX_PIPES 8
52 #define SI_MAX_PIPES_MASK 0xFF
53 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
54 #define SI_MAX_LDS_NUM 0xFFFF
56 #define SI_MAX_TCC_MASK 0xFFFF
58 #define VGA_HDP_CONTROL 0x328
59 #define VGA_MEMORY_DISABLE (1 << 4)
61 #define DMIF_ADDR_CONFIG 0xBD4
63 #define SRBM_STATUS 0xE50
64 #define GRBM_RQ_PENDING (1 << 5)
65 #define VMC_BUSY (1 << 8)
66 #define MCB_BUSY (1 << 9)
67 #define MCB_NON_DISPLAY_BUSY (1 << 10)
68 #define MCC_BUSY (1 << 11)
69 #define MCD_BUSY (1 << 12)
70 #define SEM_BUSY (1 << 14)
71 #define IH_BUSY (1 << 17)
73 #define SRBM_SOFT_RESET 0x0E60
74 #define SOFT_RESET_BIF (1 << 1)
75 #define SOFT_RESET_DC (1 << 5)
76 #define SOFT_RESET_DMA1 (1 << 6)
77 #define SOFT_RESET_GRBM (1 << 8)
78 #define SOFT_RESET_HDP (1 << 9)
79 #define SOFT_RESET_IH (1 << 10)
80 #define SOFT_RESET_MC (1 << 11)
81 #define SOFT_RESET_ROM (1 << 14)
82 #define SOFT_RESET_SEM (1 << 15)
83 #define SOFT_RESET_VMC (1 << 17)
84 #define SOFT_RESET_DMA (1 << 20)
85 #define SOFT_RESET_TST (1 << 21)
86 #define SOFT_RESET_REGBB (1 << 22)
87 #define SOFT_RESET_ORB (1 << 23)
89 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
90 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
92 #define SRBM_STATUS2 0x0EC4
93 #define DMA_BUSY (1 << 5)
94 #define DMA1_BUSY (1 << 6)
96 #define VM_L2_CNTL 0x1400
97 #define ENABLE_L2_CACHE (1 << 0)
98 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
99 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
100 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
101 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
102 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
103 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
104 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
105 #define VM_L2_CNTL2 0x1404
106 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
107 #define INVALIDATE_L2_CACHE (1 << 1)
108 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
109 #define INVALIDATE_PTE_AND_PDE_CACHES 0
110 #define INVALIDATE_ONLY_PTE_CACHES 1
111 #define INVALIDATE_ONLY_PDE_CACHES 2
112 #define VM_L2_CNTL3 0x1408
113 #define BANK_SELECT(x) ((x) << 0)
114 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
115 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
116 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
117 #define VM_L2_STATUS 0x140C
118 #define L2_BUSY (1 << 0)
119 #define VM_CONTEXT0_CNTL 0x1410
120 #define ENABLE_CONTEXT (1 << 0)
121 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
122 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
123 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
124 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
125 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
126 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
127 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
128 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
129 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
130 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
131 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
132 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
133 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
134 #define VM_CONTEXT1_CNTL 0x1414
135 #define VM_CONTEXT0_CNTL2 0x1430
136 #define VM_CONTEXT1_CNTL2 0x1434
137 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
138 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
139 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
140 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
141 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
142 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
143 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
144 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
146 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
147 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
149 #define VM_INVALIDATE_REQUEST 0x1478
150 #define VM_INVALIDATE_RESPONSE 0x147c
152 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
153 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
155 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
156 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
157 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
158 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
159 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
160 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
161 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
162 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
163 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
164 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
166 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
167 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
169 #define MC_SHARED_CHMAP 0x2004
170 #define NOOFCHAN_SHIFT 12
171 #define NOOFCHAN_MASK 0x0000f000
172 #define MC_SHARED_CHREMAP 0x2008
174 #define MC_VM_FB_LOCATION 0x2024
175 #define MC_VM_AGP_TOP 0x2028
176 #define MC_VM_AGP_BOT 0x202C
177 #define MC_VM_AGP_BASE 0x2030
178 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
179 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
180 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
182 #define MC_VM_MX_L1_TLB_CNTL 0x2064
183 #define ENABLE_L1_TLB (1 << 0)
184 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
185 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
186 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
187 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
188 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
189 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
190 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
192 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
194 #define MC_ARB_RAMCFG 0x2760
195 #define NOOFBANK_SHIFT 0
196 #define NOOFBANK_MASK 0x00000003
197 #define NOOFRANK_SHIFT 2
198 #define NOOFRANK_MASK 0x00000004
199 #define NOOFROWS_SHIFT 3
200 #define NOOFROWS_MASK 0x00000038
201 #define NOOFCOLS_SHIFT 6
202 #define NOOFCOLS_MASK 0x000000C0
203 #define CHANSIZE_SHIFT 8
204 #define CHANSIZE_MASK 0x00000100
205 #define CHANSIZE_OVERRIDE (1 << 11)
206 #define NOOFGROUPS_SHIFT 12
207 #define NOOFGROUPS_MASK 0x00001000
209 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
210 #define TRAIN_DONE_D0 (1 << 30)
211 #define TRAIN_DONE_D1 (1 << 31)
213 #define MC_SEQ_SUP_CNTL 0x28c8
214 #define RUN_MASK (1 << 0)
215 #define MC_SEQ_SUP_PGM 0x28cc
217 #define MC_IO_PAD_CNTL_D0 0x29d0
218 #define MEM_FALL_OUT_CMD (1 << 8)
220 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
221 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
223 #define HDP_HOST_PATH_CNTL 0x2C00
224 #define HDP_NONSURFACE_BASE 0x2C04
225 #define HDP_NONSURFACE_INFO 0x2C08
226 #define HDP_NONSURFACE_SIZE 0x2C0C
228 #define HDP_ADDR_CONFIG 0x2F48
229 #define HDP_MISC_CNTL 0x2F4C
230 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
232 #define IH_RB_CNTL 0x3e00
233 # define IH_RB_ENABLE (1 << 0)
234 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
235 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
236 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
237 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
238 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
239 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
240 #define IH_RB_BASE 0x3e04
241 #define IH_RB_RPTR 0x3e08
242 #define IH_RB_WPTR 0x3e0c
243 # define RB_OVERFLOW (1 << 0)
244 # define WPTR_OFFSET_MASK 0x3fffc
245 #define IH_RB_WPTR_ADDR_HI 0x3e10
246 #define IH_RB_WPTR_ADDR_LO 0x3e14
247 #define IH_CNTL 0x3e18
248 # define ENABLE_INTR (1 << 0)
249 # define IH_MC_SWAP(x) ((x) << 1)
250 # define IH_MC_SWAP_NONE 0
251 # define IH_MC_SWAP_16BIT 1
252 # define IH_MC_SWAP_32BIT 2
253 # define IH_MC_SWAP_64BIT 3
254 # define RPTR_REARM (1 << 4)
255 # define MC_WRREQ_CREDIT(x) ((x) << 15)
256 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
257 # define MC_VMID(x) ((x) << 25)
259 #define CONFIG_MEMSIZE 0x5428
261 #define INTERRUPT_CNTL 0x5468
262 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
263 # define IH_DUMMY_RD_EN (1 << 1)
264 # define IH_REQ_NONSNOOP_EN (1 << 3)
265 # define GEN_IH_INT_EN (1 << 8)
266 #define INTERRUPT_CNTL2 0x546c
268 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
270 #define BIF_FB_EN 0x5490
271 #define FB_READ_EN (1 << 0)
272 #define FB_WRITE_EN (1 << 1)
274 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
276 #define DC_LB_MEMORY_SPLIT 0x6b0c
277 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
279 #define PRIORITY_A_CNT 0x6b18
280 #define PRIORITY_MARK_MASK 0x7fff
281 #define PRIORITY_OFF (1 << 16)
282 #define PRIORITY_ALWAYS_ON (1 << 20)
283 #define PRIORITY_B_CNT 0x6b1c
285 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
286 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
287 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
288 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
289 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
291 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
292 #define VLINE_STATUS 0x6bb8
293 # define VLINE_OCCURRED (1 << 0)
294 # define VLINE_ACK (1 << 4)
295 # define VLINE_STAT (1 << 12)
296 # define VLINE_INTERRUPT (1 << 16)
297 # define VLINE_INTERRUPT_TYPE (1 << 17)
298 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
299 #define VBLANK_STATUS 0x6bbc
300 # define VBLANK_OCCURRED (1 << 0)
301 # define VBLANK_ACK (1 << 4)
302 # define VBLANK_STAT (1 << 12)
303 # define VBLANK_INTERRUPT (1 << 16)
304 # define VBLANK_INTERRUPT_TYPE (1 << 17)
306 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
307 #define INT_MASK 0x6b40
308 # define VBLANK_INT_MASK (1 << 0)
309 # define VLINE_INT_MASK (1 << 4)
311 #define DISP_INTERRUPT_STATUS 0x60f4
312 # define LB_D1_VLINE_INTERRUPT (1 << 2)
313 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
314 # define DC_HPD1_INTERRUPT (1 << 17)
315 # define DC_HPD1_RX_INTERRUPT (1 << 18)
316 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
317 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
318 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
319 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
320 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
321 # define LB_D2_VLINE_INTERRUPT (1 << 2)
322 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
323 # define DC_HPD2_INTERRUPT (1 << 17)
324 # define DC_HPD2_RX_INTERRUPT (1 << 18)
325 # define DISP_TIMER_INTERRUPT (1 << 24)
326 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
327 # define LB_D3_VLINE_INTERRUPT (1 << 2)
328 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
329 # define DC_HPD3_INTERRUPT (1 << 17)
330 # define DC_HPD3_RX_INTERRUPT (1 << 18)
331 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
332 # define LB_D4_VLINE_INTERRUPT (1 << 2)
333 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
334 # define DC_HPD4_INTERRUPT (1 << 17)
335 # define DC_HPD4_RX_INTERRUPT (1 << 18)
336 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
337 # define LB_D5_VLINE_INTERRUPT (1 << 2)
338 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
339 # define DC_HPD5_INTERRUPT (1 << 17)
340 # define DC_HPD5_RX_INTERRUPT (1 << 18)
341 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
342 # define LB_D6_VLINE_INTERRUPT (1 << 2)
343 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
344 # define DC_HPD6_INTERRUPT (1 << 17)
345 # define DC_HPD6_RX_INTERRUPT (1 << 18)
347 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
348 #define GRPH_INT_STATUS 0x6858
349 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
350 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
351 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
352 #define GRPH_INT_CONTROL 0x685c
353 # define GRPH_PFLIP_INT_MASK (1 << 0)
354 # define GRPH_PFLIP_INT_TYPE (1 << 8)
356 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
358 #define DC_HPD1_INT_STATUS 0x601c
359 #define DC_HPD2_INT_STATUS 0x6028
360 #define DC_HPD3_INT_STATUS 0x6034
361 #define DC_HPD4_INT_STATUS 0x6040
362 #define DC_HPD5_INT_STATUS 0x604c
363 #define DC_HPD6_INT_STATUS 0x6058
364 # define DC_HPDx_INT_STATUS (1 << 0)
365 # define DC_HPDx_SENSE (1 << 1)
366 # define DC_HPDx_RX_INT_STATUS (1 << 8)
368 #define DC_HPD1_INT_CONTROL 0x6020
369 #define DC_HPD2_INT_CONTROL 0x602c
370 #define DC_HPD3_INT_CONTROL 0x6038
371 #define DC_HPD4_INT_CONTROL 0x6044
372 #define DC_HPD5_INT_CONTROL 0x6050
373 #define DC_HPD6_INT_CONTROL 0x605c
374 # define DC_HPDx_INT_ACK (1 << 0)
375 # define DC_HPDx_INT_POLARITY (1 << 8)
376 # define DC_HPDx_INT_EN (1 << 16)
377 # define DC_HPDx_RX_INT_ACK (1 << 20)
378 # define DC_HPDx_RX_INT_EN (1 << 24)
380 #define DC_HPD1_CONTROL 0x6024
381 #define DC_HPD2_CONTROL 0x6030
382 #define DC_HPD3_CONTROL 0x603c
383 #define DC_HPD4_CONTROL 0x6048
384 #define DC_HPD5_CONTROL 0x6054
385 #define DC_HPD6_CONTROL 0x6060
386 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
387 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
388 # define DC_HPDx_EN (1 << 28)
390 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
391 #define CRTC_STATUS_FRAME_COUNT 0x6e98
393 #define GRBM_CNTL 0x8000
394 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
396 #define GRBM_STATUS2 0x8008
397 #define RLC_RQ_PENDING (1 << 0)
398 #define RLC_BUSY (1 << 8)
399 #define TC_BUSY (1 << 9)
401 #define GRBM_STATUS 0x8010
402 #define CMDFIFO_AVAIL_MASK 0x0000000F
403 #define RING2_RQ_PENDING (1 << 4)
404 #define SRBM_RQ_PENDING (1 << 5)
405 #define RING1_RQ_PENDING (1 << 6)
406 #define CF_RQ_PENDING (1 << 7)
407 #define PF_RQ_PENDING (1 << 8)
408 #define GDS_DMA_RQ_PENDING (1 << 9)
409 #define GRBM_EE_BUSY (1 << 10)
410 #define DB_CLEAN (1 << 12)
411 #define CB_CLEAN (1 << 13)
412 #define TA_BUSY (1 << 14)
413 #define GDS_BUSY (1 << 15)
414 #define VGT_BUSY (1 << 17)
415 #define IA_BUSY_NO_DMA (1 << 18)
416 #define IA_BUSY (1 << 19)
417 #define SX_BUSY (1 << 20)
418 #define SPI_BUSY (1 << 22)
419 #define BCI_BUSY (1 << 23)
420 #define SC_BUSY (1 << 24)
421 #define PA_BUSY (1 << 25)
422 #define DB_BUSY (1 << 26)
423 #define CP_COHERENCY_BUSY (1 << 28)
424 #define CP_BUSY (1 << 29)
425 #define CB_BUSY (1 << 30)
426 #define GUI_ACTIVE (1 << 31)
427 #define GRBM_STATUS_SE0 0x8014
428 #define GRBM_STATUS_SE1 0x8018
429 #define SE_DB_CLEAN (1 << 1)
430 #define SE_CB_CLEAN (1 << 2)
431 #define SE_BCI_BUSY (1 << 22)
432 #define SE_VGT_BUSY (1 << 23)
433 #define SE_PA_BUSY (1 << 24)
434 #define SE_TA_BUSY (1 << 25)
435 #define SE_SX_BUSY (1 << 26)
436 #define SE_SPI_BUSY (1 << 27)
437 #define SE_SC_BUSY (1 << 29)
438 #define SE_DB_BUSY (1 << 30)
439 #define SE_CB_BUSY (1 << 31)
441 #define GRBM_SOFT_RESET 0x8020
442 #define SOFT_RESET_CP (1 << 0)
443 #define SOFT_RESET_CB (1 << 1)
444 #define SOFT_RESET_RLC (1 << 2)
445 #define SOFT_RESET_DB (1 << 3)
446 #define SOFT_RESET_GDS (1 << 4)
447 #define SOFT_RESET_PA (1 << 5)
448 #define SOFT_RESET_SC (1 << 6)
449 #define SOFT_RESET_BCI (1 << 7)
450 #define SOFT_RESET_SPI (1 << 8)
451 #define SOFT_RESET_SX (1 << 10)
452 #define SOFT_RESET_TC (1 << 11)
453 #define SOFT_RESET_TA (1 << 12)
454 #define SOFT_RESET_VGT (1 << 14)
455 #define SOFT_RESET_IA (1 << 15)
457 #define GRBM_GFX_INDEX 0x802C
458 #define INSTANCE_INDEX(x) ((x) << 0)
459 #define SH_INDEX(x) ((x) << 8)
460 #define SE_INDEX(x) ((x) << 16)
461 #define SH_BROADCAST_WRITES (1 << 29)
462 #define INSTANCE_BROADCAST_WRITES (1 << 30)
463 #define SE_BROADCAST_WRITES (1 << 31)
465 #define GRBM_INT_CNTL 0x8060
466 # define RDERR_INT_ENABLE (1 << 0)
467 # define GUI_IDLE_INT_ENABLE (1 << 19)
469 #define CP_STRMOUT_CNTL 0x84FC
470 #define SCRATCH_REG0 0x8500
471 #define SCRATCH_REG1 0x8504
472 #define SCRATCH_REG2 0x8508
473 #define SCRATCH_REG3 0x850C
474 #define SCRATCH_REG4 0x8510
475 #define SCRATCH_REG5 0x8514
476 #define SCRATCH_REG6 0x8518
477 #define SCRATCH_REG7 0x851C
479 #define SCRATCH_UMSK 0x8540
480 #define SCRATCH_ADDR 0x8544
482 #define CP_SEM_WAIT_TIMER 0x85BC
484 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
486 #define CP_ME_CNTL 0x86D8
487 #define CP_CE_HALT (1 << 24)
488 #define CP_PFP_HALT (1 << 26)
489 #define CP_ME_HALT (1 << 28)
491 #define CP_COHER_CNTL2 0x85E8
493 #define CP_RB2_RPTR 0x86f8
494 #define CP_RB1_RPTR 0x86fc
495 #define CP_RB0_RPTR 0x8700
496 #define CP_RB_WPTR_DELAY 0x8704
498 #define CP_QUEUE_THRESHOLDS 0x8760
499 #define ROQ_IB1_START(x) ((x) << 0)
500 #define ROQ_IB2_START(x) ((x) << 8)
501 #define CP_MEQ_THRESHOLDS 0x8764
502 #define MEQ1_START(x) ((x) << 0)
503 #define MEQ2_START(x) ((x) << 8)
505 #define CP_PERFMON_CNTL 0x87FC
507 #define VGT_VTX_VECT_EJECT_REG 0x88B0
509 #define VGT_CACHE_INVALIDATION 0x88C4
510 #define CACHE_INVALIDATION(x) ((x) << 0)
514 #define AUTO_INVLD_EN(x) ((x) << 6)
518 #define ES_AND_GS_AUTO 3
519 #define VGT_ESGS_RING_SIZE 0x88C8
520 #define VGT_GSVS_RING_SIZE 0x88CC
522 #define VGT_GS_VERTEX_REUSE 0x88D4
524 #define VGT_PRIMITIVE_TYPE 0x8958
525 #define VGT_INDEX_TYPE 0x895C
527 #define VGT_NUM_INDICES 0x8970
528 #define VGT_NUM_INSTANCES 0x8974
530 #define VGT_TF_RING_SIZE 0x8988
532 #define VGT_HS_OFFCHIP_PARAM 0x89B0
534 #define VGT_TF_MEMORY_BASE 0x89B8
536 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
537 #define INACTIVE_CUS_MASK 0xFFFF0000
538 #define INACTIVE_CUS_SHIFT 16
539 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
541 #define PA_CL_ENHANCE 0x8A14
542 #define CLIP_VTX_REORDER_ENA (1 << 0)
543 #define NUM_CLIP_SEQ(x) ((x) << 1)
545 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
547 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
549 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
550 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
551 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
553 #define PA_SC_FIFO_SIZE 0x8BCC
554 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
555 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
556 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
557 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
559 #define PA_SC_ENHANCE 0x8BF0
561 #define SQ_CONFIG 0x8C00
563 #define SQC_CACHES 0x8C08
565 #define SX_DEBUG_1 0x9060
567 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
568 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
569 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
570 #define SPI_PS_MAX_WAVE_ID 0x90EC
572 #define SPI_CONFIG_CNTL 0x9100
574 #define SPI_CONFIG_CNTL_1 0x913C
575 #define VTX_DONE_DELAY(x) ((x) << 0)
576 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
578 #define CGTS_TCC_DISABLE 0x9148
579 #define CGTS_USER_TCC_DISABLE 0x914C
580 #define TCC_DISABLE_MASK 0xFFFF0000
581 #define TCC_DISABLE_SHIFT 16
583 #define TA_CNTL_AUX 0x9508
585 #define CC_RB_BACKEND_DISABLE 0x98F4
586 #define BACKEND_DISABLE(x) ((x) << 16)
587 #define GB_ADDR_CONFIG 0x98F8
588 #define NUM_PIPES(x) ((x) << 0)
589 #define NUM_PIPES_MASK 0x00000007
590 #define NUM_PIPES_SHIFT 0
591 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
592 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
593 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
594 #define NUM_SHADER_ENGINES(x) ((x) << 12)
595 #define NUM_SHADER_ENGINES_MASK 0x00003000
596 #define NUM_SHADER_ENGINES_SHIFT 12
597 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
598 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
599 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
600 #define NUM_GPUS(x) ((x) << 20)
601 #define NUM_GPUS_MASK 0x00700000
602 #define NUM_GPUS_SHIFT 20
603 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
604 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
605 #define MULTI_GPU_TILE_SIZE_SHIFT 24
606 #define ROW_SIZE(x) ((x) << 28)
607 #define ROW_SIZE_MASK 0x30000000
608 #define ROW_SIZE_SHIFT 28
610 #define GB_TILE_MODE0 0x9910
611 # define MICRO_TILE_MODE(x) ((x) << 0)
612 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
613 # define ADDR_SURF_THIN_MICRO_TILING 1
614 # define ADDR_SURF_DEPTH_MICRO_TILING 2
615 # define ARRAY_MODE(x) ((x) << 2)
616 # define ARRAY_LINEAR_GENERAL 0
617 # define ARRAY_LINEAR_ALIGNED 1
618 # define ARRAY_1D_TILED_THIN1 2
619 # define ARRAY_2D_TILED_THIN1 4
620 # define PIPE_CONFIG(x) ((x) << 6)
621 # define ADDR_SURF_P2 0
622 # define ADDR_SURF_P4_8x16 4
623 # define ADDR_SURF_P4_16x16 5
624 # define ADDR_SURF_P4_16x32 6
625 # define ADDR_SURF_P4_32x32 7
626 # define ADDR_SURF_P8_16x16_8x16 8
627 # define ADDR_SURF_P8_16x32_8x16 9
628 # define ADDR_SURF_P8_32x32_8x16 10
629 # define ADDR_SURF_P8_16x32_16x16 11
630 # define ADDR_SURF_P8_32x32_16x16 12
631 # define ADDR_SURF_P8_32x32_16x32 13
632 # define ADDR_SURF_P8_32x64_32x32 14
633 # define TILE_SPLIT(x) ((x) << 11)
634 # define ADDR_SURF_TILE_SPLIT_64B 0
635 # define ADDR_SURF_TILE_SPLIT_128B 1
636 # define ADDR_SURF_TILE_SPLIT_256B 2
637 # define ADDR_SURF_TILE_SPLIT_512B 3
638 # define ADDR_SURF_TILE_SPLIT_1KB 4
639 # define ADDR_SURF_TILE_SPLIT_2KB 5
640 # define ADDR_SURF_TILE_SPLIT_4KB 6
641 # define BANK_WIDTH(x) ((x) << 14)
642 # define ADDR_SURF_BANK_WIDTH_1 0
643 # define ADDR_SURF_BANK_WIDTH_2 1
644 # define ADDR_SURF_BANK_WIDTH_4 2
645 # define ADDR_SURF_BANK_WIDTH_8 3
646 # define BANK_HEIGHT(x) ((x) << 16)
647 # define ADDR_SURF_BANK_HEIGHT_1 0
648 # define ADDR_SURF_BANK_HEIGHT_2 1
649 # define ADDR_SURF_BANK_HEIGHT_4 2
650 # define ADDR_SURF_BANK_HEIGHT_8 3
651 # define MACRO_TILE_ASPECT(x) ((x) << 18)
652 # define ADDR_SURF_MACRO_ASPECT_1 0
653 # define ADDR_SURF_MACRO_ASPECT_2 1
654 # define ADDR_SURF_MACRO_ASPECT_4 2
655 # define ADDR_SURF_MACRO_ASPECT_8 3
656 # define NUM_BANKS(x) ((x) << 20)
657 # define ADDR_SURF_2_BANK 0
658 # define ADDR_SURF_4_BANK 1
659 # define ADDR_SURF_8_BANK 2
660 # define ADDR_SURF_16_BANK 3
662 #define CB_PERFCOUNTER0_SELECT0 0x9a20
663 #define CB_PERFCOUNTER0_SELECT1 0x9a24
664 #define CB_PERFCOUNTER1_SELECT0 0x9a28
665 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
666 #define CB_PERFCOUNTER2_SELECT0 0x9a30
667 #define CB_PERFCOUNTER2_SELECT1 0x9a34
668 #define CB_PERFCOUNTER3_SELECT0 0x9a38
669 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
671 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
672 #define BACKEND_DISABLE_MASK 0x00FF0000
673 #define BACKEND_DISABLE_SHIFT 16
675 #define TCP_CHAN_STEER_LO 0xac0c
676 #define TCP_CHAN_STEER_HI 0xac10
678 #define CP_RB0_BASE 0xC100
679 #define CP_RB0_CNTL 0xC104
680 #define RB_BUFSZ(x) ((x) << 0)
681 #define RB_BLKSZ(x) ((x) << 8)
682 #define BUF_SWAP_32BIT (2 << 16)
683 #define RB_NO_UPDATE (1 << 27)
684 #define RB_RPTR_WR_ENA (1 << 31)
686 #define CP_RB0_RPTR_ADDR 0xC10C
687 #define CP_RB0_RPTR_ADDR_HI 0xC110
688 #define CP_RB0_WPTR 0xC114
690 #define CP_PFP_UCODE_ADDR 0xC150
691 #define CP_PFP_UCODE_DATA 0xC154
692 #define CP_ME_RAM_RADDR 0xC158
693 #define CP_ME_RAM_WADDR 0xC15C
694 #define CP_ME_RAM_DATA 0xC160
696 #define CP_CE_UCODE_ADDR 0xC168
697 #define CP_CE_UCODE_DATA 0xC16C
699 #define CP_RB1_BASE 0xC180
700 #define CP_RB1_CNTL 0xC184
701 #define CP_RB1_RPTR_ADDR 0xC188
702 #define CP_RB1_RPTR_ADDR_HI 0xC18C
703 #define CP_RB1_WPTR 0xC190
704 #define CP_RB2_BASE 0xC194
705 #define CP_RB2_CNTL 0xC198
706 #define CP_RB2_RPTR_ADDR 0xC19C
707 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
708 #define CP_RB2_WPTR 0xC1A4
709 #define CP_INT_CNTL_RING0 0xC1A8
710 #define CP_INT_CNTL_RING1 0xC1AC
711 #define CP_INT_CNTL_RING2 0xC1B0
712 # define CNTX_BUSY_INT_ENABLE (1 << 19)
713 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
714 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
715 # define TIME_STAMP_INT_ENABLE (1 << 26)
716 # define CP_RINGID2_INT_ENABLE (1 << 29)
717 # define CP_RINGID1_INT_ENABLE (1 << 30)
718 # define CP_RINGID0_INT_ENABLE (1 << 31)
719 #define CP_INT_STATUS_RING0 0xC1B4
720 #define CP_INT_STATUS_RING1 0xC1B8
721 #define CP_INT_STATUS_RING2 0xC1BC
722 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
723 # define TIME_STAMP_INT_STAT (1 << 26)
724 # define CP_RINGID2_INT_STAT (1 << 29)
725 # define CP_RINGID1_INT_STAT (1 << 30)
726 # define CP_RINGID0_INT_STAT (1 << 31)
728 #define CP_DEBUG 0xC1FC
730 #define RLC_CNTL 0xC300
731 # define RLC_ENABLE (1 << 0)
732 #define RLC_RL_BASE 0xC304
733 #define RLC_RL_SIZE 0xC308
734 #define RLC_LB_CNTL 0xC30C
735 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
736 #define RLC_LB_CNTR_MAX 0xC314
737 #define RLC_LB_CNTR_INIT 0xC318
739 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
741 #define RLC_UCODE_ADDR 0xC32C
742 #define RLC_UCODE_DATA 0xC330
744 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
745 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
746 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
747 #define RLC_MC_CNTL 0xC344
748 #define RLC_UCODE_CNTL 0xC348
750 #define PA_SC_RASTER_CONFIG 0x28350
751 # define RASTER_CONFIG_RB_MAP_0 0
752 # define RASTER_CONFIG_RB_MAP_1 1
753 # define RASTER_CONFIG_RB_MAP_2 2
754 # define RASTER_CONFIG_RB_MAP_3 3
756 #define VGT_EVENT_INITIATOR 0x28a90
757 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
758 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
759 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
760 # define CACHE_FLUSH_TS (4 << 0)
761 # define CACHE_FLUSH (6 << 0)
762 # define CS_PARTIAL_FLUSH (7 << 0)
763 # define VGT_STREAMOUT_RESET (10 << 0)
764 # define END_OF_PIPE_INCR_DE (11 << 0)
765 # define END_OF_PIPE_IB_END (12 << 0)
766 # define RST_PIX_CNT (13 << 0)
767 # define VS_PARTIAL_FLUSH (15 << 0)
768 # define PS_PARTIAL_FLUSH (16 << 0)
769 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
770 # define ZPASS_DONE (21 << 0)
771 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
772 # define PERFCOUNTER_START (23 << 0)
773 # define PERFCOUNTER_STOP (24 << 0)
774 # define PIPELINESTAT_START (25 << 0)
775 # define PIPELINESTAT_STOP (26 << 0)
776 # define PERFCOUNTER_SAMPLE (27 << 0)
777 # define SAMPLE_PIPELINESTAT (30 << 0)
778 # define SAMPLE_STREAMOUTSTATS (32 << 0)
779 # define RESET_VTX_CNT (33 << 0)
780 # define VGT_FLUSH (36 << 0)
781 # define BOTTOM_OF_PIPE_TS (40 << 0)
782 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
783 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
784 # define FLUSH_AND_INV_DB_META (44 << 0)
785 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
786 # define FLUSH_AND_INV_CB_META (46 << 0)
787 # define CS_DONE (47 << 0)
788 # define PS_DONE (48 << 0)
789 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
790 # define THREAD_TRACE_START (51 << 0)
791 # define THREAD_TRACE_STOP (52 << 0)
792 # define THREAD_TRACE_FLUSH (54 << 0)
793 # define THREAD_TRACE_FINISH (55 << 0)
798 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
799 (((reg) >> 2) & 0xFFFF) | \
800 ((n) & 0x3FFF) << 16)
801 #define CP_PACKET2 0x80000000
802 #define PACKET2_PAD_SHIFT 0
803 #define PACKET2_PAD_MASK (0x3fffffff << 0)
805 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
807 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
808 (((op) & 0xFF) << 8) | \
809 ((n) & 0x3FFF) << 16)
811 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
814 #define PACKET3_NOP 0x10
815 #define PACKET3_SET_BASE 0x11
816 #define PACKET3_BASE_INDEX(x) ((x) << 0)
817 #define GDS_PARTITION_BASE 2
818 #define CE_PARTITION_BASE 3
819 #define PACKET3_CLEAR_STATE 0x12
820 #define PACKET3_INDEX_BUFFER_SIZE 0x13
821 #define PACKET3_DISPATCH_DIRECT 0x15
822 #define PACKET3_DISPATCH_INDIRECT 0x16
823 #define PACKET3_ALLOC_GDS 0x1B
824 #define PACKET3_WRITE_GDS_RAM 0x1C
825 #define PACKET3_ATOMIC_GDS 0x1D
826 #define PACKET3_ATOMIC 0x1E
827 #define PACKET3_OCCLUSION_QUERY 0x1F
828 #define PACKET3_SET_PREDICATION 0x20
829 #define PACKET3_REG_RMW 0x21
830 #define PACKET3_COND_EXEC 0x22
831 #define PACKET3_PRED_EXEC 0x23
832 #define PACKET3_DRAW_INDIRECT 0x24
833 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
834 #define PACKET3_INDEX_BASE 0x26
835 #define PACKET3_DRAW_INDEX_2 0x27
836 #define PACKET3_CONTEXT_CONTROL 0x28
837 #define PACKET3_INDEX_TYPE 0x2A
838 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
839 #define PACKET3_DRAW_INDEX_AUTO 0x2D
840 #define PACKET3_DRAW_INDEX_IMMD 0x2E
841 #define PACKET3_NUM_INSTANCES 0x2F
842 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
843 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
844 #define PACKET3_INDIRECT_BUFFER 0x32
845 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
846 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
847 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
848 #define PACKET3_WRITE_DATA 0x37
849 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
851 * 1 - memory (sync - via GRBM)
855 * 5 - memory (async - direct)
857 #define WR_ONE_ADDR (1 << 16)
858 #define WR_CONFIRM (1 << 20)
859 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
864 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
865 #define PACKET3_MEM_SEMAPHORE 0x39
866 #define PACKET3_MPEG_INDEX 0x3A
867 #define PACKET3_COPY_DW 0x3B
868 #define PACKET3_WAIT_REG_MEM 0x3C
869 #define PACKET3_MEM_WRITE 0x3D
870 #define PACKET3_COPY_DATA 0x40
871 #define PACKET3_CP_DMA 0x41
873 * 2. SRC_ADDR_LO or DATA [31:0]
874 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
876 * 4. DST_ADDR_LO [31:0]
877 * 5. DST_ADDR_HI [7:0]
878 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
880 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
884 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
888 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
893 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
895 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
896 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
902 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
908 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
912 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
916 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
917 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
918 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
919 #define PACKET3_PFP_SYNC_ME 0x42
920 #define PACKET3_SURFACE_SYNC 0x43
921 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
922 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
923 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
924 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
925 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
926 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
927 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
928 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
929 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
930 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
931 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
932 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
933 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
934 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
935 # define PACKET3_TC_ACTION_ENA (1 << 23)
936 # define PACKET3_CB_ACTION_ENA (1 << 25)
937 # define PACKET3_DB_ACTION_ENA (1 << 26)
938 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
939 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
940 #define PACKET3_ME_INITIALIZE 0x44
941 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
942 #define PACKET3_COND_WRITE 0x45
943 #define PACKET3_EVENT_WRITE 0x46
944 #define EVENT_TYPE(x) ((x) << 0)
945 #define EVENT_INDEX(x) ((x) << 8)
946 /* 0 - any non-TS event
948 * 2 - SAMPLE_PIPELINESTAT
949 * 3 - SAMPLE_STREAMOUTSTAT*
950 * 4 - *S_PARTIAL_FLUSH
953 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
955 #define INV_L2 (1 << 20)
956 /* INV TC L2 cache when EVENT_INDEX = 7 */
957 #define PACKET3_EVENT_WRITE_EOP 0x47
958 #define DATA_SEL(x) ((x) << 29)
960 * 1 - send low 32bit data
961 * 2 - send 64bit data
962 * 3 - send 64bit counter value
964 #define INT_SEL(x) ((x) << 24)
966 * 1 - interrupt only (DATA_SEL = 0)
967 * 2 - interrupt when data write is confirmed
969 #define PACKET3_EVENT_WRITE_EOS 0x48
970 #define PACKET3_PREAMBLE_CNTL 0x4A
971 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
972 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
973 #define PACKET3_ONE_REG_WRITE 0x57
974 #define PACKET3_LOAD_CONFIG_REG 0x5F
975 #define PACKET3_LOAD_CONTEXT_REG 0x60
976 #define PACKET3_LOAD_SH_REG 0x61
977 #define PACKET3_SET_CONFIG_REG 0x68
978 #define PACKET3_SET_CONFIG_REG_START 0x00008000
979 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
980 #define PACKET3_SET_CONTEXT_REG 0x69
981 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
982 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
983 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
984 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
985 #define PACKET3_SET_SH_REG 0x76
986 #define PACKET3_SET_SH_REG_START 0x0000b000
987 #define PACKET3_SET_SH_REG_END 0x0000c000
988 #define PACKET3_SET_SH_REG_OFFSET 0x77
989 #define PACKET3_ME_WRITE 0x7A
990 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
991 #define PACKET3_SCRATCH_RAM_READ 0x7E
992 #define PACKET3_CE_WRITE 0x7F
993 #define PACKET3_LOAD_CONST_RAM 0x80
994 #define PACKET3_WRITE_CONST_RAM 0x81
995 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
996 #define PACKET3_DUMP_CONST_RAM 0x83
997 #define PACKET3_INCREMENT_CE_COUNTER 0x84
998 #define PACKET3_INCREMENT_DE_COUNTER 0x85
999 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1000 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1001 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1002 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1003 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1004 #define PACKET3_SWITCH_BUFFER 0x8B
1006 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1007 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1008 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1010 #define DMA_RB_CNTL 0xd000
1011 # define DMA_RB_ENABLE (1 << 0)
1012 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1013 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1014 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1015 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1016 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1017 #define DMA_RB_BASE 0xd004
1018 #define DMA_RB_RPTR 0xd008
1019 #define DMA_RB_WPTR 0xd00c
1021 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1022 #define DMA_RB_RPTR_ADDR_LO 0xd020
1024 #define DMA_IB_CNTL 0xd024
1025 # define DMA_IB_ENABLE (1 << 0)
1026 # define DMA_IB_SWAP_ENABLE (1 << 4)
1027 #define DMA_IB_RPTR 0xd028
1028 #define DMA_CNTL 0xd02c
1029 # define TRAP_ENABLE (1 << 0)
1030 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1031 # define SEM_WAIT_INT_ENABLE (1 << 2)
1032 # define DATA_SWAP_ENABLE (1 << 3)
1033 # define FENCE_SWAP_ENABLE (1 << 4)
1034 # define CTXEMPTY_INT_ENABLE (1 << 28)
1035 #define DMA_STATUS_REG 0xd034
1036 # define DMA_IDLE (1 << 0)
1037 #define DMA_TILING_CONFIG 0xd0b8
1039 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1040 (((b) & 0x1) << 26) | \
1041 (((t) & 0x1) << 23) | \
1042 (((s) & 0x1) << 22) | \
1043 (((n) & 0xFFFFF) << 0))
1045 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1046 (((vmid) & 0xF) << 20) | \
1047 (((n) & 0xFFFFF) << 0))
1049 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1052 (((n) & 0xFFFFF) << 0))
1054 /* async DMA Packet types */
1055 #define DMA_PACKET_WRITE 0x2
1056 #define DMA_PACKET_COPY 0x3
1057 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1058 #define DMA_PACKET_SEMAPHORE 0x5
1059 #define DMA_PACKET_FENCE 0x6
1060 #define DMA_PACKET_TRAP 0x7
1061 #define DMA_PACKET_SRBM_WRITE 0x9
1062 #define DMA_PACKET_CONSTANT_FILL 0xd
1063 #define DMA_PACKET_NOP 0xf