2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
38 #define SMC_RAM_END 0x20000
40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
42 static const struct si_cac_config_reg cac_weights_tahiti[] =
44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
107 static const struct si_cac_config_reg lcac_tahiti[] =
109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
199 static const struct si_cac_config_reg cac_override_tahiti[] =
204 static const struct si_powertune_data powertune_data_tahiti =
235 static const struct si_dte_data dte_data_tahiti =
237 { 1159409, 0, 0, 0, 0 },
246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
253 static const struct si_dte_data dte_data_tahiti_le =
255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
271 static const struct si_dte_data dte_data_tahiti_pro =
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
274 { 0x0, 0x0, 0x0, 0x0, 0x0 },
282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
289 static const struct si_dte_data dte_data_new_zealand =
291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
307 static const struct si_dte_data dte_data_aruba_pro =
309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
310 { 0x0, 0x0, 0x0, 0x0, 0x0 },
318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
325 static const struct si_dte_data dte_data_malta =
327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
328 { 0x0, 0x0, 0x0, 0x0, 0x0 },
336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
343 struct si_cac_config_reg cac_weights_pitcairn[] =
345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
408 static const struct si_cac_config_reg lcac_pitcairn[] =
410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
499 static const struct si_cac_config_reg cac_override_pitcairn[] =
504 static const struct si_powertune_data powertune_data_pitcairn =
535 static const struct si_dte_data dte_data_pitcairn =
546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
553 static const struct si_dte_data dte_data_curacao_xt =
555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
556 { 0x0, 0x0, 0x0, 0x0, 0x0 },
564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
571 static const struct si_dte_data dte_data_curacao_pro =
573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
574 { 0x0, 0x0, 0x0, 0x0, 0x0 },
582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
589 static const struct si_dte_data dte_data_neptune_xt =
591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
592 { 0x0, 0x0, 0x0, 0x0, 0x0 },
600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
737 static const struct si_cac_config_reg cac_weights_heathrow[] =
739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
932 static const struct si_cac_config_reg lcac_cape_verde[] =
934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
991 static const struct si_cac_config_reg cac_override_cape_verde[] =
996 static const struct si_powertune_data powertune_data_cape_verde =
998 ((1 << 16) | 0x6993),
1027 static const struct si_dte_data dte_data_cape_verde =
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1045 static const struct si_dte_data dte_data_venus_xtx =
1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1063 static const struct si_dte_data dte_data_venus_xt =
1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1081 static const struct si_dte_data dte_data_venus_pro =
1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1099 struct si_cac_config_reg cac_weights_oland[] =
1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1424 static const struct si_cac_config_reg lcac_oland[] =
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518 static const struct si_cac_config_reg cac_override_oland[] =
1523 static const struct si_powertune_data powertune_data_oland =
1525 ((1 << 16) | 0x6993),
1554 static const struct si_powertune_data powertune_data_mars_pro =
1556 ((1 << 16) | 0x6993),
1585 static const struct si_dte_data dte_data_oland =
1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1603 static const struct si_dte_data dte_data_mars_pro =
1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1621 static const struct si_dte_data dte_data_sun_xt =
1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1705 static const struct si_powertune_data powertune_data_hainan =
1707 ((1 << 16) | 0x6993),
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741 static int si_populate_voltage_value(struct radeon_device *rdev,
1742 const struct atom_voltage_table *table,
1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1744 static int si_get_std_voltage_value(struct radeon_device *rdev,
1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1747 static int si_write_smc_soft_register(struct radeon_device *rdev,
1748 u16 reg_offset, u32 value);
1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1750 struct rv7xx_pl *pl,
1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1752 static int si_calculate_sclk_params(struct radeon_device *rdev,
1754 SISLANDS_SMC_SCLK_VALUE *sclk);
1756 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1758 struct si_power_info *pi = rdev->pm.dpm.priv;
1763 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1764 u16 v, s32 t, u32 ileakage, u32 *leakage)
1766 s64 kt, kv, leakage_w, i_leakage, vddc;
1767 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1771 vddc = div64_s64(drm_int2fixp(v), 1000);
1772 temperature = div64_s64(drm_int2fixp(t), 1000);
1774 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1775 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1776 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1777 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1778 t_ref = drm_int2fixp(coeff->t_ref);
1780 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1781 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1782 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1783 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1785 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1787 *leakage = drm_fixp2int(leakage_w * 1000);
1790 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1791 const struct ni_leakage_coeffients *coeff,
1797 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1800 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1801 const u32 fixed_kt, u16 v,
1802 u32 ileakage, u32 *leakage)
1804 s64 kt, kv, leakage_w, i_leakage, vddc;
1806 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1807 vddc = div64_s64(drm_int2fixp(v), 1000);
1809 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1810 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1811 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1813 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1815 *leakage = drm_fixp2int(leakage_w * 1000);
1818 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1819 const struct ni_leakage_coeffients *coeff,
1825 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1829 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1830 struct si_dte_data *dte_data)
1832 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1833 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1834 u32 k = dte_data->k;
1835 u32 t_max = dte_data->max_t;
1836 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1837 u32 t_0 = dte_data->t0;
1840 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1841 dte_data->tdep_count = 3;
1843 for (i = 0; i < k; i++) {
1845 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1846 (p_limit2 * (u32)100);
1849 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1851 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1852 dte_data->tdep_r[i] = dte_data->r[4];
1855 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1859 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1861 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1862 struct si_power_info *si_pi = si_get_pi(rdev);
1863 bool update_dte_from_pl2 = false;
1865 if (rdev->family == CHIP_TAHITI) {
1866 si_pi->cac_weights = cac_weights_tahiti;
1867 si_pi->lcac_config = lcac_tahiti;
1868 si_pi->cac_override = cac_override_tahiti;
1869 si_pi->powertune_data = &powertune_data_tahiti;
1870 si_pi->dte_data = dte_data_tahiti;
1872 switch (rdev->pdev->device) {
1874 si_pi->dte_data.enable_dte_by_default = true;
1877 si_pi->dte_data = dte_data_new_zealand;
1883 si_pi->dte_data = dte_data_aruba_pro;
1884 update_dte_from_pl2 = true;
1887 si_pi->dte_data = dte_data_malta;
1888 update_dte_from_pl2 = true;
1891 si_pi->dte_data = dte_data_tahiti_pro;
1892 update_dte_from_pl2 = true;
1895 if (si_pi->dte_data.enable_dte_by_default == true)
1896 DRM_ERROR("DTE is not enabled!\n");
1899 } else if (rdev->family == CHIP_PITCAIRN) {
1900 switch (rdev->pdev->device) {
1903 si_pi->cac_weights = cac_weights_pitcairn;
1904 si_pi->lcac_config = lcac_pitcairn;
1905 si_pi->cac_override = cac_override_pitcairn;
1906 si_pi->powertune_data = &powertune_data_pitcairn;
1907 si_pi->dte_data = dte_data_curacao_xt;
1908 update_dte_from_pl2 = true;
1912 si_pi->cac_weights = cac_weights_pitcairn;
1913 si_pi->lcac_config = lcac_pitcairn;
1914 si_pi->cac_override = cac_override_pitcairn;
1915 si_pi->powertune_data = &powertune_data_pitcairn;
1916 si_pi->dte_data = dte_data_curacao_pro;
1917 update_dte_from_pl2 = true;
1921 si_pi->cac_weights = cac_weights_pitcairn;
1922 si_pi->lcac_config = lcac_pitcairn;
1923 si_pi->cac_override = cac_override_pitcairn;
1924 si_pi->powertune_data = &powertune_data_pitcairn;
1925 si_pi->dte_data = dte_data_neptune_xt;
1926 update_dte_from_pl2 = true;
1929 si_pi->cac_weights = cac_weights_pitcairn;
1930 si_pi->lcac_config = lcac_pitcairn;
1931 si_pi->cac_override = cac_override_pitcairn;
1932 si_pi->powertune_data = &powertune_data_pitcairn;
1933 si_pi->dte_data = dte_data_pitcairn;
1936 } else if (rdev->family == CHIP_VERDE) {
1937 si_pi->lcac_config = lcac_cape_verde;
1938 si_pi->cac_override = cac_override_cape_verde;
1939 si_pi->powertune_data = &powertune_data_cape_verde;
1941 switch (rdev->pdev->device) {
1946 si_pi->cac_weights = cac_weights_cape_verde_pro;
1947 si_pi->dte_data = dte_data_cape_verde;
1951 si_pi->cac_weights = cac_weights_heathrow;
1952 si_pi->dte_data = dte_data_cape_verde;
1956 si_pi->cac_weights = cac_weights_chelsea_xt;
1957 si_pi->dte_data = dte_data_cape_verde;
1960 si_pi->cac_weights = cac_weights_chelsea_pro;
1961 si_pi->dte_data = dte_data_cape_verde;
1964 si_pi->cac_weights = cac_weights_heathrow;
1965 si_pi->dte_data = dte_data_venus_xtx;
1968 si_pi->cac_weights = cac_weights_heathrow;
1969 si_pi->dte_data = dte_data_venus_xt;
1972 si_pi->cac_weights = cac_weights_chelsea_pro;
1973 si_pi->dte_data = dte_data_venus_pro;
1976 si_pi->cac_weights = cac_weights_chelsea_pro;
1977 si_pi->dte_data = dte_data_venus_pro;
1980 si_pi->cac_weights = cac_weights_cape_verde;
1981 si_pi->dte_data = dte_data_cape_verde;
1984 } else if (rdev->family == CHIP_OLAND) {
1985 switch (rdev->pdev->device) {
1989 si_pi->cac_weights = cac_weights_mars_pro;
1990 si_pi->lcac_config = lcac_mars_pro;
1991 si_pi->cac_override = cac_override_oland;
1992 si_pi->powertune_data = &powertune_data_mars_pro;
1993 si_pi->dte_data = dte_data_mars_pro;
1994 update_dte_from_pl2 = true;
1999 si_pi->cac_weights = cac_weights_mars_xt;
2000 si_pi->lcac_config = lcac_mars_pro;
2001 si_pi->cac_override = cac_override_oland;
2002 si_pi->powertune_data = &powertune_data_mars_pro;
2003 si_pi->dte_data = dte_data_mars_pro;
2004 update_dte_from_pl2 = true;
2007 si_pi->cac_weights = cac_weights_oland_pro;
2008 si_pi->lcac_config = lcac_mars_pro;
2009 si_pi->cac_override = cac_override_oland;
2010 si_pi->powertune_data = &powertune_data_mars_pro;
2011 si_pi->dte_data = dte_data_mars_pro;
2012 update_dte_from_pl2 = true;
2015 si_pi->cac_weights = cac_weights_oland_xt;
2016 si_pi->lcac_config = lcac_mars_pro;
2017 si_pi->cac_override = cac_override_oland;
2018 si_pi->powertune_data = &powertune_data_mars_pro;
2019 si_pi->dte_data = dte_data_mars_pro;
2020 update_dte_from_pl2 = true;
2023 si_pi->cac_weights = cac_weights_oland;
2024 si_pi->lcac_config = lcac_oland;
2025 si_pi->cac_override = cac_override_oland;
2026 si_pi->powertune_data = &powertune_data_oland;
2027 si_pi->dte_data = dte_data_oland;
2030 } else if (rdev->family == CHIP_HAINAN) {
2031 si_pi->cac_weights = cac_weights_hainan;
2032 si_pi->lcac_config = lcac_oland;
2033 si_pi->cac_override = cac_override_oland;
2034 si_pi->powertune_data = &powertune_data_hainan;
2035 si_pi->dte_data = dte_data_sun_xt;
2036 update_dte_from_pl2 = true;
2038 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2042 ni_pi->enable_power_containment = false;
2043 ni_pi->enable_cac = false;
2044 ni_pi->enable_sq_ramping = false;
2045 si_pi->enable_dte = false;
2047 if (si_pi->powertune_data->enable_powertune_by_default) {
2048 ni_pi->enable_power_containment= true;
2049 ni_pi->enable_cac = true;
2050 if (si_pi->dte_data.enable_dte_by_default) {
2051 si_pi->enable_dte = true;
2052 if (update_dte_from_pl2)
2053 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2056 ni_pi->enable_sq_ramping = true;
2059 ni_pi->driver_calculate_cac_leakage = true;
2060 ni_pi->cac_configuration_required = true;
2062 if (ni_pi->cac_configuration_required) {
2063 ni_pi->support_cac_long_term_average = true;
2064 si_pi->dyn_powertune_data.l2_lta_window_size =
2065 si_pi->powertune_data->l2_lta_window_size_default;
2066 si_pi->dyn_powertune_data.lts_truncate =
2067 si_pi->powertune_data->lts_truncate_default;
2069 ni_pi->support_cac_long_term_average = false;
2070 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2071 si_pi->dyn_powertune_data.lts_truncate = 0;
2074 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2077 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2082 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2087 u32 cac_window_size;
2089 xclk = radeon_get_xclk(rdev);
2094 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2095 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2097 wintime = (cac_window_size * 100) / xclk;
2102 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2104 return power_in_watts;
2107 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2108 bool adjust_polarity,
2111 u32 *near_tdp_limit)
2113 u32 adjustment_delta, max_tdp_limit;
2115 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2118 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2120 if (adjust_polarity) {
2121 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2122 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2124 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2125 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2126 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2127 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2129 *near_tdp_limit = 0;
2132 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2134 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2140 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2141 struct radeon_ps *radeon_state)
2143 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2144 struct si_power_info *si_pi = si_get_pi(rdev);
2146 if (ni_pi->enable_power_containment) {
2147 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2148 PP_SIslands_PAPMParameters *papm_parm;
2149 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2150 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2155 if (scaling_factor == 0)
2158 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2160 ret = si_calculate_adjusted_tdp_limits(rdev,
2162 rdev->pm.dpm.tdp_adjustment,
2168 smc_table->dpm2Params.TDPLimit =
2169 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2170 smc_table->dpm2Params.NearTDPLimit =
2171 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2172 smc_table->dpm2Params.SafePowerLimit =
2173 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2175 ret = si_copy_bytes_to_smc(rdev,
2176 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2177 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2178 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2184 if (si_pi->enable_ppm) {
2185 papm_parm = &si_pi->papm_parm;
2186 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2187 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2188 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2189 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2190 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2191 papm_parm->PlatformPowerLimit = 0xffffffff;
2192 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2194 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2196 sizeof(PP_SIslands_PAPMParameters),
2205 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2206 struct radeon_ps *radeon_state)
2208 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2209 struct si_power_info *si_pi = si_get_pi(rdev);
2211 if (ni_pi->enable_power_containment) {
2212 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2213 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2216 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2218 smc_table->dpm2Params.NearTDPLimit =
2219 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2220 smc_table->dpm2Params.SafePowerLimit =
2221 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2223 ret = si_copy_bytes_to_smc(rdev,
2224 (si_pi->state_table_start +
2225 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2226 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2227 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2237 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2238 const u16 prev_std_vddc,
2239 const u16 curr_std_vddc)
2241 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2242 u64 prev_vddc = (u64)prev_std_vddc;
2243 u64 curr_vddc = (u64)curr_std_vddc;
2244 u64 pwr_efficiency_ratio, n, d;
2246 if ((prev_vddc == 0) || (curr_vddc == 0))
2249 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2250 d = prev_vddc * prev_vddc;
2251 pwr_efficiency_ratio = div64_u64(n, d);
2253 if (pwr_efficiency_ratio > (u64)0xFFFF)
2256 return (u16)pwr_efficiency_ratio;
2259 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2260 struct radeon_ps *radeon_state)
2262 struct si_power_info *si_pi = si_get_pi(rdev);
2264 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2265 radeon_state->vclk && radeon_state->dclk)
2271 static int si_populate_power_containment_values(struct radeon_device *rdev,
2272 struct radeon_ps *radeon_state,
2273 SISLANDS_SMC_SWSTATE *smc_state)
2275 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2276 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2277 struct ni_ps *state = ni_get_ps(radeon_state);
2278 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2285 u16 pwr_efficiency_ratio;
2287 bool disable_uvd_power_tune;
2290 if (ni_pi->enable_power_containment == false)
2293 if (state->performance_level_count == 0)
2296 if (smc_state->levelCount != state->performance_level_count)
2299 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2301 smc_state->levels[0].dpm2.MaxPS = 0;
2302 smc_state->levels[0].dpm2.NearTDPDec = 0;
2303 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2304 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2305 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2307 for (i = 1; i < state->performance_level_count; i++) {
2308 prev_sclk = state->performance_levels[i-1].sclk;
2309 max_sclk = state->performance_levels[i].sclk;
2311 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2313 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2315 if (prev_sclk > max_sclk)
2318 if ((max_ps_percent == 0) ||
2319 (prev_sclk == max_sclk) ||
2320 disable_uvd_power_tune) {
2321 min_sclk = max_sclk;
2322 } else if (i == 1) {
2323 min_sclk = prev_sclk;
2325 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2328 if (min_sclk < state->performance_levels[0].sclk)
2329 min_sclk = state->performance_levels[0].sclk;
2334 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2335 state->performance_levels[i-1].vddc, &vddc);
2339 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2343 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2344 state->performance_levels[i].vddc, &vddc);
2348 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2352 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2353 prev_std_vddc, curr_std_vddc);
2355 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2356 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2357 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2358 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2359 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2365 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2366 struct radeon_ps *radeon_state,
2367 SISLANDS_SMC_SWSTATE *smc_state)
2369 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2370 struct ni_ps *state = ni_get_ps(radeon_state);
2371 u32 sq_power_throttle, sq_power_throttle2;
2372 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2375 if (state->performance_level_count == 0)
2378 if (smc_state->levelCount != state->performance_level_count)
2381 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2384 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2385 enable_sq_ramping = false;
2387 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2388 enable_sq_ramping = false;
2390 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2391 enable_sq_ramping = false;
2393 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2394 enable_sq_ramping = false;
2396 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2397 enable_sq_ramping = false;
2399 for (i = 0; i < state->performance_level_count; i++) {
2400 sq_power_throttle = 0;
2401 sq_power_throttle2 = 0;
2403 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2404 enable_sq_ramping) {
2405 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2406 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2407 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2408 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2409 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2411 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2412 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2415 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2416 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2422 static int si_enable_power_containment(struct radeon_device *rdev,
2423 struct radeon_ps *radeon_new_state,
2426 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2427 PPSMC_Result smc_result;
2430 if (ni_pi->enable_power_containment) {
2432 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2433 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2434 if (smc_result != PPSMC_Result_OK) {
2436 ni_pi->pc_enabled = false;
2438 ni_pi->pc_enabled = true;
2442 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2443 if (smc_result != PPSMC_Result_OK)
2445 ni_pi->pc_enabled = false;
2452 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2454 struct si_power_info *si_pi = si_get_pi(rdev);
2456 struct si_dte_data *dte_data = &si_pi->dte_data;
2457 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2462 if (dte_data == NULL)
2463 si_pi->enable_dte = false;
2465 if (si_pi->enable_dte == false)
2468 if (dte_data->k <= 0)
2471 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2472 if (dte_tables == NULL) {
2473 si_pi->enable_dte = false;
2477 table_size = dte_data->k;
2479 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2480 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2482 tdep_count = dte_data->tdep_count;
2483 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2484 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2486 dte_tables->K = cpu_to_be32(table_size);
2487 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2488 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2489 dte_tables->WindowSize = dte_data->window_size;
2490 dte_tables->temp_select = dte_data->temp_select;
2491 dte_tables->DTE_mode = dte_data->dte_mode;
2492 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2497 for (i = 0; i < table_size; i++) {
2498 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2499 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2502 dte_tables->Tdep_count = tdep_count;
2504 for (i = 0; i < (u32)tdep_count; i++) {
2505 dte_tables->T_limits[i] = dte_data->t_limits[i];
2506 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2507 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2510 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2511 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2517 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2520 struct si_power_info *si_pi = si_get_pi(rdev);
2521 struct radeon_cac_leakage_table *table =
2522 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2533 for (i = 0; i < table->count; i++) {
2534 if (table->entries[i].vddc > *max)
2535 *max = table->entries[i].vddc;
2536 if (table->entries[i].vddc < *min)
2537 *min = table->entries[i].vddc;
2540 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2543 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2545 if (v0_loadline > 0xFFFFUL)
2548 *min = (u16)v0_loadline;
2550 if ((*min > *max) || (*max == 0) || (*min == 0))
2556 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2558 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2559 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2562 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2563 PP_SIslands_CacConfig *cac_tables,
2564 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2567 struct si_power_info *si_pi = si_get_pi(rdev);
2575 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2577 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2578 t = (1000 * (i * t_step + t0));
2580 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2581 voltage = vddc_max - (vddc_step * j);
2583 si_calculate_leakage_for_v_and_t(rdev,
2584 &si_pi->powertune_data->leakage_coefficients,
2587 si_pi->dyn_powertune_data.cac_leakage,
2590 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2592 if (smc_leakage > 0xFFFF)
2593 smc_leakage = 0xFFFF;
2595 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2596 cpu_to_be16((u16)smc_leakage);
2602 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2603 PP_SIslands_CacConfig *cac_tables,
2604 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2606 struct si_power_info *si_pi = si_get_pi(rdev);
2613 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2615 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2616 voltage = vddc_max - (vddc_step * j);
2618 si_calculate_leakage_for_v(rdev,
2619 &si_pi->powertune_data->leakage_coefficients,
2620 si_pi->powertune_data->fixed_kt,
2622 si_pi->dyn_powertune_data.cac_leakage,
2625 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2627 if (smc_leakage > 0xFFFF)
2628 smc_leakage = 0xFFFF;
2630 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2631 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2632 cpu_to_be16((u16)smc_leakage);
2637 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2639 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2640 struct si_power_info *si_pi = si_get_pi(rdev);
2641 PP_SIslands_CacConfig *cac_tables = NULL;
2642 u16 vddc_max, vddc_min, vddc_step;
2644 u32 load_line_slope, reg;
2646 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2648 if (ni_pi->enable_cac == false)
2651 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2655 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2656 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2657 WREG32(CG_CAC_CTRL, reg);
2659 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2660 si_pi->dyn_powertune_data.dc_pwr_value =
2661 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2662 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2663 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2665 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2667 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2671 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2672 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2676 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2677 ret = si_init_dte_leakage_table(rdev, cac_tables,
2678 vddc_max, vddc_min, vddc_step,
2681 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2682 vddc_max, vddc_min, vddc_step);
2686 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2688 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2689 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2690 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2691 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2692 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2693 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2694 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2695 cac_tables->calculation_repeats = cpu_to_be32(2);
2696 cac_tables->dc_cac = cpu_to_be32(0);
2697 cac_tables->log2_PG_LKG_SCALE = 12;
2698 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2699 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2700 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2702 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2703 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2708 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2712 ni_pi->enable_cac = false;
2713 ni_pi->enable_power_containment = false;
2721 static int si_program_cac_config_registers(struct radeon_device *rdev,
2722 const struct si_cac_config_reg *cac_config_regs)
2724 const struct si_cac_config_reg *config_regs = cac_config_regs;
2725 u32 data = 0, offset;
2730 while (config_regs->offset != 0xFFFFFFFF) {
2731 switch (config_regs->type) {
2732 case SISLANDS_CACCONFIG_CGIND:
2733 offset = SMC_CG_IND_START + config_regs->offset;
2734 if (offset < SMC_CG_IND_END)
2735 data = RREG32_SMC(offset);
2738 data = RREG32(config_regs->offset << 2);
2742 data &= ~config_regs->mask;
2743 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 WREG32_SMC(offset, data);
2752 WREG32(config_regs->offset << 2, data);
2760 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2762 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2763 struct si_power_info *si_pi = si_get_pi(rdev);
2766 if ((ni_pi->enable_cac == false) ||
2767 (ni_pi->cac_configuration_required == false))
2770 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2773 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2776 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2783 static int si_enable_smc_cac(struct radeon_device *rdev,
2784 struct radeon_ps *radeon_new_state,
2787 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2788 struct si_power_info *si_pi = si_get_pi(rdev);
2789 PPSMC_Result smc_result;
2792 if (ni_pi->enable_cac) {
2794 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2795 if (ni_pi->support_cac_long_term_average) {
2796 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2797 if (smc_result != PPSMC_Result_OK)
2798 ni_pi->support_cac_long_term_average = false;
2801 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2802 if (smc_result != PPSMC_Result_OK) {
2804 ni_pi->cac_enabled = false;
2806 ni_pi->cac_enabled = true;
2809 if (si_pi->enable_dte) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2811 if (smc_result != PPSMC_Result_OK)
2815 } else if (ni_pi->cac_enabled) {
2816 if (si_pi->enable_dte)
2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2821 ni_pi->cac_enabled = false;
2823 if (ni_pi->support_cac_long_term_average)
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2830 static int si_init_smc_spll_table(struct radeon_device *rdev)
2832 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2833 struct si_power_info *si_pi = si_get_pi(rdev);
2834 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2835 SISLANDS_SMC_SCLK_VALUE sclk_params;
2843 if (si_pi->spll_table_start == 0)
2846 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2847 if (spll_table == NULL)
2850 for (i = 0; i < 256; i++) {
2851 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2855 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2856 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2857 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2858 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2860 fb_div &= ~0x00001FFF;
2864 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2866 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2868 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2870 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2876 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2877 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2878 spll_table->freq[i] = cpu_to_be32(tmp);
2880 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2881 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2882 spll_table->ss[i] = cpu_to_be32(tmp);
2889 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2890 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2894 ni_pi->enable_power_containment = false;
2901 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2902 struct radeon_ps *rps)
2904 struct ni_ps *ps = ni_get_ps(rps);
2905 struct radeon_clock_and_voltage_limits *max_limits;
2906 bool disable_mclk_switching = false;
2907 bool disable_sclk_switching = false;
2910 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2913 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2914 ni_dpm_vblank_too_short(rdev))
2915 disable_mclk_switching = true;
2917 if (rps->vclk || rps->dclk) {
2918 disable_mclk_switching = true;
2919 disable_sclk_switching = true;
2922 if (rdev->pm.dpm.ac_power)
2923 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2927 for (i = ps->performance_level_count - 2; i >= 0; i--) {
2928 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2929 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2931 if (rdev->pm.dpm.ac_power == false) {
2932 for (i = 0; i < ps->performance_level_count; i++) {
2933 if (ps->performance_levels[i].mclk > max_limits->mclk)
2934 ps->performance_levels[i].mclk = max_limits->mclk;
2935 if (ps->performance_levels[i].sclk > max_limits->sclk)
2936 ps->performance_levels[i].sclk = max_limits->sclk;
2937 if (ps->performance_levels[i].vddc > max_limits->vddc)
2938 ps->performance_levels[i].vddc = max_limits->vddc;
2939 if (ps->performance_levels[i].vddci > max_limits->vddci)
2940 ps->performance_levels[i].vddci = max_limits->vddci;
2944 /* limit clocks to max supported clocks based on voltage dependency tables */
2945 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2947 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2949 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2952 for (i = 0; i < ps->performance_level_count; i++) {
2953 if (max_sclk_vddc) {
2954 if (ps->performance_levels[i].sclk > max_sclk_vddc)
2955 ps->performance_levels[i].sclk = max_sclk_vddc;
2957 if (max_mclk_vddci) {
2958 if (ps->performance_levels[i].mclk > max_mclk_vddci)
2959 ps->performance_levels[i].mclk = max_mclk_vddci;
2961 if (max_mclk_vddc) {
2962 if (ps->performance_levels[i].mclk > max_mclk_vddc)
2963 ps->performance_levels[i].mclk = max_mclk_vddc;
2967 /* XXX validate the min clocks required for display */
2969 if (disable_mclk_switching) {
2970 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
2971 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2973 mclk = ps->performance_levels[0].mclk;
2974 vddci = ps->performance_levels[0].vddci;
2977 if (disable_sclk_switching) {
2978 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
2979 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
2981 sclk = ps->performance_levels[0].sclk;
2982 vddc = ps->performance_levels[0].vddc;
2985 /* adjusted low state */
2986 ps->performance_levels[0].sclk = sclk;
2987 ps->performance_levels[0].mclk = mclk;
2988 ps->performance_levels[0].vddc = vddc;
2989 ps->performance_levels[0].vddci = vddci;
2991 if (disable_sclk_switching) {
2992 sclk = ps->performance_levels[0].sclk;
2993 for (i = 1; i < ps->performance_level_count; i++) {
2994 if (sclk < ps->performance_levels[i].sclk)
2995 sclk = ps->performance_levels[i].sclk;
2997 for (i = 0; i < ps->performance_level_count; i++) {
2998 ps->performance_levels[i].sclk = sclk;
2999 ps->performance_levels[i].vddc = vddc;
3002 for (i = 1; i < ps->performance_level_count; i++) {
3003 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3004 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3005 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3006 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3010 if (disable_mclk_switching) {
3011 mclk = ps->performance_levels[0].mclk;
3012 for (i = 1; i < ps->performance_level_count; i++) {
3013 if (mclk < ps->performance_levels[i].mclk)
3014 mclk = ps->performance_levels[i].mclk;
3016 for (i = 0; i < ps->performance_level_count; i++) {
3017 ps->performance_levels[i].mclk = mclk;
3018 ps->performance_levels[i].vddci = vddci;
3021 for (i = 1; i < ps->performance_level_count; i++) {
3022 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3023 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3024 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3025 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3029 for (i = 0; i < ps->performance_level_count; i++)
3030 btc_adjust_clock_combinations(rdev, max_limits,
3031 &ps->performance_levels[i]);
3033 for (i = 0; i < ps->performance_level_count; i++) {
3034 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3035 ps->performance_levels[i].sclk,
3036 max_limits->vddc, &ps->performance_levels[i].vddc);
3037 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3038 ps->performance_levels[i].mclk,
3039 max_limits->vddci, &ps->performance_levels[i].vddci);
3040 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3041 ps->performance_levels[i].mclk,
3042 max_limits->vddc, &ps->performance_levels[i].vddc);
3043 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3044 rdev->clock.current_dispclk,
3045 max_limits->vddc, &ps->performance_levels[i].vddc);
3048 for (i = 0; i < ps->performance_level_count; i++) {
3049 btc_apply_voltage_delta_rules(rdev,
3050 max_limits->vddc, max_limits->vddci,
3051 &ps->performance_levels[i].vddc,
3052 &ps->performance_levels[i].vddci);
3055 ps->dc_compatible = true;
3056 for (i = 0; i < ps->performance_level_count; i++) {
3057 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3058 ps->dc_compatible = false;
3064 static int si_read_smc_soft_register(struct radeon_device *rdev,
3065 u16 reg_offset, u32 *value)
3067 struct si_power_info *si_pi = si_get_pi(rdev);
3069 return si_read_smc_sram_dword(rdev,
3070 si_pi->soft_regs_start + reg_offset, value,
3075 static int si_write_smc_soft_register(struct radeon_device *rdev,
3076 u16 reg_offset, u32 value)
3078 struct si_power_info *si_pi = si_get_pi(rdev);
3080 return si_write_smc_sram_dword(rdev,
3081 si_pi->soft_regs_start + reg_offset,
3082 value, si_pi->sram_end);
3085 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3088 u32 tmp, width, row, column, bank, density;
3089 bool is_memory_gddr5, is_special;
3091 tmp = RREG32(MC_SEQ_MISC0);
3092 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3093 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3094 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3096 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3097 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3099 tmp = RREG32(MC_ARB_RAMCFG);
3100 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3101 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3102 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3104 density = (1 << (row + column - 20 + bank)) * width;
3106 if ((rdev->pdev->device == 0x6819) &&
3107 is_memory_gddr5 && is_special && (density == 0x400))
3113 static void si_get_leakage_vddc(struct radeon_device *rdev)
3115 struct si_power_info *si_pi = si_get_pi(rdev);
3116 u16 vddc, count = 0;
3119 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3120 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3122 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3123 si_pi->leakage_voltage.entries[count].voltage = vddc;
3124 si_pi->leakage_voltage.entries[count].leakage_index =
3125 SISLANDS_LEAKAGE_INDEX0 + i;
3129 si_pi->leakage_voltage.count = count;
3132 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3133 u32 index, u16 *leakage_voltage)
3135 struct si_power_info *si_pi = si_get_pi(rdev);
3138 if (leakage_voltage == NULL)
3141 if ((index & 0xff00) != 0xff00)
3144 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3147 if (index < SISLANDS_LEAKAGE_INDEX0)
3150 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3151 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3152 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3159 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3161 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3162 bool want_thermal_protection;
3163 enum radeon_dpm_event_src dpm_event_src;
3168 want_thermal_protection = false;
3170 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3171 want_thermal_protection = true;
3172 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3174 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3175 want_thermal_protection = true;
3176 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3178 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3179 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3180 want_thermal_protection = true;
3181 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3185 if (want_thermal_protection) {
3186 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3187 if (pi->thermal_protection)
3188 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3190 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3194 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3195 enum radeon_dpm_auto_throttle_src source,
3198 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3201 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3202 pi->active_auto_throttle_sources |= 1 << source;
3203 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3206 if (pi->active_auto_throttle_sources & (1 << source)) {
3207 pi->active_auto_throttle_sources &= ~(1 << source);
3208 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3213 static void si_start_dpm(struct radeon_device *rdev)
3215 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3218 static void si_stop_dpm(struct radeon_device *rdev)
3220 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3223 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3226 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3228 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3233 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3238 if (thermal_level == 0) {
3239 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3240 if (ret == PPSMC_Result_OK)
3248 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3250 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3255 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3258 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3265 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3266 PPSMC_Msg msg, u32 parameter)
3268 WREG32(SMC_SCRATCH0, parameter);
3269 return si_send_msg_to_smc(rdev, msg);
3272 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3274 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3277 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3281 int si_dpm_force_performance_level(struct radeon_device *rdev,
3282 enum radeon_dpm_forced_level level)
3284 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3285 struct ni_ps *ps = ni_get_ps(rps);
3286 u32 levels = ps->performance_level_count;
3288 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3289 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3292 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3294 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3295 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3298 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3300 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3301 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3304 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3308 rdev->pm.dpm.forced_level = level;
3313 static int si_set_boot_state(struct radeon_device *rdev)
3315 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3319 static int si_set_sw_state(struct radeon_device *rdev)
3321 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3325 static int si_halt_smc(struct radeon_device *rdev)
3327 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3330 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3334 static int si_resume_smc(struct radeon_device *rdev)
3336 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3339 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3343 static void si_dpm_start_smc(struct radeon_device *rdev)
3345 si_program_jump_on_start(rdev);
3347 si_start_smc_clock(rdev);
3350 static void si_dpm_stop_smc(struct radeon_device *rdev)
3353 si_stop_smc_clock(rdev);
3356 static int si_process_firmware_header(struct radeon_device *rdev)
3358 struct si_power_info *si_pi = si_get_pi(rdev);
3362 ret = si_read_smc_sram_dword(rdev,
3363 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3364 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3365 &tmp, si_pi->sram_end);
3369 si_pi->state_table_start = tmp;
3371 ret = si_read_smc_sram_dword(rdev,
3372 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3373 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3374 &tmp, si_pi->sram_end);
3378 si_pi->soft_regs_start = tmp;
3380 ret = si_read_smc_sram_dword(rdev,
3381 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3382 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3383 &tmp, si_pi->sram_end);
3387 si_pi->mc_reg_table_start = tmp;
3389 ret = si_read_smc_sram_dword(rdev,
3390 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3391 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3392 &tmp, si_pi->sram_end);
3396 si_pi->arb_table_start = tmp;
3398 ret = si_read_smc_sram_dword(rdev,
3399 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3400 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3401 &tmp, si_pi->sram_end);
3405 si_pi->cac_table_start = tmp;
3407 ret = si_read_smc_sram_dword(rdev,
3408 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3409 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3410 &tmp, si_pi->sram_end);
3414 si_pi->dte_table_start = tmp;
3416 ret = si_read_smc_sram_dword(rdev,
3417 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3418 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3419 &tmp, si_pi->sram_end);
3423 si_pi->spll_table_start = tmp;
3425 ret = si_read_smc_sram_dword(rdev,
3426 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3427 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3428 &tmp, si_pi->sram_end);
3432 si_pi->papm_cfg_table_start = tmp;
3437 static void si_read_clock_registers(struct radeon_device *rdev)
3439 struct si_power_info *si_pi = si_get_pi(rdev);
3441 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3442 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3443 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3444 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3445 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3446 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3447 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3448 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3449 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3450 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3451 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3452 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3453 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3454 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3455 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3458 static void si_enable_thermal_protection(struct radeon_device *rdev,
3462 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3464 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3467 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3469 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3473 static int si_enter_ulp_state(struct radeon_device *rdev)
3475 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3482 static int si_exit_ulp_state(struct radeon_device *rdev)
3486 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3490 for (i = 0; i < rdev->usec_timeout; i++) {
3491 if (RREG32(SMC_RESP_0) == 1)
3500 static int si_notify_smc_display_change(struct radeon_device *rdev,
3503 PPSMC_Msg msg = has_display ?
3504 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3506 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3510 static void si_program_response_times(struct radeon_device *rdev)
3512 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3513 u32 vddc_dly, acpi_dly, vbi_dly;
3514 u32 reference_clock;
3516 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3518 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3519 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3521 if (voltage_response_time == 0)
3522 voltage_response_time = 1000;
3524 acpi_delay_time = 15000;
3525 vbi_time_out = 100000;
3527 reference_clock = radeon_get_xclk(rdev);
3529 vddc_dly = (voltage_response_time * reference_clock) / 100;
3530 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3531 vbi_dly = (vbi_time_out * reference_clock) / 100;
3533 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3534 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3535 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3536 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3539 static void si_program_ds_registers(struct radeon_device *rdev)
3541 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3542 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3544 if (eg_pi->sclk_deep_sleep) {
3545 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3546 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3547 ~AUTOSCALE_ON_SS_CLEAR);
3551 static void si_program_display_gap(struct radeon_device *rdev)
3556 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3557 if (rdev->pm.dpm.new_active_crtc_count > 0)
3558 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3560 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3562 if (rdev->pm.dpm.new_active_crtc_count > 1)
3563 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3565 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3567 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3569 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3570 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3572 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3573 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3574 /* find the first active crtc */
3575 for (i = 0; i < rdev->num_crtc; i++) {
3576 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3579 if (i == rdev->num_crtc)
3584 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3585 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3586 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3589 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3590 * This can be a problem on PowerXpress systems or if you want to use the card
3591 * for offscreen rendering or compute if there are no crtcs enabled. Set it to
3592 * true for now so that performance scales even if the displays are off.
3594 si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
3597 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3599 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3603 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3605 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3606 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3610 static void si_setup_bsp(struct radeon_device *rdev)
3612 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3613 u32 xclk = radeon_get_xclk(rdev);
3615 r600_calculate_u_and_p(pi->asi,
3621 r600_calculate_u_and_p(pi->pasi,
3628 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3629 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3631 WREG32(CG_BSP, pi->dsp);
3634 static void si_program_git(struct radeon_device *rdev)
3636 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3639 static void si_program_tp(struct radeon_device *rdev)
3642 enum r600_td td = R600_TD_DFLT;
3644 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3645 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3647 if (td == R600_TD_AUTO)
3648 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3650 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3652 if (td == R600_TD_UP)
3653 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3655 if (td == R600_TD_DOWN)
3656 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3659 static void si_program_tpp(struct radeon_device *rdev)
3661 WREG32(CG_TPC, R600_TPC_DFLT);
3664 static void si_program_sstp(struct radeon_device *rdev)
3666 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3669 static void si_enable_display_gap(struct radeon_device *rdev)
3671 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3673 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3674 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3675 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3677 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3678 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3679 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3680 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3683 static void si_program_vc(struct radeon_device *rdev)
3685 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3687 WREG32(CG_FTV, pi->vrc);
3690 static void si_clear_vc(struct radeon_device *rdev)
3695 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3699 if (memory_clock < 10000)
3701 else if (memory_clock >= 80000)
3702 mc_para_index = 0x0f;
3704 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3705 return mc_para_index;
3708 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3713 if (memory_clock < 12500)
3714 mc_para_index = 0x00;
3715 else if (memory_clock > 47500)
3716 mc_para_index = 0x0f;
3718 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3720 if (memory_clock < 65000)
3721 mc_para_index = 0x00;
3722 else if (memory_clock > 135000)
3723 mc_para_index = 0x0f;
3725 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3727 return mc_para_index;
3730 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3732 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3733 bool strobe_mode = false;
3736 if (mclk <= pi->mclk_strobe_mode_threshold)
3740 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3742 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3745 result |= SISLANDS_SMC_STROBE_ENABLE;
3750 static int si_upload_firmware(struct radeon_device *rdev)
3752 struct si_power_info *si_pi = si_get_pi(rdev);
3756 si_stop_smc_clock(rdev);
3758 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3763 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3764 const struct atom_voltage_table *table,
3765 const struct radeon_phase_shedding_limits_table *limits)
3767 u32 data, num_bits, num_levels;
3769 if ((table == NULL) || (limits == NULL))
3772 data = table->mask_low;
3774 num_bits = hweight32(data);
3779 num_levels = (1 << num_bits);
3781 if (table->count != num_levels)
3784 if (limits->count != (num_levels - 1))
3790 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3791 u32 max_voltage_steps,
3792 struct atom_voltage_table *voltage_table)
3794 unsigned int i, diff;
3796 if (voltage_table->count <= max_voltage_steps)
3799 diff = voltage_table->count - max_voltage_steps;
3801 for (i= 0; i < max_voltage_steps; i++)
3802 voltage_table->entries[i] = voltage_table->entries[i + diff];
3804 voltage_table->count = max_voltage_steps;
3807 static int si_construct_voltage_tables(struct radeon_device *rdev)
3809 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3810 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3811 struct si_power_info *si_pi = si_get_pi(rdev);
3814 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3815 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3819 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3820 si_trim_voltage_table_to_fit_state_table(rdev,
3821 SISLANDS_MAX_NO_VREG_STEPS,
3822 &eg_pi->vddc_voltage_table);
3824 if (eg_pi->vddci_control) {
3825 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3826 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3830 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3831 si_trim_voltage_table_to_fit_state_table(rdev,
3832 SISLANDS_MAX_NO_VREG_STEPS,
3833 &eg_pi->vddci_voltage_table);
3836 if (pi->mvdd_control) {
3837 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3838 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3841 pi->mvdd_control = false;
3845 if (si_pi->mvdd_voltage_table.count == 0) {
3846 pi->mvdd_control = false;
3850 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3851 si_trim_voltage_table_to_fit_state_table(rdev,
3852 SISLANDS_MAX_NO_VREG_STEPS,
3853 &si_pi->mvdd_voltage_table);
3856 if (si_pi->vddc_phase_shed_control) {
3857 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3858 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3860 si_pi->vddc_phase_shed_control = false;
3862 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3863 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3864 si_pi->vddc_phase_shed_control = false;
3870 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3871 const struct atom_voltage_table *voltage_table,
3872 SISLANDS_SMC_STATETABLE *table)
3876 for (i = 0; i < voltage_table->count; i++)
3877 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3880 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3881 SISLANDS_SMC_STATETABLE *table)
3883 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3884 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3885 struct si_power_info *si_pi = si_get_pi(rdev);
3888 if (eg_pi->vddc_voltage_table.count) {
3889 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3890 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3891 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3893 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3894 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3895 table->maxVDDCIndexInPPTable = i;
3901 if (eg_pi->vddci_voltage_table.count) {
3902 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3904 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3905 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3909 if (si_pi->mvdd_voltage_table.count) {
3910 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3912 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3913 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3916 if (si_pi->vddc_phase_shed_control) {
3917 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3918 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3919 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3921 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3922 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3924 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3925 (u32)si_pi->vddc_phase_shed_table.phase_delay);
3927 si_pi->vddc_phase_shed_control = false;
3934 static int si_populate_voltage_value(struct radeon_device *rdev,
3935 const struct atom_voltage_table *table,
3936 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3940 for (i = 0; i < table->count; i++) {
3941 if (value <= table->entries[i].value) {
3942 voltage->index = (u8)i;
3943 voltage->value = cpu_to_be16(table->entries[i].value);
3948 if (i >= table->count)
3954 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3955 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3957 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3958 struct si_power_info *si_pi = si_get_pi(rdev);
3960 if (pi->mvdd_control) {
3961 if (mclk <= pi->mvdd_split_frequency)
3964 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3966 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3971 static int si_get_std_voltage_value(struct radeon_device *rdev,
3972 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3976 bool voltage_found = false;
3977 *std_voltage = be16_to_cpu(voltage->value);
3979 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3980 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3981 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3984 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3985 if (be16_to_cpu(voltage->value) ==
3986 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3987 voltage_found = true;
3988 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3990 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3993 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3998 if (!voltage_found) {
3999 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4000 if (be16_to_cpu(voltage->value) <=
4001 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4002 voltage_found = true;
4003 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4005 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4008 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4014 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4015 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4022 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4023 u16 value, u8 index,
4024 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4026 voltage->index = index;
4027 voltage->value = cpu_to_be16(value);
4032 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4033 const struct radeon_phase_shedding_limits_table *limits,
4034 u16 voltage, u32 sclk, u32 mclk,
4035 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4039 for (i = 0; i < limits->count; i++) {
4040 if ((voltage <= limits->entries[i].voltage) &&
4041 (sclk <= limits->entries[i].sclk) &&
4042 (mclk <= limits->entries[i].mclk))
4046 smc_voltage->phase_settings = (u8)i;
4051 static int si_init_arb_table_index(struct radeon_device *rdev)
4053 struct si_power_info *si_pi = si_get_pi(rdev);
4057 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4062 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4064 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4067 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4069 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4072 static int si_reset_to_default(struct radeon_device *rdev)
4074 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4078 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4080 struct si_power_info *si_pi = si_get_pi(rdev);
4084 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4085 &tmp, si_pi->sram_end);
4089 tmp = (tmp >> 24) & 0xff;
4091 if (tmp == MC_CG_ARB_FREQ_F0)
4094 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4097 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4101 u32 dram_refresh_rate;
4102 u32 mc_arb_rfsh_rate;
4103 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4108 dram_rows = 1 << (tmp + 10);
4110 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4111 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4113 return mc_arb_rfsh_rate;
4116 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4117 struct rv7xx_pl *pl,
4118 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4124 arb_regs->mc_arb_rfsh_rate =
4125 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4127 radeon_atom_set_engine_dram_timings(rdev,
4131 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4132 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4133 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4135 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4136 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4137 arb_regs->mc_arb_burst_time = (u8)burst_time;
4142 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4143 struct radeon_ps *radeon_state,
4144 unsigned int first_arb_set)
4146 struct si_power_info *si_pi = si_get_pi(rdev);
4147 struct ni_ps *state = ni_get_ps(radeon_state);
4148 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4151 for (i = 0; i < state->performance_level_count; i++) {
4152 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4155 ret = si_copy_bytes_to_smc(rdev,
4156 si_pi->arb_table_start +
4157 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4158 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4160 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4169 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4170 struct radeon_ps *radeon_new_state)
4172 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4173 SISLANDS_DRIVER_STATE_ARB_INDEX);
4176 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4177 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4179 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4180 struct si_power_info *si_pi = si_get_pi(rdev);
4182 if (pi->mvdd_control)
4183 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4184 si_pi->mvdd_bootup_value, voltage);
4189 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4190 struct radeon_ps *radeon_initial_state,
4191 SISLANDS_SMC_STATETABLE *table)
4193 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4194 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4195 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4196 struct si_power_info *si_pi = si_get_pi(rdev);
4200 table->initialState.levels[0].mclk.vDLL_CNTL =
4201 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4202 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4203 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4204 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4205 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4206 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4207 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4208 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4209 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4210 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4211 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4212 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4213 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4214 table->initialState.levels[0].mclk.vMPLL_SS =
4215 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4216 table->initialState.levels[0].mclk.vMPLL_SS2 =
4217 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4219 table->initialState.levels[0].mclk.mclk_value =
4220 cpu_to_be32(initial_state->performance_levels[0].mclk);
4222 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4223 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4224 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4225 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4226 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4227 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4228 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4229 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4230 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4231 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4232 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4233 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4235 table->initialState.levels[0].sclk.sclk_value =
4236 cpu_to_be32(initial_state->performance_levels[0].sclk);
4238 table->initialState.levels[0].arbRefreshState =
4239 SISLANDS_INITIAL_STATE_ARB_INDEX;
4241 table->initialState.levels[0].ACIndex = 0;
4243 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4244 initial_state->performance_levels[0].vddc,
4245 &table->initialState.levels[0].vddc);
4250 ret = si_get_std_voltage_value(rdev,
4251 &table->initialState.levels[0].vddc,
4254 si_populate_std_voltage_value(rdev, std_vddc,
4255 table->initialState.levels[0].vddc.index,
4256 &table->initialState.levels[0].std_vddc);
4259 if (eg_pi->vddci_control)
4260 si_populate_voltage_value(rdev,
4261 &eg_pi->vddci_voltage_table,
4262 initial_state->performance_levels[0].vddci,
4263 &table->initialState.levels[0].vddci);
4265 if (si_pi->vddc_phase_shed_control)
4266 si_populate_phase_shedding_value(rdev,
4267 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4268 initial_state->performance_levels[0].vddc,
4269 initial_state->performance_levels[0].sclk,
4270 initial_state->performance_levels[0].mclk,
4271 &table->initialState.levels[0].vddc);
4273 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4275 reg = CG_R(0xffff) | CG_L(0);
4276 table->initialState.levels[0].aT = cpu_to_be32(reg);
4278 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4280 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4282 if (pi->mem_gddr5) {
4283 table->initialState.levels[0].strobeMode =
4284 si_get_strobe_mode_settings(rdev,
4285 initial_state->performance_levels[0].mclk);
4287 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4288 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4290 table->initialState.levels[0].mcFlags = 0;
4293 table->initialState.levelCount = 1;
4295 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4297 table->initialState.levels[0].dpm2.MaxPS = 0;
4298 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4299 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4300 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4301 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4303 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4304 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4306 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4307 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4312 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4313 SISLANDS_SMC_STATETABLE *table)
4315 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4316 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4317 struct si_power_info *si_pi = si_get_pi(rdev);
4318 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4319 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4320 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4321 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4322 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4323 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4324 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4325 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4326 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4327 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4328 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4332 table->ACPIState = table->initialState;
4334 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4336 if (pi->acpi_vddc) {
4337 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4338 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4342 ret = si_get_std_voltage_value(rdev,
4343 &table->ACPIState.levels[0].vddc, &std_vddc);
4345 si_populate_std_voltage_value(rdev, std_vddc,
4346 table->ACPIState.levels[0].vddc.index,
4347 &table->ACPIState.levels[0].std_vddc);
4349 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4351 if (si_pi->vddc_phase_shed_control) {
4352 si_populate_phase_shedding_value(rdev,
4353 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4357 &table->ACPIState.levels[0].vddc);
4360 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4361 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4365 ret = si_get_std_voltage_value(rdev,
4366 &table->ACPIState.levels[0].vddc, &std_vddc);
4369 si_populate_std_voltage_value(rdev, std_vddc,
4370 table->ACPIState.levels[0].vddc.index,
4371 &table->ACPIState.levels[0].std_vddc);
4373 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4374 si_pi->sys_pcie_mask,
4375 si_pi->boot_pcie_gen,
4378 if (si_pi->vddc_phase_shed_control)
4379 si_populate_phase_shedding_value(rdev,
4380 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4381 pi->min_vddc_in_table,
4384 &table->ACPIState.levels[0].vddc);
4387 if (pi->acpi_vddc) {
4388 if (eg_pi->acpi_vddci)
4389 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4391 &table->ACPIState.levels[0].vddci);
4394 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4395 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4397 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4399 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4400 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4402 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4403 cpu_to_be32(dll_cntl);
4404 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4405 cpu_to_be32(mclk_pwrmgt_cntl);
4406 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4407 cpu_to_be32(mpll_ad_func_cntl);
4408 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4409 cpu_to_be32(mpll_dq_func_cntl);
4410 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4411 cpu_to_be32(mpll_func_cntl);
4412 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4413 cpu_to_be32(mpll_func_cntl_1);
4414 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4415 cpu_to_be32(mpll_func_cntl_2);
4416 table->ACPIState.levels[0].mclk.vMPLL_SS =
4417 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4418 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4419 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4421 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4422 cpu_to_be32(spll_func_cntl);
4423 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4424 cpu_to_be32(spll_func_cntl_2);
4425 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4426 cpu_to_be32(spll_func_cntl_3);
4427 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4428 cpu_to_be32(spll_func_cntl_4);
4430 table->ACPIState.levels[0].mclk.mclk_value = 0;
4431 table->ACPIState.levels[0].sclk.sclk_value = 0;
4433 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4435 if (eg_pi->dynamic_ac_timing)
4436 table->ACPIState.levels[0].ACIndex = 0;
4438 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4439 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4440 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4441 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4442 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4444 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4445 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4447 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4448 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4453 static int si_populate_ulv_state(struct radeon_device *rdev,
4454 SISLANDS_SMC_SWSTATE *state)
4456 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4457 struct si_power_info *si_pi = si_get_pi(rdev);
4458 struct si_ulv_param *ulv = &si_pi->ulv;
4459 u32 sclk_in_sr = 1350; /* ??? */
4462 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4465 if (eg_pi->sclk_deep_sleep) {
4466 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4467 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4469 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4471 if (ulv->one_pcie_lane_in_ulv)
4472 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4473 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4474 state->levels[0].ACIndex = 1;
4475 state->levels[0].std_vddc = state->levels[0].vddc;
4476 state->levelCount = 1;
4478 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4484 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4486 struct si_power_info *si_pi = si_get_pi(rdev);
4487 struct si_ulv_param *ulv = &si_pi->ulv;
4488 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4491 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4496 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4497 ulv->volt_change_delay);
4499 ret = si_copy_bytes_to_smc(rdev,
4500 si_pi->arb_table_start +
4501 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4502 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4504 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4510 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4512 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4514 pi->mvdd_split_frequency = 30000;
4517 static int si_init_smc_table(struct radeon_device *rdev)
4519 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4520 struct si_power_info *si_pi = si_get_pi(rdev);
4521 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4522 const struct si_ulv_param *ulv = &si_pi->ulv;
4523 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4528 si_populate_smc_voltage_tables(rdev, table);
4530 switch (rdev->pm.int_thermal_type) {
4531 case THERMAL_TYPE_SI:
4532 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4533 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4535 case THERMAL_TYPE_NONE:
4536 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4539 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4543 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4544 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4546 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4547 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4548 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4551 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4552 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4555 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4557 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4558 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4560 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4561 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4562 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4563 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4567 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4571 ret = si_populate_smc_acpi_state(rdev, table);
4575 table->driverState = table->initialState;
4577 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4578 SISLANDS_INITIAL_STATE_ARB_INDEX);
4582 if (ulv->supported && ulv->pl.vddc) {
4583 ret = si_populate_ulv_state(rdev, &table->ULVState);
4587 ret = si_program_ulv_memory_timing_parameters(rdev);
4591 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4592 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4594 lane_width = radeon_get_pcie_lanes(rdev);
4595 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4597 table->ULVState = table->initialState;
4600 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4601 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4605 static int si_calculate_sclk_params(struct radeon_device *rdev,
4607 SISLANDS_SMC_SCLK_VALUE *sclk)
4609 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4610 struct si_power_info *si_pi = si_get_pi(rdev);
4611 struct atom_clock_dividers dividers;
4612 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4613 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4614 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4615 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4616 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4617 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4619 u32 reference_clock = rdev->clock.spll.reference_freq;
4620 u32 reference_divider;
4624 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4625 engine_clock, false, ÷rs);
4629 reference_divider = 1 + dividers.ref_div;
4631 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4632 do_div(tmp, reference_clock);
4635 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4636 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4637 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4639 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4640 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4642 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4643 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4644 spll_func_cntl_3 |= SPLL_DITHEN;
4647 struct radeon_atom_ss ss;
4648 u32 vco_freq = engine_clock * dividers.post_div;
4650 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4651 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4652 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4653 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4655 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4656 cg_spll_spread_spectrum |= CLK_S(clk_s);
4657 cg_spll_spread_spectrum |= SSEN;
4659 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4660 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4664 sclk->sclk_value = engine_clock;
4665 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4666 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4667 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4668 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4669 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4670 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4675 static int si_populate_sclk_value(struct radeon_device *rdev,
4677 SISLANDS_SMC_SCLK_VALUE *sclk)
4679 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4682 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4684 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4685 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4686 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4687 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4688 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4689 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4690 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4696 static int si_populate_mclk_value(struct radeon_device *rdev,
4699 SISLANDS_SMC_MCLK_VALUE *mclk,
4703 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4704 struct si_power_info *si_pi = si_get_pi(rdev);
4705 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4706 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4707 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4708 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4709 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4710 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4711 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4712 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4713 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4714 struct atom_mpll_param mpll_param;
4717 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4721 mpll_func_cntl &= ~BWCTRL_MASK;
4722 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4724 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4725 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4726 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4728 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4729 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4731 if (pi->mem_gddr5) {
4732 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4733 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4734 YCLK_POST_DIV(mpll_param.post_div);
4738 struct radeon_atom_ss ss;
4741 u32 reference_clock = rdev->clock.mpll.reference_freq;
4744 freq_nom = memory_clock * 4;
4746 freq_nom = memory_clock * 2;
4748 tmp = freq_nom / reference_clock;
4750 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4751 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4752 u32 clks = reference_clock * 5 / ss.rate;
4753 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4755 mpll_ss1 &= ~CLKV_MASK;
4756 mpll_ss1 |= CLKV(clkv);
4758 mpll_ss2 &= ~CLKS_MASK;
4759 mpll_ss2 |= CLKS(clks);
4763 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4764 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4767 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4769 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4771 mclk->mclk_value = cpu_to_be32(memory_clock);
4772 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4773 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4774 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4775 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4776 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4777 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4778 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4779 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4780 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4785 static void si_populate_smc_sp(struct radeon_device *rdev,
4786 struct radeon_ps *radeon_state,
4787 SISLANDS_SMC_SWSTATE *smc_state)
4789 struct ni_ps *ps = ni_get_ps(radeon_state);
4790 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4793 for (i = 0; i < ps->performance_level_count - 1; i++)
4794 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4796 smc_state->levels[ps->performance_level_count - 1].bSP =
4797 cpu_to_be32(pi->psp);
4800 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4801 struct rv7xx_pl *pl,
4802 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4804 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4805 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4806 struct si_power_info *si_pi = si_get_pi(rdev);
4810 bool gmc_pg = false;
4812 if (eg_pi->pcie_performance_request &&
4813 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4814 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4816 level->gen2PCIE = (u8)pl->pcie_gen;
4818 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4824 if (pi->mclk_stutter_mode_threshold &&
4825 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4826 !eg_pi->uvd_enabled &&
4827 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4828 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4829 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4832 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4835 if (pi->mem_gddr5) {
4836 if (pl->mclk > pi->mclk_edc_enable_threshold)
4837 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4839 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4840 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4842 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4844 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4845 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4846 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4847 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4849 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4851 dll_state_on = false;
4854 level->strobeMode = si_get_strobe_mode_settings(rdev,
4857 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4860 ret = si_populate_mclk_value(rdev,
4864 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4868 ret = si_populate_voltage_value(rdev,
4869 &eg_pi->vddc_voltage_table,
4870 pl->vddc, &level->vddc);
4875 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4879 ret = si_populate_std_voltage_value(rdev, std_vddc,
4880 level->vddc.index, &level->std_vddc);
4884 if (eg_pi->vddci_control) {
4885 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4886 pl->vddci, &level->vddci);
4891 if (si_pi->vddc_phase_shed_control) {
4892 ret = si_populate_phase_shedding_value(rdev,
4893 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4902 level->MaxPoweredUpCU = si_pi->max_cu;
4904 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4909 static int si_populate_smc_t(struct radeon_device *rdev,
4910 struct radeon_ps *radeon_state,
4911 SISLANDS_SMC_SWSTATE *smc_state)
4913 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4914 struct ni_ps *state = ni_get_ps(radeon_state);
4920 if (state->performance_level_count >= 9)
4923 if (state->performance_level_count < 2) {
4924 a_t = CG_R(0xffff) | CG_L(0);
4925 smc_state->levels[0].aT = cpu_to_be32(a_t);
4929 smc_state->levels[0].aT = cpu_to_be32(0);
4931 for (i = 0; i <= state->performance_level_count - 2; i++) {
4932 ret = r600_calculate_at(
4933 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4935 state->performance_levels[i + 1].sclk,
4936 state->performance_levels[i].sclk,
4941 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4942 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4945 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4946 a_t |= CG_R(t_l * pi->bsp / 20000);
4947 smc_state->levels[i].aT = cpu_to_be32(a_t);
4949 high_bsp = (i == state->performance_level_count - 2) ?
4951 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4952 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4958 static int si_disable_ulv(struct radeon_device *rdev)
4960 struct si_power_info *si_pi = si_get_pi(rdev);
4961 struct si_ulv_param *ulv = &si_pi->ulv;
4964 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4970 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4971 struct radeon_ps *radeon_state)
4973 const struct si_power_info *si_pi = si_get_pi(rdev);
4974 const struct si_ulv_param *ulv = &si_pi->ulv;
4975 const struct ni_ps *state = ni_get_ps(radeon_state);
4978 if (state->performance_levels[0].mclk != ulv->pl.mclk)
4981 /* XXX validate against display requirements! */
4983 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4984 if (rdev->clock.current_dispclk <=
4985 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4987 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4992 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4998 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4999 struct radeon_ps *radeon_new_state)
5001 const struct si_power_info *si_pi = si_get_pi(rdev);
5002 const struct si_ulv_param *ulv = &si_pi->ulv;
5004 if (ulv->supported) {
5005 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5006 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5012 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5013 struct radeon_ps *radeon_state,
5014 SISLANDS_SMC_SWSTATE *smc_state)
5016 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5017 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5018 struct si_power_info *si_pi = si_get_pi(rdev);
5019 struct ni_ps *state = ni_get_ps(radeon_state);
5022 u32 sclk_in_sr = 1350; /* ??? */
5024 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5027 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5029 if (radeon_state->vclk && radeon_state->dclk) {
5030 eg_pi->uvd_enabled = true;
5031 if (eg_pi->smu_uvd_hs)
5032 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5034 eg_pi->uvd_enabled = false;
5037 if (state->dc_compatible)
5038 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5040 smc_state->levelCount = 0;
5041 for (i = 0; i < state->performance_level_count; i++) {
5042 if (eg_pi->sclk_deep_sleep) {
5043 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5044 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5045 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5047 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5051 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5052 &smc_state->levels[i]);
5053 smc_state->levels[i].arbRefreshState =
5054 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5059 if (ni_pi->enable_power_containment)
5060 smc_state->levels[i].displayWatermark =
5061 (state->performance_levels[i].sclk < threshold) ?
5062 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5064 smc_state->levels[i].displayWatermark = (i < 2) ?
5065 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5067 if (eg_pi->dynamic_ac_timing)
5068 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5070 smc_state->levels[i].ACIndex = 0;
5072 smc_state->levelCount++;
5075 si_write_smc_soft_register(rdev,
5076 SI_SMC_SOFT_REGISTER_watermark_threshold,
5079 si_populate_smc_sp(rdev, radeon_state, smc_state);
5081 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5083 ni_pi->enable_power_containment = false;
5085 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5087 ni_pi->enable_sq_ramping = false;
5089 return si_populate_smc_t(rdev, radeon_state, smc_state);
5092 static int si_upload_sw_state(struct radeon_device *rdev,
5093 struct radeon_ps *radeon_new_state)
5095 struct si_power_info *si_pi = si_get_pi(rdev);
5096 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5098 u32 address = si_pi->state_table_start +
5099 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5100 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5101 ((new_state->performance_level_count - 1) *
5102 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5103 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5105 memset(smc_state, 0, state_size);
5107 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5111 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5112 state_size, si_pi->sram_end);
5117 static int si_upload_ulv_state(struct radeon_device *rdev)
5119 struct si_power_info *si_pi = si_get_pi(rdev);
5120 struct si_ulv_param *ulv = &si_pi->ulv;
5123 if (ulv->supported && ulv->pl.vddc) {
5124 u32 address = si_pi->state_table_start +
5125 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5126 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5127 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5129 memset(smc_state, 0, state_size);
5131 ret = si_populate_ulv_state(rdev, smc_state);
5133 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5134 state_size, si_pi->sram_end);
5140 static int si_upload_smc_data(struct radeon_device *rdev)
5142 struct radeon_crtc *radeon_crtc = NULL;
5145 if (rdev->pm.dpm.new_active_crtc_count == 0)
5148 for (i = 0; i < rdev->num_crtc; i++) {
5149 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5150 radeon_crtc = rdev->mode_info.crtcs[i];
5155 if (radeon_crtc == NULL)
5158 if (radeon_crtc->line_time <= 0)
5161 if (si_write_smc_soft_register(rdev,
5162 SI_SMC_SOFT_REGISTER_crtc_index,
5163 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5166 if (si_write_smc_soft_register(rdev,
5167 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5168 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5171 if (si_write_smc_soft_register(rdev,
5172 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5173 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5179 static int si_set_mc_special_registers(struct radeon_device *rdev,
5180 struct si_mc_reg_table *table)
5182 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5186 for (i = 0, j = table->last; i < table->last; i++) {
5187 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5189 switch (table->mc_reg_address[i].s1 << 2) {
5191 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5192 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5193 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5194 for (k = 0; k < table->num_entries; k++)
5195 table->mc_reg_table_entry[k].mc_data[j] =
5196 ((temp_reg & 0xffff0000)) |
5197 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5199 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5202 temp_reg = RREG32(MC_PMG_CMD_MRS);
5203 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5204 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5205 for (k = 0; k < table->num_entries; k++) {
5206 table->mc_reg_table_entry[k].mc_data[j] =
5207 (temp_reg & 0xffff0000) |
5208 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5210 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5213 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5216 if (!pi->mem_gddr5) {
5217 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5218 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5219 for (k = 0; k < table->num_entries; k++)
5220 table->mc_reg_table_entry[k].mc_data[j] =
5221 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5223 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5227 case MC_SEQ_RESERVE_M:
5228 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5229 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5230 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5231 for(k = 0; k < table->num_entries; k++)
5232 table->mc_reg_table_entry[k].mc_data[j] =
5233 (temp_reg & 0xffff0000) |
5234 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5236 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5249 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5254 case MC_SEQ_RAS_TIMING >> 2:
5255 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5257 case MC_SEQ_CAS_TIMING >> 2:
5258 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5260 case MC_SEQ_MISC_TIMING >> 2:
5261 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5263 case MC_SEQ_MISC_TIMING2 >> 2:
5264 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5266 case MC_SEQ_RD_CTL_D0 >> 2:
5267 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5269 case MC_SEQ_RD_CTL_D1 >> 2:
5270 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5272 case MC_SEQ_WR_CTL_D0 >> 2:
5273 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5275 case MC_SEQ_WR_CTL_D1 >> 2:
5276 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5278 case MC_PMG_CMD_EMRS >> 2:
5279 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5281 case MC_PMG_CMD_MRS >> 2:
5282 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5284 case MC_PMG_CMD_MRS1 >> 2:
5285 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5287 case MC_SEQ_PMG_TIMING >> 2:
5288 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5290 case MC_PMG_CMD_MRS2 >> 2:
5291 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5293 case MC_SEQ_WR_CTL_2 >> 2:
5294 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5304 static void si_set_valid_flag(struct si_mc_reg_table *table)
5308 for (i = 0; i < table->last; i++) {
5309 for (j = 1; j < table->num_entries; j++) {
5310 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5311 table->valid_flag |= 1 << i;
5318 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5323 for (i = 0; i < table->last; i++)
5324 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5325 address : table->mc_reg_address[i].s1;
5329 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5330 struct si_mc_reg_table *si_table)
5334 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5336 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5339 for (i = 0; i < table->last; i++)
5340 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5341 si_table->last = table->last;
5343 for (i = 0; i < table->num_entries; i++) {
5344 si_table->mc_reg_table_entry[i].mclk_max =
5345 table->mc_reg_table_entry[i].mclk_max;
5346 for (j = 0; j < table->last; j++) {
5347 si_table->mc_reg_table_entry[i].mc_data[j] =
5348 table->mc_reg_table_entry[i].mc_data[j];
5351 si_table->num_entries = table->num_entries;
5356 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5358 struct si_power_info *si_pi = si_get_pi(rdev);
5359 struct atom_mc_reg_table *table;
5360 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5361 u8 module_index = rv770_get_memory_module_index(rdev);
5364 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5368 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5369 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5370 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5371 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5372 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5373 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5374 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5375 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5376 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5377 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5378 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5379 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5380 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5381 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5383 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5387 ret = si_copy_vbios_mc_reg_table(table, si_table);
5391 si_set_s0_mc_reg_index(si_table);
5393 ret = si_set_mc_special_registers(rdev, si_table);
5397 si_set_valid_flag(si_table);
5406 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5407 SMC_SIslands_MCRegisters *mc_reg_table)
5409 struct si_power_info *si_pi = si_get_pi(rdev);
5412 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5413 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5414 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5416 mc_reg_table->address[i].s0 =
5417 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5418 mc_reg_table->address[i].s1 =
5419 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5423 mc_reg_table->last = (u8)i;
5426 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5427 SMC_SIslands_MCRegisterSet *data,
5428 u32 num_entries, u32 valid_flag)
5432 for(i = 0, j = 0; j < num_entries; j++) {
5433 if (valid_flag & (1 << j)) {
5434 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5440 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5441 struct rv7xx_pl *pl,
5442 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5444 struct si_power_info *si_pi = si_get_pi(rdev);
5447 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5448 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5452 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5455 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5456 mc_reg_table_data, si_pi->mc_reg_table.last,
5457 si_pi->mc_reg_table.valid_flag);
5460 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5461 struct radeon_ps *radeon_state,
5462 SMC_SIslands_MCRegisters *mc_reg_table)
5464 struct ni_ps *state = ni_get_ps(radeon_state);
5467 for (i = 0; i < state->performance_level_count; i++) {
5468 si_convert_mc_reg_table_entry_to_smc(rdev,
5469 &state->performance_levels[i],
5470 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5474 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5475 struct radeon_ps *radeon_boot_state)
5477 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5478 struct si_power_info *si_pi = si_get_pi(rdev);
5479 struct si_ulv_param *ulv = &si_pi->ulv;
5480 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5482 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5484 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5486 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5488 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5489 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5491 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5492 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5493 si_pi->mc_reg_table.last,
5494 si_pi->mc_reg_table.valid_flag);
5496 if (ulv->supported && ulv->pl.vddc != 0)
5497 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5498 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5500 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5501 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5502 si_pi->mc_reg_table.last,
5503 si_pi->mc_reg_table.valid_flag);
5505 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5507 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5508 (u8 *)smc_mc_reg_table,
5509 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5512 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5513 struct radeon_ps *radeon_new_state)
5515 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5516 struct si_power_info *si_pi = si_get_pi(rdev);
5517 u32 address = si_pi->mc_reg_table_start +
5518 offsetof(SMC_SIslands_MCRegisters,
5519 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5520 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5522 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5524 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5527 return si_copy_bytes_to_smc(rdev, address,
5528 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5529 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5534 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5537 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5539 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5542 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5543 struct radeon_ps *radeon_state)
5545 struct ni_ps *state = ni_get_ps(radeon_state);
5547 u16 pcie_speed, max_speed = 0;
5549 for (i = 0; i < state->performance_level_count; i++) {
5550 pcie_speed = state->performance_levels[i].pcie_gen;
5551 if (max_speed < pcie_speed)
5552 max_speed = pcie_speed;
5557 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5561 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5562 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5564 return (u16)speed_cntl;
5567 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5568 struct radeon_ps *radeon_new_state,
5569 struct radeon_ps *radeon_current_state)
5571 struct si_power_info *si_pi = si_get_pi(rdev);
5572 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5573 enum radeon_pcie_gen current_link_speed;
5575 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5576 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5578 current_link_speed = si_pi->force_pcie_gen;
5580 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5581 si_pi->pspp_notify_required = false;
5582 if (target_link_speed > current_link_speed) {
5583 switch (target_link_speed) {
5584 #if defined(CONFIG_ACPI)
5585 case RADEON_PCIE_GEN3:
5586 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5588 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5589 if (current_link_speed == RADEON_PCIE_GEN2)
5591 case RADEON_PCIE_GEN2:
5592 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5596 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5600 if (target_link_speed < current_link_speed)
5601 si_pi->pspp_notify_required = true;
5605 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5606 struct radeon_ps *radeon_new_state,
5607 struct radeon_ps *radeon_current_state)
5609 struct si_power_info *si_pi = si_get_pi(rdev);
5610 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5613 if (si_pi->pspp_notify_required) {
5614 if (target_link_speed == RADEON_PCIE_GEN3)
5615 request = PCIE_PERF_REQ_PECI_GEN3;
5616 else if (target_link_speed == RADEON_PCIE_GEN2)
5617 request = PCIE_PERF_REQ_PECI_GEN2;
5619 request = PCIE_PERF_REQ_PECI_GEN1;
5621 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5622 (si_get_current_pcie_speed(rdev) > 0))
5625 #if defined(CONFIG_ACPI)
5626 radeon_acpi_pcie_performance_request(rdev, request, false);
5632 static int si_ds_request(struct radeon_device *rdev,
5633 bool ds_status_on, u32 count_write)
5635 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5637 if (eg_pi->sclk_deep_sleep) {
5639 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5643 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5644 PPSMC_Result_OK) ? 0 : -EINVAL;
5650 static void si_set_max_cu_value(struct radeon_device *rdev)
5652 struct si_power_info *si_pi = si_get_pi(rdev);
5654 if (rdev->family == CHIP_VERDE) {
5655 switch (rdev->pdev->device) {
5691 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5692 struct radeon_clock_voltage_dependency_table *table)
5696 u16 leakage_voltage;
5699 for (i = 0; i < table->count; i++) {
5700 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5701 table->entries[i].v,
5702 &leakage_voltage)) {
5704 table->entries[i].v = leakage_voltage;
5714 for (j = (table->count - 2); j >= 0; j--) {
5715 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5716 table->entries[j].v : table->entries[j + 1].v;
5722 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5726 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5727 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5728 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5729 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5730 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5731 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5735 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5736 struct radeon_ps *radeon_new_state,
5737 struct radeon_ps *radeon_current_state)
5740 u32 new_lane_width =
5741 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5742 u32 current_lane_width =
5743 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5745 if (new_lane_width != current_lane_width) {
5746 radeon_set_pcie_lanes(rdev, new_lane_width);
5747 lane_width = radeon_get_pcie_lanes(rdev);
5748 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5752 void si_dpm_setup_asic(struct radeon_device *rdev)
5754 rv770_get_memory_type(rdev);
5755 si_read_clock_registers(rdev);
5756 si_enable_acpi_power_management(rdev);
5759 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5760 int min_temp, int max_temp)
5762 int low_temp = 0 * 1000;
5763 int high_temp = 255 * 1000;
5765 if (low_temp < min_temp)
5766 low_temp = min_temp;
5767 if (high_temp > max_temp)
5768 high_temp = max_temp;
5769 if (high_temp < low_temp) {
5770 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5774 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5775 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5776 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5778 rdev->pm.dpm.thermal.min_temp = low_temp;
5779 rdev->pm.dpm.thermal.max_temp = high_temp;
5784 int si_dpm_enable(struct radeon_device *rdev)
5786 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5787 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5788 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5791 if (si_is_smc_running(rdev))
5793 if (pi->voltage_control)
5794 si_enable_voltage_control(rdev, true);
5795 if (pi->mvdd_control)
5796 si_get_mvdd_configuration(rdev);
5797 if (pi->voltage_control) {
5798 ret = si_construct_voltage_tables(rdev);
5800 DRM_ERROR("si_construct_voltage_tables failed\n");
5804 if (eg_pi->dynamic_ac_timing) {
5805 ret = si_initialize_mc_reg_table(rdev);
5807 eg_pi->dynamic_ac_timing = false;
5810 si_enable_spread_spectrum(rdev, true);
5811 if (pi->thermal_protection)
5812 si_enable_thermal_protection(rdev, true);
5814 si_program_git(rdev);
5815 si_program_tp(rdev);
5816 si_program_tpp(rdev);
5817 si_program_sstp(rdev);
5818 si_enable_display_gap(rdev);
5819 si_program_vc(rdev);
5820 ret = si_upload_firmware(rdev);
5822 DRM_ERROR("si_upload_firmware failed\n");
5825 ret = si_process_firmware_header(rdev);
5827 DRM_ERROR("si_process_firmware_header failed\n");
5830 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5832 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5835 ret = si_init_smc_table(rdev);
5837 DRM_ERROR("si_init_smc_table failed\n");
5840 ret = si_init_smc_spll_table(rdev);
5842 DRM_ERROR("si_init_smc_spll_table failed\n");
5845 ret = si_init_arb_table_index(rdev);
5847 DRM_ERROR("si_init_arb_table_index failed\n");
5850 if (eg_pi->dynamic_ac_timing) {
5851 ret = si_populate_mc_reg_table(rdev, boot_ps);
5853 DRM_ERROR("si_populate_mc_reg_table failed\n");
5857 ret = si_initialize_smc_cac_tables(rdev);
5859 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5862 ret = si_initialize_hardware_cac_manager(rdev);
5864 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5867 ret = si_initialize_smc_dte_tables(rdev);
5869 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5872 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5874 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5877 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5879 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5882 si_program_response_times(rdev);
5883 si_program_ds_registers(rdev);
5884 si_dpm_start_smc(rdev);
5885 ret = si_notify_smc_display_change(rdev, false);
5887 DRM_ERROR("si_notify_smc_display_change failed\n");
5890 si_enable_sclk_control(rdev, true);
5893 if (rdev->irq.installed &&
5894 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5895 PPSMC_Result result;
5897 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5900 rdev->irq.dpm_thermal = true;
5901 radeon_irq_set(rdev);
5902 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5904 if (result != PPSMC_Result_OK)
5905 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5908 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5910 ni_update_current_ps(rdev, boot_ps);
5915 void si_dpm_disable(struct radeon_device *rdev)
5917 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5918 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5920 if (!si_is_smc_running(rdev))
5922 si_disable_ulv(rdev);
5924 if (pi->thermal_protection)
5925 si_enable_thermal_protection(rdev, false);
5926 si_enable_power_containment(rdev, boot_ps, false);
5927 si_enable_smc_cac(rdev, boot_ps, false);
5928 si_enable_spread_spectrum(rdev, false);
5929 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5931 si_reset_to_default(rdev);
5932 si_dpm_stop_smc(rdev);
5933 si_force_switch_to_arb_f0(rdev);
5935 ni_update_current_ps(rdev, boot_ps);
5938 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5940 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5941 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5942 struct radeon_ps *new_ps = &requested_ps;
5944 ni_update_requested_ps(rdev, new_ps);
5946 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5951 static int si_power_control_set_level(struct radeon_device *rdev)
5953 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5956 ret = si_restrict_performance_levels_before_switch(rdev);
5959 ret = si_halt_smc(rdev);
5962 ret = si_populate_smc_tdp_limits(rdev, new_ps);
5965 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5968 ret = si_resume_smc(rdev);
5971 ret = si_set_sw_state(rdev);
5977 int si_dpm_set_power_state(struct radeon_device *rdev)
5979 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5980 struct radeon_ps *new_ps = &eg_pi->requested_rps;
5981 struct radeon_ps *old_ps = &eg_pi->current_rps;
5984 ret = si_disable_ulv(rdev);
5986 DRM_ERROR("si_disable_ulv failed\n");
5989 ret = si_restrict_performance_levels_before_switch(rdev);
5991 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5994 if (eg_pi->pcie_performance_request)
5995 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5996 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5997 ret = si_enable_power_containment(rdev, new_ps, false);
5999 DRM_ERROR("si_enable_power_containment failed\n");
6002 ret = si_enable_smc_cac(rdev, new_ps, false);
6004 DRM_ERROR("si_enable_smc_cac failed\n");
6007 ret = si_halt_smc(rdev);
6009 DRM_ERROR("si_halt_smc failed\n");
6012 ret = si_upload_sw_state(rdev, new_ps);
6014 DRM_ERROR("si_upload_sw_state failed\n");
6017 ret = si_upload_smc_data(rdev);
6019 DRM_ERROR("si_upload_smc_data failed\n");
6022 ret = si_upload_ulv_state(rdev);
6024 DRM_ERROR("si_upload_ulv_state failed\n");
6027 if (eg_pi->dynamic_ac_timing) {
6028 ret = si_upload_mc_reg_table(rdev, new_ps);
6030 DRM_ERROR("si_upload_mc_reg_table failed\n");
6034 ret = si_program_memory_timing_parameters(rdev, new_ps);
6036 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6039 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6041 ret = si_resume_smc(rdev);
6043 DRM_ERROR("si_resume_smc failed\n");
6046 ret = si_set_sw_state(rdev);
6048 DRM_ERROR("si_set_sw_state failed\n");
6051 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6052 if (eg_pi->pcie_performance_request)
6053 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6054 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6056 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6059 ret = si_enable_smc_cac(rdev, new_ps, true);
6061 DRM_ERROR("si_enable_smc_cac failed\n");
6064 ret = si_enable_power_containment(rdev, new_ps, true);
6066 DRM_ERROR("si_enable_power_containment failed\n");
6070 ret = si_power_control_set_level(rdev);
6072 DRM_ERROR("si_power_control_set_level failed\n");
6079 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6081 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6082 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6084 ni_update_current_ps(rdev, new_ps);
6088 void si_dpm_reset_asic(struct radeon_device *rdev)
6090 si_restrict_performance_levels_before_switch(rdev);
6091 si_disable_ulv(rdev);
6092 si_set_boot_state(rdev);
6095 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6097 si_program_display_gap(rdev);
6101 struct _ATOM_POWERPLAY_INFO info;
6102 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6103 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6104 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6105 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6106 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6109 union pplib_clock_info {
6110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6114 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6117 union pplib_power_state {
6118 struct _ATOM_PPLIB_STATE v1;
6119 struct _ATOM_PPLIB_STATE_V2 v2;
6122 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6123 struct radeon_ps *rps,
6124 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6127 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6128 rps->class = le16_to_cpu(non_clock_info->usClassification);
6129 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6131 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6132 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6133 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6134 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6135 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6136 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6142 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6143 rdev->pm.dpm.boot_ps = rps;
6144 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6145 rdev->pm.dpm.uvd_ps = rps;
6148 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6149 struct radeon_ps *rps, int index,
6150 union pplib_clock_info *clock_info)
6152 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6153 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6154 struct si_power_info *si_pi = si_get_pi(rdev);
6155 struct ni_ps *ps = ni_get_ps(rps);
6156 u16 leakage_voltage;
6157 struct rv7xx_pl *pl = &ps->performance_levels[index];
6160 ps->performance_level_count = index + 1;
6162 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6163 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6164 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6165 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6167 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6168 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6169 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6170 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6171 si_pi->sys_pcie_mask,
6172 si_pi->boot_pcie_gen,
6173 clock_info->si.ucPCIEGen);
6175 /* patch up vddc if necessary */
6176 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6179 pl->vddc = leakage_voltage;
6181 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6182 pi->acpi_vddc = pl->vddc;
6183 eg_pi->acpi_vddci = pl->vddci;
6184 si_pi->acpi_pcie_gen = pl->pcie_gen;
6187 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6189 /* XXX disable for A0 tahiti */
6190 si_pi->ulv.supported = true;
6191 si_pi->ulv.pl = *pl;
6192 si_pi->ulv.one_pcie_lane_in_ulv = false;
6193 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6194 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6195 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6198 if (pi->min_vddc_in_table > pl->vddc)
6199 pi->min_vddc_in_table = pl->vddc;
6201 if (pi->max_vddc_in_table < pl->vddc)
6202 pi->max_vddc_in_table = pl->vddc;
6204 /* patch up boot state */
6205 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6206 u16 vddc, vddci, mvdd;
6207 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6208 pl->mclk = rdev->clock.default_mclk;
6209 pl->sclk = rdev->clock.default_sclk;
6212 si_pi->mvdd_bootup_value = mvdd;
6215 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6216 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6217 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6218 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6219 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6220 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6224 static int si_parse_power_table(struct radeon_device *rdev)
6226 struct radeon_mode_info *mode_info = &rdev->mode_info;
6227 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6228 union pplib_power_state *power_state;
6229 int i, j, k, non_clock_array_index, clock_array_index;
6230 union pplib_clock_info *clock_info;
6231 struct _StateArray *state_array;
6232 struct _ClockInfoArray *clock_info_array;
6233 struct _NonClockInfoArray *non_clock_info_array;
6234 union power_info *power_info;
6235 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6238 u8 *power_state_offset;
6241 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6242 &frev, &crev, &data_offset))
6244 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6246 state_array = (struct _StateArray *)
6247 (mode_info->atom_context->bios + data_offset +
6248 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6249 clock_info_array = (struct _ClockInfoArray *)
6250 (mode_info->atom_context->bios + data_offset +
6251 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6252 non_clock_info_array = (struct _NonClockInfoArray *)
6253 (mode_info->atom_context->bios + data_offset +
6254 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6256 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6257 state_array->ucNumEntries, GFP_KERNEL);
6258 if (!rdev->pm.dpm.ps)
6260 power_state_offset = (u8 *)state_array->states;
6261 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6262 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6263 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6264 for (i = 0; i < state_array->ucNumEntries; i++) {
6266 power_state = (union pplib_power_state *)power_state_offset;
6267 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6268 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6269 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6270 if (!rdev->pm.power_state[i].clock_info)
6272 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6274 kfree(rdev->pm.dpm.ps);
6277 rdev->pm.dpm.ps[i].ps_priv = ps;
6278 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6280 non_clock_info_array->ucEntrySize);
6282 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6283 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6284 clock_array_index = idx[j];
6285 if (clock_array_index >= clock_info_array->ucNumEntries)
6287 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6289 clock_info = (union pplib_clock_info *)
6290 ((u8 *)&clock_info_array->clockInfo[0] +
6291 (clock_array_index * clock_info_array->ucEntrySize));
6292 si_parse_pplib_clock_info(rdev,
6293 &rdev->pm.dpm.ps[i], k,
6297 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6299 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6303 int si_dpm_init(struct radeon_device *rdev)
6305 struct rv7xx_power_info *pi;
6306 struct evergreen_power_info *eg_pi;
6307 struct ni_power_info *ni_pi;
6308 struct si_power_info *si_pi;
6309 struct atom_clock_dividers dividers;
6313 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6316 rdev->pm.dpm.priv = si_pi;
6321 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6323 si_pi->sys_pcie_mask = 0;
6325 si_pi->sys_pcie_mask = mask;
6326 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6327 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6329 si_set_max_cu_value(rdev);
6331 rv770_get_max_vddc(rdev);
6332 si_get_leakage_vddc(rdev);
6333 si_patch_dependency_tables_based_on_leakage(rdev);
6336 eg_pi->acpi_vddci = 0;
6337 pi->min_vddc_in_table = 0;
6338 pi->max_vddc_in_table = 0;
6340 ret = si_parse_power_table(rdev);
6343 ret = r600_parse_extended_power_table(rdev);
6347 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6348 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6349 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6350 r600_free_extended_power_table(rdev);
6353 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6354 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6355 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6356 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6357 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6358 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6359 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6360 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6361 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6363 if (rdev->pm.dpm.voltage_response_time == 0)
6364 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6365 if (rdev->pm.dpm.backbias_response_time == 0)
6366 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6368 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6369 0, false, ÷rs);
6371 pi->ref_div = dividers.ref_div + 1;
6373 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6375 eg_pi->smu_uvd_hs = false;
6377 pi->mclk_strobe_mode_threshold = 40000;
6378 if (si_is_special_1gb_platform(rdev))
6379 pi->mclk_stutter_mode_threshold = 0;
6381 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6382 pi->mclk_edc_enable_threshold = 40000;
6383 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6385 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6387 pi->voltage_control =
6388 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6391 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6393 eg_pi->vddci_control =
6394 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6396 si_pi->vddc_phase_shed_control =
6397 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6399 rv770_get_engine_memory_ss(rdev);
6401 pi->asi = RV770_ASI_DFLT;
6402 pi->pasi = CYPRESS_HASI_DFLT;
6403 pi->vrc = SISLANDS_VRC_DFLT;
6405 pi->gfx_clock_gating = true;
6407 eg_pi->sclk_deep_sleep = true;
6408 si_pi->sclk_deep_sleep_above_low = false;
6410 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6411 pi->thermal_protection = true;
6413 pi->thermal_protection = false;
6415 eg_pi->dynamic_ac_timing = true;
6417 eg_pi->light_sleep = true;
6418 #if defined(CONFIG_ACPI)
6419 eg_pi->pcie_performance_request =
6420 radeon_acpi_is_pcie_performance_request_supported(rdev);
6422 eg_pi->pcie_performance_request = false;
6425 si_pi->sram_end = SMC_RAM_END;
6427 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6428 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6429 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6430 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6431 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6432 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6433 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6435 si_initialize_powertune_defaults(rdev);
6437 /* make sure dc limits are valid */
6438 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6439 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6440 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6441 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6446 void si_dpm_fini(struct radeon_device *rdev)
6450 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6451 kfree(rdev->pm.dpm.ps[i].ps_priv);
6453 kfree(rdev->pm.dpm.ps);
6454 kfree(rdev->pm.dpm.priv);
6455 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6456 r600_free_extended_power_table(rdev);
6459 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6462 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6463 struct ni_ps *ps = ni_get_ps(rps);
6464 struct rv7xx_pl *pl;
6466 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6467 CURRENT_STATE_INDEX_SHIFT;
6469 if (current_index >= ps->performance_level_count) {
6470 seq_printf(m, "invalid dpm profile %d\n", current_index);
6472 pl = &ps->performance_levels[current_index];
6473 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6474 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6475 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);