drivers/gpu/drm/radeon/si.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include <drm/radeon_drm.h>
  32 #include "sid.h"
  33 #include "atom.h"
  34 #include "si_blit_shaders.h"
  35
  36 #define SI_PFP_UCODE_SIZE 2144
  37 #define SI_PM4_UCODE_SIZE 2144
  38 #define SI_CE_UCODE_SIZE 2144
  39 #define SI_RLC_UCODE_SIZE 2048
  40 #define SI_MC_UCODE_SIZE 7769
  41 #define OLAND_MC_UCODE_SIZE 7863
  42
  43 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
  44 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
  45 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
  46 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
  47 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
  48 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
  49 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
  50 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
  51 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
  52 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
  53 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
  54 MODULE_FIRMWARE("radeon/VERDE_me.bin");
  55 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
  56 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
  57 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
  58 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
  59 MODULE_FIRMWARE("radeon/OLAND_me.bin");
  60 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
  61 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
  62 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
  63
  64 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  65 extern void r600_ih_ring_fini(struct radeon_device *rdev);
  66 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  67 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  68 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  69 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
  70 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
  71 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
  72
  73 /* get temperature in millidegrees */
  74 int si_get_temp(struct radeon_device *rdev)
  75 {
  76         u32 temp;
  77         int actual_temp = 0;
  78
  79         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  80                 CTF_TEMP_SHIFT;
  81
  82         if (temp & 0x200)
  83                 actual_temp = 255;
  84         else
  85                 actual_temp = temp & 0x1ff;
  86
  87         actual_temp = (actual_temp * 1000);
  88
  89         return actual_temp;
  90 }
  91
  92 #define TAHITI_IO_MC_REGS_SIZE 36
  93
  94 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
  95         {0x0000006f, 0x03044000},
  96         {0x00000070, 0x0480c018},
  97         {0x00000071, 0x00000040},
  98         {0x00000072, 0x01000000},
  99         {0x00000074, 0x000000ff},
 100         {0x00000075, 0x00143400},
 101         {0x00000076, 0x08ec0800},
 102         {0x00000077, 0x040000cc},
 103         {0x00000079, 0x00000000},
 104         {0x0000007a, 0x21000409},
 105         {0x0000007c, 0x00000000},
 106         {0x0000007d, 0xe8000000},
 107         {0x0000007e, 0x044408a8},
 108         {0x0000007f, 0x00000003},
 109         {0x00000080, 0x00000000},
 110         {0x00000081, 0x01000000},
 111         {0x00000082, 0x02000000},
 112         {0x00000083, 0x00000000},
 113         {0x00000084, 0xe3f3e4f4},
 114         {0x00000085, 0x00052024},
 115         {0x00000087, 0x00000000},
 116         {0x00000088, 0x66036603},
 117         {0x00000089, 0x01000000},
 118         {0x0000008b, 0x1c0a0000},
 119         {0x0000008c, 0xff010000},
 120         {0x0000008e, 0xffffefff},
 121         {0x0000008f, 0xfff3efff},
 122         {0x00000090, 0xfff3efbf},
 123         {0x00000094, 0x00101101},
 124         {0x00000095, 0x00000fff},
 125         {0x00000096, 0x00116fff},
 126         {0x00000097, 0x60010000},
 127         {0x00000098, 0x10010000},
 128         {0x00000099, 0x00006000},
 129         {0x0000009a, 0x00001000},
 130         {0x0000009f, 0x00a77400}
 131 };
 132
 133 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 134         {0x0000006f, 0x03044000},
 135         {0x00000070, 0x0480c018},
 136         {0x00000071, 0x00000040},
 137         {0x00000072, 0x01000000},
 138         {0x00000074, 0x000000ff},
 139         {0x00000075, 0x00143400},
 140         {0x00000076, 0x08ec0800},
 141         {0x00000077, 0x040000cc},
 142         {0x00000079, 0x00000000},
 143         {0x0000007a, 0x21000409},
 144         {0x0000007c, 0x00000000},
 145         {0x0000007d, 0xe8000000},
 146         {0x0000007e, 0x044408a8},
 147         {0x0000007f, 0x00000003},
 148         {0x00000080, 0x00000000},
 149         {0x00000081, 0x01000000},
 150         {0x00000082, 0x02000000},
 151         {0x00000083, 0x00000000},
 152         {0x00000084, 0xe3f3e4f4},
 153         {0x00000085, 0x00052024},
 154         {0x00000087, 0x00000000},
 155         {0x00000088, 0x66036603},
 156         {0x00000089, 0x01000000},
 157         {0x0000008b, 0x1c0a0000},
 158         {0x0000008c, 0xff010000},
 159         {0x0000008e, 0xffffefff},
 160         {0x0000008f, 0xfff3efff},
 161         {0x00000090, 0xfff3efbf},
 162         {0x00000094, 0x00101101},
 163         {0x00000095, 0x00000fff},
 164         {0x00000096, 0x00116fff},
 165         {0x00000097, 0x60010000},
 166         {0x00000098, 0x10010000},
 167         {0x00000099, 0x00006000},
 168         {0x0000009a, 0x00001000},
 169         {0x0000009f, 0x00a47400}
 170 };
 171
 172 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 173         {0x0000006f, 0x03044000},
 174         {0x00000070, 0x0480c018},
 175         {0x00000071, 0x00000040},
 176         {0x00000072, 0x01000000},
 177         {0x00000074, 0x000000ff},
 178         {0x00000075, 0x00143400},
 179         {0x00000076, 0x08ec0800},
 180         {0x00000077, 0x040000cc},
 181         {0x00000079, 0x00000000},
 182         {0x0000007a, 0x21000409},
 183         {0x0000007c, 0x00000000},
 184         {0x0000007d, 0xe8000000},
 185         {0x0000007e, 0x044408a8},
 186         {0x0000007f, 0x00000003},
 187         {0x00000080, 0x00000000},
 188         {0x00000081, 0x01000000},
 189         {0x00000082, 0x02000000},
 190         {0x00000083, 0x00000000},
 191         {0x00000084, 0xe3f3e4f4},
 192         {0x00000085, 0x00052024},
 193         {0x00000087, 0x00000000},
 194         {0x00000088, 0x66036603},
 195         {0x00000089, 0x01000000},
 196         {0x0000008b, 0x1c0a0000},
 197         {0x0000008c, 0xff010000},
 198         {0x0000008e, 0xffffefff},
 199         {0x0000008f, 0xfff3efff},
 200         {0x00000090, 0xfff3efbf},
 201         {0x00000094, 0x00101101},
 202         {0x00000095, 0x00000fff},
 203         {0x00000096, 0x00116fff},
 204         {0x00000097, 0x60010000},
 205         {0x00000098, 0x10010000},
 206         {0x00000099, 0x00006000},
 207         {0x0000009a, 0x00001000},
 208         {0x0000009f, 0x00a37400}
 209 };
 210
 211 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
 212         {0x0000006f, 0x03044000},
 213         {0x00000070, 0x0480c018},
 214         {0x00000071, 0x00000040},
 215         {0x00000072, 0x01000000},
 216         {0x00000074, 0x000000ff},
 217         {0x00000075, 0x00143400},
 218         {0x00000076, 0x08ec0800},
 219         {0x00000077, 0x040000cc},
 220         {0x00000079, 0x00000000},
 221         {0x0000007a, 0x21000409},
 222         {0x0000007c, 0x00000000},
 223         {0x0000007d, 0xe8000000},
 224         {0x0000007e, 0x044408a8},
 225         {0x0000007f, 0x00000003},
 226         {0x00000080, 0x00000000},
 227         {0x00000081, 0x01000000},
 228         {0x00000082, 0x02000000},
 229         {0x00000083, 0x00000000},
 230         {0x00000084, 0xe3f3e4f4},
 231         {0x00000085, 0x00052024},
 232         {0x00000087, 0x00000000},
 233         {0x00000088, 0x66036603},
 234         {0x00000089, 0x01000000},
 235         {0x0000008b, 0x1c0a0000},
 236         {0x0000008c, 0xff010000},
 237         {0x0000008e, 0xffffefff},
 238         {0x0000008f, 0xfff3efff},
 239         {0x00000090, 0xfff3efbf},
 240         {0x00000094, 0x00101101},
 241         {0x00000095, 0x00000fff},
 242         {0x00000096, 0x00116fff},
 243         {0x00000097, 0x60010000},
 244         {0x00000098, 0x10010000},
 245         {0x00000099, 0x00006000},
 246         {0x0000009a, 0x00001000},
 247         {0x0000009f, 0x00a17730}
 248 };
 249
 250 /* ucode loading */
 251 static int si_mc_load_microcode(struct radeon_device *rdev)
 252 {
 253         const __be32 *fw_data;
 254         u32 running, blackout = 0;
 255         u32 *io_mc_regs;
 256         int i, ucode_size, regs_size;
 257
 258         if (!rdev->mc_fw)
 259                 return -EINVAL;
 260
 261         switch (rdev->family) {
 262         case CHIP_TAHITI:
 263                 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
 264                 ucode_size = SI_MC_UCODE_SIZE;
 265                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 266                 break;
 267         case CHIP_PITCAIRN:
 268                 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
 269                 ucode_size = SI_MC_UCODE_SIZE;
 270                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 271                 break;
 272         case CHIP_VERDE:
 273         default:
 274                 io_mc_regs = (u32 *)&verde_io_mc_regs;
 275                 ucode_size = SI_MC_UCODE_SIZE;
 276                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 277                 break;
 278         case CHIP_OLAND:
 279                 io_mc_regs = (u32 *)&oland_io_mc_regs;
 280                 ucode_size = OLAND_MC_UCODE_SIZE;
 281                 regs_size = TAHITI_IO_MC_REGS_SIZE;
 282                 break;
 283         }
 284
 285         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 286
 287         if (running == 0) {
 288                 if (running) {
 289                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 290                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 291                 }
 292
 293                 /* reset the engine and set to writable */
 294                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 295                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 296
 297                 /* load mc io regs */
 298                 for (i = 0; i < regs_size; i++) {
 299                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 300                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 301                 }
 302                 /* load the MC ucode */
 303                 fw_data = (const __be32 *)rdev->mc_fw->data;
 304                 for (i = 0; i < ucode_size; i++)
 305                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 306
 307                 /* put the engine back into the active state */
 308                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 309                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 310                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 311
 312                 /* wait for training to complete */
 313                 for (i = 0; i < rdev->usec_timeout; i++) {
 314                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
 315                                 break;
 316                         udelay(1);
 317                 }
 318                 for (i = 0; i < rdev->usec_timeout; i++) {
 319                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
 320                                 break;
 321                         udelay(1);
 322                 }
 323
 324                 if (running)
 325                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int si_init_microcode(struct radeon_device *rdev)
 332 {
 333         struct platform_device *pdev;
 334         const char *chip_name;
 335         const char *rlc_chip_name;
 336         size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
 337         char fw_name[30];
 338         int err;
 339
 340         DRM_DEBUG("\n");
 341
 342         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 343         err = IS_ERR(pdev);
 344         if (err) {
 345                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 346                 return -EINVAL;
 347         }
 348
 349         switch (rdev->family) {
 350         case CHIP_TAHITI:
 351                 chip_name = "TAHITI";
 352                 rlc_chip_name = "TAHITI";
 353                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 354                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 355                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 356                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 357                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 358                 break;
 359         case CHIP_PITCAIRN:
 360                 chip_name = "PITCAIRN";
 361                 rlc_chip_name = "PITCAIRN";
 362                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 363                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 364                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 365                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 366                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 367                 break;
 368         case CHIP_VERDE:
 369                 chip_name = "VERDE";
 370                 rlc_chip_name = "VERDE";
 371                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 372                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 373                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 374                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 375                 mc_req_size = SI_MC_UCODE_SIZE * 4;
 376                 break;
 377         case CHIP_OLAND:
 378                 chip_name = "OLAND";
 379                 rlc_chip_name = "OLAND";
 380                 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
 381                 me_req_size = SI_PM4_UCODE_SIZE * 4;
 382                 ce_req_size = SI_CE_UCODE_SIZE * 4;
 383                 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
 384                 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
 385                 break;
 386         default: BUG();
 387         }
 388
 389         DRM_INFO("Loading %s Microcode\n", chip_name);
 390
 391         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 392         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 393         if (err)
 394                 goto out;
 395         if (rdev->pfp_fw->size != pfp_req_size) {
 396                 printk(KERN_ERR
 397                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 398                        rdev->pfp_fw->size, fw_name);
 399                 err = -EINVAL;
 400                 goto out;
 401         }
 402
 403         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 404         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 405         if (err)
 406                 goto out;
 407         if (rdev->me_fw->size != me_req_size) {
 408                 printk(KERN_ERR
 409                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 410                        rdev->me_fw->size, fw_name);
 411                 err = -EINVAL;
 412         }
 413
 414         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 415         err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
 416         if (err)
 417                 goto out;
 418         if (rdev->ce_fw->size != ce_req_size) {
 419                 printk(KERN_ERR
 420                        "si_cp: Bogus length %zu in firmware \"%s\"\n",
 421                        rdev->ce_fw->size, fw_name);
 422                 err = -EINVAL;
 423         }
 424
 425         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 426         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 427         if (err)
 428                 goto out;
 429         if (rdev->rlc_fw->size != rlc_req_size) {
 430                 printk(KERN_ERR
 431                        "si_rlc: Bogus length %zu in firmware \"%s\"\n",
 432                        rdev->rlc_fw->size, fw_name);
 433                 err = -EINVAL;
 434         }
 435
 436         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 437         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 438         if (err)
 439                 goto out;
 440         if (rdev->mc_fw->size != mc_req_size) {
 441                 printk(KERN_ERR
 442                        "si_mc: Bogus length %zu in firmware \"%s\"\n",
 443                        rdev->mc_fw->size, fw_name);
 444                 err = -EINVAL;
 445         }
 446
 447 out:
 448         platform_device_unregister(pdev);
 449
 450         if (err) {
 451                 if (err != -EINVAL)
 452                         printk(KERN_ERR
 453                                "si_cp: Failed to load firmware \"%s\"\n",
 454                                fw_name);
 455                 release_firmware(rdev->pfp_fw);
 456                 rdev->pfp_fw = NULL;
 457                 release_firmware(rdev->me_fw);
 458                 rdev->me_fw = NULL;
 459                 release_firmware(rdev->ce_fw);
 460                 rdev->ce_fw = NULL;
 461                 release_firmware(rdev->rlc_fw);
 462                 rdev->rlc_fw = NULL;
 463                 release_firmware(rdev->mc_fw);
 464                 rdev->mc_fw = NULL;
 465         }
 466         return err;
 467 }
 468
 469 /* watermark setup */
 470 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
 471                                    struct radeon_crtc *radeon_crtc,
 472                                    struct drm_display_mode *mode,
 473                                    struct drm_display_mode *other_mode)
 474 {
 475         u32 tmp;
 476         /*
 477          * Line Buffer Setup
 478          * There are 3 line buffers, each one shared by 2 display controllers.
 479          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 480          * the display controllers.  The paritioning is done via one of four
 481          * preset allocations specified in bits 21:20:
 482          *  0 - half lb
 483          *  2 - whole lb, other crtc must be disabled
 484          */
 485         /* this can get tricky if we have two large displays on a paired group
 486          * of crtcs.  Ideally for multiple large displays we'd assign them to
 487          * non-linked crtcs for maximum line buffer allocation.
 488          */
 489         if (radeon_crtc->base.enabled && mode) {
 490                 if (other_mode)
 491                         tmp = 0; /* 1/2 */
 492                 else
 493                         tmp = 2; /* whole */
 494         } else
 495                 tmp = 0;
 496
 497         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
 498                DC_LB_MEMORY_CONFIG(tmp));
 499
 500         if (radeon_crtc->base.enabled && mode) {
 501                 switch (tmp) {
 502                 case 0:
 503                 default:
 504                         return 4096 * 2;
 505                 case 2:
 506                         return 8192 * 2;
 507                 }
 508         }
 509
 510         /* controller not enabled, so no lb used */
 511         return 0;
 512 }
 513
 514 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
 515 {
 516         u32 tmp = RREG32(MC_SHARED_CHMAP);
 517
 518         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 519         case 0:
 520         default:
 521                 return 1;
 522         case 1:
 523                 return 2;
 524         case 2:
 525                 return 4;
 526         case 3:
 527                 return 8;
 528         case 4:
 529                 return 3;
 530         case 5:
 531                 return 6;
 532         case 6:
 533                 return 10;
 534         case 7:
 535                 return 12;
 536         case 8:
 537                 return 16;
 538         }
 539 }
 540
 541 struct dce6_wm_params {
 542         u32 dram_channels; /* number of dram channels */
 543         u32 yclk;          /* bandwidth per dram data pin in kHz */
 544         u32 sclk;          /* engine clock in kHz */
 545         u32 disp_clk;      /* display clock in kHz */
 546         u32 src_width;     /* viewport width */
 547         u32 active_time;   /* active display time in ns */
 548         u32 blank_time;    /* blank time in ns */
 549         bool interlaced;    /* mode is interlaced */
 550         fixed20_12 vsc;    /* vertical scale ratio */
 551         u32 num_heads;     /* number of active crtcs */
 552         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 553         u32 lb_size;       /* line buffer allocated to pipe */
 554         u32 vtaps;         /* vertical scaler taps */
 555 };
 556
 557 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
 558 {
 559         /* Calculate raw DRAM Bandwidth */
 560         fixed20_12 dram_efficiency; /* 0.7 */
 561         fixed20_12 yclk, dram_channels, bandwidth;
 562         fixed20_12 a;
 563
 564         a.full = dfixed_const(1000);
 565         yclk.full = dfixed_const(wm->yclk);
 566         yclk.full = dfixed_div(yclk, a);
 567         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 568         a.full = dfixed_const(10);
 569         dram_efficiency.full = dfixed_const(7);
 570         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 571         bandwidth.full = dfixed_mul(dram_channels, yclk);
 572         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 573
 574         return dfixed_trunc(bandwidth);
 575 }
 576
 577 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 578 {
 579         /* Calculate DRAM Bandwidth and the part allocated to display. */
 580         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 581         fixed20_12 yclk, dram_channels, bandwidth;
 582         fixed20_12 a;
 583
 584         a.full = dfixed_const(1000);
 585         yclk.full = dfixed_const(wm->yclk);
 586         yclk.full = dfixed_div(yclk, a);
 587         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 588         a.full = dfixed_const(10);
 589         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 590         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 591         bandwidth.full = dfixed_mul(dram_channels, yclk);
 592         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 593
 594         return dfixed_trunc(bandwidth);
 595 }
 596
 597 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
 598 {
 599         /* Calculate the display Data return Bandwidth */
 600         fixed20_12 return_efficiency; /* 0.8 */
 601         fixed20_12 sclk, bandwidth;
 602         fixed20_12 a;
 603
 604         a.full = dfixed_const(1000);
 605         sclk.full = dfixed_const(wm->sclk);
 606         sclk.full = dfixed_div(sclk, a);
 607         a.full = dfixed_const(10);
 608         return_efficiency.full = dfixed_const(8);
 609         return_efficiency.full = dfixed_div(return_efficiency, a);
 610         a.full = dfixed_const(32);
 611         bandwidth.full = dfixed_mul(a, sclk);
 612         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 613
 614         return dfixed_trunc(bandwidth);
 615 }
 616
 617 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
 618 {
 619         return 32;
 620 }
 621
 622 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
 623 {
 624         /* Calculate the DMIF Request Bandwidth */
 625         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 626         fixed20_12 disp_clk, sclk, bandwidth;
 627         fixed20_12 a, b1, b2;
 628         u32 min_bandwidth;
 629
 630         a.full = dfixed_const(1000);
 631         disp_clk.full = dfixed_const(wm->disp_clk);
 632         disp_clk.full = dfixed_div(disp_clk, a);
 633         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
 634         b1.full = dfixed_mul(a, disp_clk);
 635
 636         a.full = dfixed_const(1000);
 637         sclk.full = dfixed_const(wm->sclk);
 638         sclk.full = dfixed_div(sclk, a);
 639         a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
 640         b2.full = dfixed_mul(a, sclk);
 641
 642         a.full = dfixed_const(10);
 643         disp_clk_request_efficiency.full = dfixed_const(8);
 644         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 645
 646         min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
 647
 648         a.full = dfixed_const(min_bandwidth);
 649         bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
 650
 651         return dfixed_trunc(bandwidth);
 652 }
 653
 654 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
 655 {
 656         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 657         u32 dram_bandwidth = dce6_dram_bandwidth(wm);
 658         u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
 659         u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
 660
 661         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 662 }
 663
 664 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
 665 {
 666         /* Calculate the display mode Average Bandwidth
 667          * DisplayMode should contain the source and destination dimensions,
 668          * timing, etc.
 669          */
 670         fixed20_12 bpp;
 671         fixed20_12 line_time;
 672         fixed20_12 src_width;
 673         fixed20_12 bandwidth;
 674         fixed20_12 a;
 675
 676         a.full = dfixed_const(1000);
 677         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 678         line_time.full = dfixed_div(line_time, a);
 679         bpp.full = dfixed_const(wm->bytes_per_pixel);
 680         src_width.full = dfixed_const(wm->src_width);
 681         bandwidth.full = dfixed_mul(src_width, bpp);
 682         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 683         bandwidth.full = dfixed_div(bandwidth, line_time);
 684
 685         return dfixed_trunc(bandwidth);
 686 }
 687
 688 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
 689 {
 690         /* First calcualte the latency in ns */
 691         u32 mc_latency = 2000; /* 2000 ns. */
 692         u32 available_bandwidth = dce6_available_bandwidth(wm);
 693         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 694         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 695         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 696         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 697                 (wm->num_heads * cursor_line_pair_return_time);
 698         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 699         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 700         u32 tmp, dmif_size = 12288;
 701         fixed20_12 a, b, c;
 702
 703         if (wm->num_heads == 0)
 704                 return 0;
 705
 706         a.full = dfixed_const(2);
 707         b.full = dfixed_const(1);
 708         if ((wm->vsc.full > a.full) ||
 709             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 710             (wm->vtaps >= 5) ||
 711             ((wm->vsc.full >= a.full) && wm->interlaced))
 712                 max_src_lines_per_dst_line = 4;
 713         else
 714                 max_src_lines_per_dst_line = 2;
 715
 716         a.full = dfixed_const(available_bandwidth);
 717         b.full = dfixed_const(wm->num_heads);
 718         a.full = dfixed_div(a, b);
 719
 720         b.full = dfixed_const(mc_latency + 512);
 721         c.full = dfixed_const(wm->disp_clk);
 722         b.full = dfixed_div(b, c);
 723
 724         c.full = dfixed_const(dmif_size);
 725         b.full = dfixed_div(c, b);
 726
 727         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
 728
 729         b.full = dfixed_const(1000);
 730         c.full = dfixed_const(wm->disp_clk);
 731         b.full = dfixed_div(c, b);
 732         c.full = dfixed_const(wm->bytes_per_pixel);
 733         b.full = dfixed_mul(b, c);
 734
 735         lb_fill_bw = min(tmp, dfixed_trunc(b));
 736
 737         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 738         b.full = dfixed_const(1000);
 739         c.full = dfixed_const(lb_fill_bw);
 740         b.full = dfixed_div(c, b);
 741         a.full = dfixed_div(a, b);
 742         line_fill_time = dfixed_trunc(a);
 743
 744         if (line_fill_time < wm->active_time)
 745                 return latency;
 746         else
 747                 return latency + (line_fill_time - wm->active_time);
 748
 749 }
 750
 751 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
 752 {
 753         if (dce6_average_bandwidth(wm) <=
 754             (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
 755                 return true;
 756         else
 757                 return false;
 758 };
 759
 760 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
 761 {
 762         if (dce6_average_bandwidth(wm) <=
 763             (dce6_available_bandwidth(wm) / wm->num_heads))
 764                 return true;
 765         else
 766                 return false;
 767 };
 768
 769 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
 770 {
 771         u32 lb_partitions = wm->lb_size / wm->src_width;
 772         u32 line_time = wm->active_time + wm->blank_time;
 773         u32 latency_tolerant_lines;
 774         u32 latency_hiding;
 775         fixed20_12 a;
 776
 777         a.full = dfixed_const(1);
 778         if (wm->vsc.full > a.full)
 779                 latency_tolerant_lines = 1;
 780         else {
 781                 if (lb_partitions <= (wm->vtaps + 1))
 782                         latency_tolerant_lines = 1;
 783                 else
 784                         latency_tolerant_lines = 2;
 785         }
 786
 787         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 788
 789         if (dce6_latency_watermark(wm) <= latency_hiding)
 790                 return true;
 791         else
 792                 return false;
 793 }
 794
 795 static void dce6_program_watermarks(struct radeon_device *rdev,
 796                                          struct radeon_crtc *radeon_crtc,
 797                                          u32 lb_size, u32 num_heads)
 798 {
 799         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 800         struct dce6_wm_params wm;
 801         u32 pixel_period;
 802         u32 line_time = 0;
 803         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 804         u32 priority_a_mark = 0, priority_b_mark = 0;
 805         u32 priority_a_cnt = PRIORITY_OFF;
 806         u32 priority_b_cnt = PRIORITY_OFF;
 807         u32 tmp, arb_control3;
 808         fixed20_12 a, b, c;
 809
 810         if (radeon_crtc->base.enabled && num_heads && mode) {
 811                 pixel_period = 1000000 / (u32)mode->clock;
 812                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 813                 priority_a_cnt = 0;
 814                 priority_b_cnt = 0;
 815
 816                 wm.yclk = rdev->pm.current_mclk * 10;
 817                 wm.sclk = rdev->pm.current_sclk * 10;
 818                 wm.disp_clk = mode->clock;
 819                 wm.src_width = mode->crtc_hdisplay;
 820                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 821                 wm.blank_time = line_time - wm.active_time;
 822                 wm.interlaced = false;
 823                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 824                         wm.interlaced = true;
 825                 wm.vsc = radeon_crtc->vsc;
 826                 wm.vtaps = 1;
 827                 if (radeon_crtc->rmx_type != RMX_OFF)
 828                         wm.vtaps = 2;
 829                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 830                 wm.lb_size = lb_size;
 831                 if (rdev->family == CHIP_ARUBA)
 832                         wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 833                 else
 834                         wm.dram_channels = si_get_number_of_dram_channels(rdev);
 835                 wm.num_heads = num_heads;
 836
 837                 /* set for high clocks */
 838                 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
 839                 /* set for low clocks */
 840                 /* wm.yclk = low clk; wm.sclk = low clk */
 841                 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
 842
 843                 /* possibly force display priority to high */
 844                 /* should really do this at mode validation time... */
 845                 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 846                     !dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
 847                     !dce6_check_latency_hiding(&wm) ||
 848                     (rdev->disp_priority == 2)) {
 849                         DRM_DEBUG_KMS("force priority to high\n");
 850                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 851                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 852                 }
 853
 854                 a.full = dfixed_const(1000);
 855                 b.full = dfixed_const(mode->clock);
 856                 b.full = dfixed_div(b, a);
 857                 c.full = dfixed_const(latency_watermark_a);
 858                 c.full = dfixed_mul(c, b);
 859                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 860                 c.full = dfixed_div(c, a);
 861                 a.full = dfixed_const(16);
 862                 c.full = dfixed_div(c, a);
 863                 priority_a_mark = dfixed_trunc(c);
 864                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 865
 866                 a.full = dfixed_const(1000);
 867                 b.full = dfixed_const(mode->clock);
 868                 b.full = dfixed_div(b, a);
 869                 c.full = dfixed_const(latency_watermark_b);
 870                 c.full = dfixed_mul(c, b);
 871                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 872                 c.full = dfixed_div(c, a);
 873                 a.full = dfixed_const(16);
 874                 c.full = dfixed_div(c, a);
 875                 priority_b_mark = dfixed_trunc(c);
 876                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 877         }
 878
 879         /* select wm A */
 880         arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 881         tmp = arb_control3;
 882         tmp &= ~LATENCY_WATERMARK_MASK(3);
 883         tmp |= LATENCY_WATERMARK_MASK(1);
 884         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 885         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 886                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 887                 LATENCY_HIGH_WATERMARK(line_time)));
 888         /* select wm B */
 889         tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
 890         tmp &= ~LATENCY_WATERMARK_MASK(3);
 891         tmp |= LATENCY_WATERMARK_MASK(2);
 892         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
 893         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
 894                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 895                 LATENCY_HIGH_WATERMARK(line_time)));
 896         /* restore original selection */
 897         WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
 898
 899         /* write the priority marks */
 900         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 901         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 902
 903 }
 904
 905 void dce6_bandwidth_update(struct radeon_device *rdev)
 906 {
 907         struct drm_display_mode *mode0 = NULL;
 908         struct drm_display_mode *mode1 = NULL;
 909         u32 num_heads = 0, lb_size;
 910         int i;
 911
 912         radeon_update_display_priority(rdev);
 913
 914         for (i = 0; i < rdev->num_crtc; i++) {
 915                 if (rdev->mode_info.crtcs[i]->base.enabled)
 916                         num_heads++;
 917         }
 918         for (i = 0; i < rdev->num_crtc; i += 2) {
 919                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 920                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 921                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 922                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 923                 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 924                 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 925         }
 926 }
 927
 928 /*
 929  * Core functions
 930  */
 931 static void si_tiling_mode_table_init(struct radeon_device *rdev)
 932 {
 933         const u32 num_tile_mode_states = 32;
 934         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 935
 936         switch (rdev->config.si.mem_row_size_in_kb) {
 937         case 1:
 938                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 939                 break;
 940         case 2:
 941         default:
 942                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 943                 break;
 944         case 4:
 945                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 946                 break;
 947         }
 948
 949         if ((rdev->family == CHIP_TAHITI) ||
 950             (rdev->family == CHIP_PITCAIRN)) {
 951                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 952                         switch (reg_offset) {
 953                         case 0:  /* non-AA compressed depth or any compressed stencil */
 954                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 955                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 956                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 957                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 958                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 959                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 960                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 961                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 962                                 break;
 963                         case 1:  /* 2xAA/4xAA compressed depth only */
 964                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 965                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 966                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 967                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 968                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 969                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 970                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 971                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 972                                 break;
 973                         case 2:  /* 8xAA compressed depth only */
 974                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 975                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 976                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 977                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 978                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 979                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 980                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 981                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 982                                 break;
 983                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
 984                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 985                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 986                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 987                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 988                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 989                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 990                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 991                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 992                                 break;
 993                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
 994                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 995                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 996                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 997                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 998                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
 999                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1000                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1001                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1002                                 break;
1003                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1004                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1005                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1006                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1007                                                  TILE_SPLIT(split_equal_to_row_size) |
1008                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1009                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1010                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1011                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1012                                 break;
1013                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1014                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1015                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1016                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1017                                                  TILE_SPLIT(split_equal_to_row_size) |
1018                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1019                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1020                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1021                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1022                                 break;
1023                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1024                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1025                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1026                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1027                                                  TILE_SPLIT(split_equal_to_row_size) |
1028                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1029                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1030                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1031                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1032                                 break;
1033                         case 8:  /* 1D and 1D Array Surfaces */
1034                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1035                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1036                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1037                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1038                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1039                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1040                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1041                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1042                                 break;
1043                         case 9:  /* Displayable maps. */
1044                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1045                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1046                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1047                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1048                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1049                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1050                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1051                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1052                                 break;
1053                         case 10:  /* Display 8bpp. */
1054                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1055                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1056                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1057                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1058                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1059                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1060                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1061                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1062                                 break;
1063                         case 11:  /* Display 16bpp. */
1064                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1065                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1066                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1067                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1068                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1069                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1070                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1071                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1072                                 break;
1073                         case 12:  /* Display 32bpp. */
1074                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1076                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1077                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1078                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1079                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1081                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1082                                 break;
1083                         case 13:  /* Thin. */
1084                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1086                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1087                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1088                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1089                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1090                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1091                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1092                                 break;
1093                         case 14:  /* Thin 8 bpp. */
1094                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1095                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1096                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1097                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1098                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1099                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1100                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1101                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1102                                 break;
1103                         case 15:  /* Thin 16 bpp. */
1104                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1105                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1106                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1107                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1108                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1109                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1110                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1111                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1112                                 break;
1113                         case 16:  /* Thin 32 bpp. */
1114                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1115                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1116                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1117                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1118                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1119                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1120                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1121                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1122                                 break;
1123                         case 17:  /* Thin 64 bpp. */
1124                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1125                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1126                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1127                                                  TILE_SPLIT(split_equal_to_row_size) |
1128                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1129                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1130                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1131                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1132                                 break;
1133                         case 21:  /* 8 bpp PRT. */
1134                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1135                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1136                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1137                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1138                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1139                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1140                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1141                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1142                                 break;
1143                         case 22:  /* 16 bpp PRT */
1144                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1146                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1147                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1148                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1149                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1150                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1151                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1152                                 break;
1153                         case 23:  /* 32 bpp PRT */
1154                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1155                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1156                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1157                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1158                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1159                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1161                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1162                                 break;
1163                         case 24:  /* 64 bpp PRT */
1164                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1166                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1167                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1168                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1169                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1172                                 break;
1173                         case 25:  /* 128 bpp PRT */
1174                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1175                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1176                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1177                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1178                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1179                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1182                                 break;
1183                         default:
1184                                 gb_tile_moden = 0;
1185                                 break;
1186                         }
1187                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1188                 }
1189         } else if ((rdev->family == CHIP_VERDE) ||
1190                    (rdev->family == CHIP_OLAND)) {
1191                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1192                         switch (reg_offset) {
1193                         case 0:  /* non-AA compressed depth or any compressed stencil */
1194                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1196                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1197                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1198                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1199                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1201                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1202                                 break;
1203                         case 1:  /* 2xAA/4xAA compressed depth only */
1204                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1206                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1207                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1208                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1209                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1211                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1212                                 break;
1213                         case 2:  /* 8xAA compressed depth only */
1214                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1215                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1216                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1217                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1218                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1219                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1221                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1222                                 break;
1223                         case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
1224                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1226                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1227                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1228                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1229                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1232                                 break;
1233                         case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
1234                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1235                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1236                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1237                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1238                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1239                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1240                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1241                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1242                                 break;
1243                         case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
1244                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1245                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1246                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1247                                                  TILE_SPLIT(split_equal_to_row_size) |
1248                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1249                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1250                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1251                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1252                                 break;
1253                         case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
1254                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1255                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1256                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257                                                  TILE_SPLIT(split_equal_to_row_size) |
1258                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1259                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1261                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1262                                 break;
1263                         case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
1264                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1265                                                  MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1266                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267                                                  TILE_SPLIT(split_equal_to_row_size) |
1268                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1269                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1271                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1272                                 break;
1273                         case 8:  /* 1D and 1D Array Surfaces */
1274                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1275                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1276                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1277                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1278                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1279                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1280                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1281                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1282                                 break;
1283                         case 9:  /* Displayable maps. */
1284                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1285                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1286                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1287                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1288                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1289                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1290                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1291                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1292                                 break;
1293                         case 10:  /* Display 8bpp. */
1294                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1295                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1296                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1297                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1298                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1299                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1300                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1301                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1302                                 break;
1303                         case 11:  /* Display 16bpp. */
1304                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1305                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1306                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1307                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1308                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1309                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1310                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1311                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1312                                 break;
1313                         case 12:  /* Display 32bpp. */
1314                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1315                                                  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1316                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1317                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1318                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1319                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1320                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1321                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1322                                 break;
1323                         case 13:  /* Thin. */
1324                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1325                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1326                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1327                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1328                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1329                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1330                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1331                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1332                                 break;
1333                         case 14:  /* Thin 8 bpp. */
1334                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1335                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1336                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1337                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1338                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1339                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1342                                 break;
1343                         case 15:  /* Thin 16 bpp. */
1344                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1345                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1346                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1347                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1348                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1349                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1351                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1352                                 break;
1353                         case 16:  /* Thin 32 bpp. */
1354                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1356                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1357                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1358                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1359                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1362                                 break;
1363                         case 17:  /* Thin 64 bpp. */
1364                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1365                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1366                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1367                                                  TILE_SPLIT(split_equal_to_row_size) |
1368                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1369                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1370                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1371                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1372                                 break;
1373                         case 21:  /* 8 bpp PRT. */
1374                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1375                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1376                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1377                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1378                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1379                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1380                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1381                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1382                                 break;
1383                         case 22:  /* 16 bpp PRT */
1384                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1385                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1386                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1387                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1388                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1389                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1390                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1391                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
1392                                 break;
1393                         case 23:  /* 32 bpp PRT */
1394                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1396                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1397                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1398                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1399                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1400                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1401                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1402                                 break;
1403                         case 24:  /* 64 bpp PRT */
1404                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1405                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1406                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1407                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1408                                                  NUM_BANKS(ADDR_SURF_16_BANK) |
1409                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1410                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1411                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
1412                                 break;
1413                         case 25:  /* 128 bpp PRT */
1414                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415                                                  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1416                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1417                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1418                                                  NUM_BANKS(ADDR_SURF_8_BANK) |
1419                                                  BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1420                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1421                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
1422                                 break;
1423                         default:
1424                                 gb_tile_moden = 0;
1425                                 break;
1426                         }
1427                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1428                 }
1429         } else
1430                 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1431 }
1432
1433 static void si_select_se_sh(struct radeon_device *rdev,
1434                             u32 se_num, u32 sh_num)
1435 {
1436         u32 data = INSTANCE_BROADCAST_WRITES;
1437
1438         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1439                 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1440         else if (se_num == 0xffffffff)
1441                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1442         else if (sh_num == 0xffffffff)
1443                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1444         else
1445                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1446         WREG32(GRBM_GFX_INDEX, data);
1447 }
1448
1449 static u32 si_create_bitmask(u32 bit_width)
1450 {
1451         u32 i, mask = 0;
1452
1453         for (i = 0; i < bit_width; i++) {
1454                 mask <<= 1;
1455                 mask |= 1;
1456         }
1457         return mask;
1458 }
1459
1460 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1461 {
1462         u32 data, mask;
1463
1464         data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1465         if (data & 1)
1466                 data &= INACTIVE_CUS_MASK;
1467         else
1468                 data = 0;
1469         data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1470
1471         data >>= INACTIVE_CUS_SHIFT;
1472
1473         mask = si_create_bitmask(cu_per_sh);
1474
1475         return ~data & mask;
1476 }
1477
1478 static void si_setup_spi(struct radeon_device *rdev,
1479                          u32 se_num, u32 sh_per_se,
1480                          u32 cu_per_sh)
1481 {
1482         int i, j, k;
1483         u32 data, mask, active_cu;
1484
1485         for (i = 0; i < se_num; i++) {
1486                 for (j = 0; j < sh_per_se; j++) {
1487                         si_select_se_sh(rdev, i, j);
1488                         data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1489                         active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1490
1491                         mask = 1;
1492                         for (k = 0; k < 16; k++) {
1493                                 mask <<= k;
1494                                 if (active_cu & mask) {
1495                                         data &= ~mask;
1496                                         WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1497                                         break;
1498                                 }
1499                         }
1500                 }
1501         }
1502         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1503 }
1504
1505 static u32 si_get_rb_disabled(struct radeon_device *rdev,
1506                               u32 max_rb_num, u32 se_num,
1507                               u32 sh_per_se)
1508 {
1509         u32 data, mask;
1510
1511         data = RREG32(CC_RB_BACKEND_DISABLE);
1512         if (data & 1)
1513                 data &= BACKEND_DISABLE_MASK;
1514         else
1515                 data = 0;
1516         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1517
1518         data >>= BACKEND_DISABLE_SHIFT;
1519
1520         mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1521
1522         return data & mask;
1523 }
1524
1525 static void si_setup_rb(struct radeon_device *rdev,
1526                         u32 se_num, u32 sh_per_se,
1527                         u32 max_rb_num)
1528 {
1529         int i, j;
1530         u32 data, mask;
1531         u32 disabled_rbs = 0;
1532         u32 enabled_rbs = 0;
1533
1534         for (i = 0; i < se_num; i++) {
1535                 for (j = 0; j < sh_per_se; j++) {
1536                         si_select_se_sh(rdev, i, j);
1537                         data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1538                         disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1539                 }
1540         }
1541         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1542
1543         mask = 1;
1544         for (i = 0; i < max_rb_num; i++) {
1545                 if (!(disabled_rbs & mask))
1546                         enabled_rbs |= mask;
1547                 mask <<= 1;
1548         }
1549
1550         for (i = 0; i < se_num; i++) {
1551                 si_select_se_sh(rdev, i, 0xffffffff);
1552                 data = 0;
1553                 for (j = 0; j < sh_per_se; j++) {
1554                         switch (enabled_rbs & 3) {
1555                         case 1:
1556                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1557                                 break;
1558                         case 2:
1559                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1560                                 break;
1561                         case 3:
1562                         default:
1563                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1564                                 break;
1565                         }
1566                         enabled_rbs >>= 2;
1567                 }
1568                 WREG32(PA_SC_RASTER_CONFIG, data);
1569         }
1570         si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1571 }
1572
1573 static void si_gpu_init(struct radeon_device *rdev)
1574 {
1575         u32 gb_addr_config = 0;
1576         u32 mc_shared_chmap, mc_arb_ramcfg;
1577         u32 sx_debug_1;
1578         u32 hdp_host_path_cntl;
1579         u32 tmp;
1580         int i, j;
1581
1582         switch (rdev->family) {
1583         case CHIP_TAHITI:
1584                 rdev->config.si.max_shader_engines = 2;
1585                 rdev->config.si.max_tile_pipes = 12;
1586                 rdev->config.si.max_cu_per_sh = 8;
1587                 rdev->config.si.max_sh_per_se = 2;
1588                 rdev->config.si.max_backends_per_se = 4;
1589                 rdev->config.si.max_texture_channel_caches = 12;
1590                 rdev->config.si.max_gprs = 256;
1591                 rdev->config.si.max_gs_threads = 32;
1592                 rdev->config.si.max_hw_contexts = 8;
1593
1594                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1595                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1596                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1597                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1598                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1599                 break;
1600         case CHIP_PITCAIRN:
1601                 rdev->config.si.max_shader_engines = 2;
1602                 rdev->config.si.max_tile_pipes = 8;
1603                 rdev->config.si.max_cu_per_sh = 5;
1604                 rdev->config.si.max_sh_per_se = 2;
1605                 rdev->config.si.max_backends_per_se = 4;
1606                 rdev->config.si.max_texture_channel_caches = 8;
1607                 rdev->config.si.max_gprs = 256;
1608                 rdev->config.si.max_gs_threads = 32;
1609                 rdev->config.si.max_hw_contexts = 8;
1610
1611                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1612                 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1613                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1614                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1615                 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1616                 break;
1617         case CHIP_VERDE:
1618         default:
1619                 rdev->config.si.max_shader_engines = 1;
1620                 rdev->config.si.max_tile_pipes = 4;
1621                 rdev->config.si.max_cu_per_sh = 2;
1622                 rdev->config.si.max_sh_per_se = 2;
1623                 rdev->config.si.max_backends_per_se = 4;
1624                 rdev->config.si.max_texture_channel_caches = 4;
1625                 rdev->config.si.max_gprs = 256;
1626                 rdev->config.si.max_gs_threads = 32;
1627                 rdev->config.si.max_hw_contexts = 8;
1628
1629                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1630                 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1631                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1632                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1633                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1634                 break;
1635         case CHIP_OLAND:
1636                 rdev->config.si.max_shader_engines = 1;
1637                 rdev->config.si.max_tile_pipes = 4;
1638                 rdev->config.si.max_cu_per_sh = 6;
1639                 rdev->config.si.max_sh_per_se = 1;
1640                 rdev->config.si.max_backends_per_se = 2;
1641                 rdev->config.si.max_texture_channel_caches = 4;
1642                 rdev->config.si.max_gprs = 256;
1643                 rdev->config.si.max_gs_threads = 16;
1644                 rdev->config.si.max_hw_contexts = 8;
1645
1646                 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1647                 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1648                 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1649                 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1650                 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1651                 break;
1652         }
1653
1654         /* Initialize HDP */
1655         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1656                 WREG32((0x2c14 + j), 0x00000000);
1657                 WREG32((0x2c18 + j), 0x00000000);
1658                 WREG32((0x2c1c + j), 0x00000000);
1659                 WREG32((0x2c20 + j), 0x00000000);
1660                 WREG32((0x2c24 + j), 0x00000000);
1661         }
1662
1663         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1664
1665         evergreen_fix_pci_max_read_req_size(rdev);
1666
1667         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1668
1669         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1670         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1671
1672         rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1673         rdev->config.si.mem_max_burst_length_bytes = 256;
1674         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1675         rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1676         if (rdev->config.si.mem_row_size_in_kb > 4)
1677                 rdev->config.si.mem_row_size_in_kb = 4;
1678         /* XXX use MC settings? */
1679         rdev->config.si.shader_engine_tile_size = 32;
1680         rdev->config.si.num_gpus = 1;
1681         rdev->config.si.multi_gpu_tile_size = 64;
1682
1683         /* fix up row size */
1684         gb_addr_config &= ~ROW_SIZE_MASK;
1685         switch (rdev->config.si.mem_row_size_in_kb) {
1686         case 1:
1687         default:
1688                 gb_addr_config |= ROW_SIZE(0);
1689                 break;
1690         case 2:
1691                 gb_addr_config |= ROW_SIZE(1);
1692                 break;
1693         case 4:
1694                 gb_addr_config |= ROW_SIZE(2);
1695                 break;
1696         }
1697
1698         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1699          * not have bank info, so create a custom tiling dword.
1700          * bits 3:0   num_pipes
1701          * bits 7:4   num_banks
1702          * bits 11:8  group_size
1703          * bits 15:12 row_size
1704          */
1705         rdev->config.si.tile_config = 0;
1706         switch (rdev->config.si.num_tile_pipes) {
1707         case 1:
1708                 rdev->config.si.tile_config |= (0 << 0);
1709                 break;
1710         case 2:
1711                 rdev->config.si.tile_config |= (1 << 0);
1712                 break;
1713         case 4:
1714                 rdev->config.si.tile_config |= (2 << 0);
1715                 break;
1716         case 8:
1717         default:
1718                 /* XXX what about 12? */
1719                 rdev->config.si.tile_config |= (3 << 0);
1720                 break;
1721         }
1722         switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1723         case 0: /* four banks */
1724                 rdev->config.si.tile_config |= 0 << 4;
1725                 break;
1726         case 1: /* eight banks */
1727                 rdev->config.si.tile_config |= 1 << 4;
1728                 break;
1729         case 2: /* sixteen banks */
1730         default:
1731                 rdev->config.si.tile_config |= 2 << 4;
1732                 break;
1733         }
1734         rdev->config.si.tile_config |=
1735                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1736         rdev->config.si.tile_config |=
1737                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1738
1739         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1740         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1741         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1742         WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1743         WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1744
1745         si_tiling_mode_table_init(rdev);
1746
1747         si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1748                     rdev->config.si.max_sh_per_se,
1749                     rdev->config.si.max_backends_per_se);
1750
1751         si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1752                      rdev->config.si.max_sh_per_se,
1753                      rdev->config.si.max_cu_per_sh);
1754
1755
1756         /* set HW defaults for 3D engine */
1757         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1758                                      ROQ_IB2_START(0x2b)));
1759         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1760
1761         sx_debug_1 = RREG32(SX_DEBUG_1);
1762         WREG32(SX_DEBUG_1, sx_debug_1);
1763
1764         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1765
1766         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
1767                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
1768                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
1769                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
1770
1771         WREG32(VGT_NUM_INSTANCES, 1);
1772
1773         WREG32(CP_PERFMON_CNTL, 0);
1774
1775         WREG32(SQ_CONFIG, 0);
1776
1777         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1778                                           FORCE_EOV_MAX_REZ_CNT(255)));
1779
1780         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1781                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1782
1783         WREG32(VGT_GS_VERTEX_REUSE, 16);
1784         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1785
1786         WREG32(CB_PERFCOUNTER0_SELECT0, 0);
1787         WREG32(CB_PERFCOUNTER0_SELECT1, 0);
1788         WREG32(CB_PERFCOUNTER1_SELECT0, 0);
1789         WREG32(CB_PERFCOUNTER1_SELECT1, 0);
1790         WREG32(CB_PERFCOUNTER2_SELECT0, 0);
1791         WREG32(CB_PERFCOUNTER2_SELECT1, 0);
1792         WREG32(CB_PERFCOUNTER3_SELECT0, 0);
1793         WREG32(CB_PERFCOUNTER3_SELECT1, 0);
1794
1795         tmp = RREG32(HDP_MISC_CNTL);
1796         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1797         WREG32(HDP_MISC_CNTL, tmp);
1798
1799         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1800         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1801
1802         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1803
1804         udelay(50);
1805 }
1806
1807 /*
1808  * GPU scratch registers helpers function.
1809  */
1810 static void si_scratch_init(struct radeon_device *rdev)
1811 {
1812         int i;
1813
1814         rdev->scratch.num_reg = 7;
1815         rdev->scratch.reg_base = SCRATCH_REG0;
1816         for (i = 0; i < rdev->scratch.num_reg; i++) {
1817                 rdev->scratch.free[i] = true;
1818                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1819         }
1820 }
1821
1822 void si_fence_ring_emit(struct radeon_device *rdev,
1823                         struct radeon_fence *fence)
1824 {
1825         struct radeon_ring *ring = &rdev->ring[fence->ring];
1826         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1827
1828         /* flush read cache over gart */
1829         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1830         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1831         radeon_ring_write(ring, 0);
1832         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1833         radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1834                           PACKET3_TC_ACTION_ENA |
1835                           PACKET3_SH_KCACHE_ACTION_ENA |
1836                           PACKET3_SH_ICACHE_ACTION_ENA);
1837         radeon_ring_write(ring, 0xFFFFFFFF);
1838         radeon_ring_write(ring, 0);
1839         radeon_ring_write(ring, 10); /* poll interval */
1840         /* EVENT_WRITE_EOP - flush caches, send int */
1841         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1842         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1843         radeon_ring_write(ring, addr & 0xffffffff);
1844         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1845         radeon_ring_write(ring, fence->seq);
1846         radeon_ring_write(ring, 0);
1847 }
1848
1849 /*
1850  * IB stuff
1851  */
1852 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1853 {
1854         struct radeon_ring *ring = &rdev->ring[ib->ring];
1855         u32 header;
1856
1857         if (ib->is_const_ib) {
1858                 /* set switch buffer packet before const IB */
1859                 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1860                 radeon_ring_write(ring, 0);
1861
1862                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1863         } else {
1864                 u32 next_rptr;
1865                 if (ring->rptr_save_reg) {
1866                         next_rptr = ring->wptr + 3 + 4 + 8;
1867                         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1868                         radeon_ring_write(ring, ((ring->rptr_save_reg -
1869                                                   PACKET3_SET_CONFIG_REG_START) >> 2));
1870                         radeon_ring_write(ring, next_rptr);
1871                 } else if (rdev->wb.enabled) {
1872                         next_rptr = ring->wptr + 5 + 4 + 8;
1873                         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1874                         radeon_ring_write(ring, (1 << 8));
1875                         radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1876                         radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1877                         radeon_ring_write(ring, next_rptr);
1878                 }
1879
1880                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1881         }
1882
1883         radeon_ring_write(ring, header);
1884         radeon_ring_write(ring,
1885 #ifdef __BIG_ENDIAN
1886                           (2 << 0) |
1887 #endif
1888                           (ib->gpu_addr & 0xFFFFFFFC));
1889         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1890         radeon_ring_write(ring, ib->length_dw |
1891                           (ib->vm ? (ib->vm->id << 24) : 0));
1892
1893         if (!ib->is_const_ib) {
1894                 /* flush read cache over gart for this vmid */
1895                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1896                 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1897                 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
1898                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1899                 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1900                                   PACKET3_TC_ACTION_ENA |
1901                                   PACKET3_SH_KCACHE_ACTION_ENA |
1902                                   PACKET3_SH_ICACHE_ACTION_ENA);
1903                 radeon_ring_write(ring, 0xFFFFFFFF);
1904                 radeon_ring_write(ring, 0);
1905                 radeon_ring_write(ring, 10); /* poll interval */
1906         }
1907 }
1908
1909 /*
1910  * CP.
1911  */
1912 static void si_cp_enable(struct radeon_device *rdev, bool enable)
1913 {
1914         if (enable)
1915                 WREG32(CP_ME_CNTL, 0);
1916         else {
1917                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1918                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1919                 WREG32(SCRATCH_UMSK, 0);
1920                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1921                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1922                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1923         }
1924         udelay(50);
1925 }
1926
1927 static int si_cp_load_microcode(struct radeon_device *rdev)
1928 {
1929         const __be32 *fw_data;
1930         int i;
1931
1932         if (!rdev->me_fw || !rdev->pfp_fw)
1933                 return -EINVAL;
1934
1935         si_cp_enable(rdev, false);
1936
1937         /* PFP */
1938         fw_data = (const __be32 *)rdev->pfp_fw->data;
1939         WREG32(CP_PFP_UCODE_ADDR, 0);
1940         for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
1941                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1942         WREG32(CP_PFP_UCODE_ADDR, 0);
1943
1944         /* CE */
1945         fw_data = (const __be32 *)rdev->ce_fw->data;
1946         WREG32(CP_CE_UCODE_ADDR, 0);
1947         for (i = 0; i < SI_CE_UCODE_SIZE; i++)
1948                 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1949         WREG32(CP_CE_UCODE_ADDR, 0);
1950
1951         /* ME */
1952         fw_data = (const __be32 *)rdev->me_fw->data;
1953         WREG32(CP_ME_RAM_WADDR, 0);
1954         for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
1955                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1956         WREG32(CP_ME_RAM_WADDR, 0);
1957
1958         WREG32(CP_PFP_UCODE_ADDR, 0);
1959         WREG32(CP_CE_UCODE_ADDR, 0);
1960         WREG32(CP_ME_RAM_WADDR, 0);
1961         WREG32(CP_ME_RAM_RADDR, 0);
1962         return 0;
1963 }
1964
1965 static int si_cp_start(struct radeon_device *rdev)
1966 {
1967         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1968         int r, i;
1969
1970         r = radeon_ring_lock(rdev, ring, 7 + 4);
1971         if (r) {
1972                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1973                 return r;
1974         }
1975         /* init the CP */
1976         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1977         radeon_ring_write(ring, 0x1);
1978         radeon_ring_write(ring, 0x0);
1979         radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
1980         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1981         radeon_ring_write(ring, 0);
1982         radeon_ring_write(ring, 0);
1983
1984         /* init the CE partitions */
1985         radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1986         radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1987         radeon_ring_write(ring, 0xc000);
1988         radeon_ring_write(ring, 0xe000);
1989         radeon_ring_unlock_commit(rdev, ring);
1990
1991         si_cp_enable(rdev, true);
1992
1993         r = radeon_ring_lock(rdev, ring, si_default_size + 10);
1994         if (r) {
1995                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1996                 return r;
1997         }
1998
1999         /* setup clear context state */
2000         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2001         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2002
2003         for (i = 0; i < si_default_size; i++)
2004                 radeon_ring_write(ring, si_default_state[i]);
2005
2006         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2007         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2008
2009         /* set clear context state */
2010         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2011         radeon_ring_write(ring, 0);
2012
2013         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2014         radeon_ring_write(ring, 0x00000316);
2015         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2016         radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2017
2018         radeon_ring_unlock_commit(rdev, ring);
2019
2020         for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
2021                 ring = &rdev->ring[i];
2022                 r = radeon_ring_lock(rdev, ring, 2);
2023
2024                 /* clear the compute context state */
2025                 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
2026                 radeon_ring_write(ring, 0);
2027
2028                 radeon_ring_unlock_commit(rdev, ring);
2029         }
2030
2031         return 0;
2032 }
2033
2034 static void si_cp_fini(struct radeon_device *rdev)
2035 {
2036         struct radeon_ring *ring;
2037         si_cp_enable(rdev, false);
2038
2039         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2040         radeon_ring_fini(rdev, ring);
2041         radeon_scratch_free(rdev, ring->rptr_save_reg);
2042
2043         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2044         radeon_ring_fini(rdev, ring);
2045         radeon_scratch_free(rdev, ring->rptr_save_reg);
2046
2047         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2048         radeon_ring_fini(rdev, ring);
2049         radeon_scratch_free(rdev, ring->rptr_save_reg);
2050 }
2051
2052 static int si_cp_resume(struct radeon_device *rdev)
2053 {
2054         struct radeon_ring *ring;
2055         u32 tmp;
2056         u32 rb_bufsz;
2057         int r;
2058
2059         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2060         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2061                                  SOFT_RESET_PA |
2062                                  SOFT_RESET_VGT |
2063                                  SOFT_RESET_SPI |
2064                                  SOFT_RESET_SX));
2065         RREG32(GRBM_SOFT_RESET);
2066         mdelay(15);
2067         WREG32(GRBM_SOFT_RESET, 0);
2068         RREG32(GRBM_SOFT_RESET);
2069
2070         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2071         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2072
2073         /* Set the write pointer delay */
2074         WREG32(CP_RB_WPTR_DELAY, 0);
2075
2076         WREG32(CP_DEBUG, 0);
2077         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2078
2079         /* ring 0 - compute and gfx */
2080         /* Set ring buffer size */
2081         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2082         rb_bufsz = drm_order(ring->ring_size / 8);
2083         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2084 #ifdef __BIG_ENDIAN
2085         tmp |= BUF_SWAP_32BIT;
2086 #endif
2087         WREG32(CP_RB0_CNTL, tmp);
2088
2089         /* Initialize the ring buffer's read and write pointers */
2090         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
2091         ring->wptr = 0;
2092         WREG32(CP_RB0_WPTR, ring->wptr);
2093
2094         /* set the wb address whether it's enabled or not */
2095         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2096         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2097
2098         if (rdev->wb.enabled)
2099                 WREG32(SCRATCH_UMSK, 0xff);
2100         else {
2101                 tmp |= RB_NO_UPDATE;
2102                 WREG32(SCRATCH_UMSK, 0);
2103         }
2104
2105         mdelay(1);
2106         WREG32(CP_RB0_CNTL, tmp);
2107
2108         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
2109
2110         ring->rptr = RREG32(CP_RB0_RPTR);
2111
2112         /* ring1  - compute only */
2113         /* Set ring buffer size */
2114         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
2115         rb_bufsz = drm_order(ring->ring_size / 8);
2116         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2117 #ifdef __BIG_ENDIAN
2118         tmp |= BUF_SWAP_32BIT;
2119 #endif
2120         WREG32(CP_RB1_CNTL, tmp);
2121
2122         /* Initialize the ring buffer's read and write pointers */
2123         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
2124         ring->wptr = 0;
2125         WREG32(CP_RB1_WPTR, ring->wptr);
2126
2127         /* set the wb address whether it's enabled or not */
2128         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
2129         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
2130
2131         mdelay(1);
2132         WREG32(CP_RB1_CNTL, tmp);
2133
2134         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
2135
2136         ring->rptr = RREG32(CP_RB1_RPTR);
2137
2138         /* ring2 - compute only */
2139         /* Set ring buffer size */
2140         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
2141         rb_bufsz = drm_order(ring->ring_size / 8);
2142         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2143 #ifdef __BIG_ENDIAN
2144         tmp |= BUF_SWAP_32BIT;
2145 #endif
2146         WREG32(CP_RB2_CNTL, tmp);
2147
2148         /* Initialize the ring buffer's read and write pointers */
2149         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
2150         ring->wptr = 0;
2151         WREG32(CP_RB2_WPTR, ring->wptr);
2152
2153         /* set the wb address whether it's enabled or not */
2154         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
2155         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
2156
2157         mdelay(1);
2158         WREG32(CP_RB2_CNTL, tmp);
2159
2160         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
2161
2162         ring->rptr = RREG32(CP_RB2_RPTR);
2163
2164         /* start the rings */
2165         si_cp_start(rdev);
2166         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
2167         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
2168         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
2169         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
2170         if (r) {
2171                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2172                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2173                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2174                 return r;
2175         }
2176         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
2177         if (r) {
2178                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
2179         }
2180         r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
2181         if (r) {
2182                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
2183         }
2184
2185         return 0;
2186 }
2187
2188 static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
2189 {
2190         u32 reset_mask = 0;
2191         u32 tmp;
2192
2193         /* GRBM_STATUS */
2194         tmp = RREG32(GRBM_STATUS);
2195         if (tmp & (PA_BUSY | SC_BUSY |
2196                    BCI_BUSY | SX_BUSY |
2197                    TA_BUSY | VGT_BUSY |
2198                    DB_BUSY | CB_BUSY |
2199                    GDS_BUSY | SPI_BUSY |
2200                    IA_BUSY | IA_BUSY_NO_DMA))
2201                 reset_mask |= RADEON_RESET_GFX;
2202
2203         if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2204                    CP_BUSY | CP_COHERENCY_BUSY))
2205                 reset_mask |= RADEON_RESET_CP;
2206
2207         if (tmp & GRBM_EE_BUSY)
2208                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2209
2210         /* GRBM_STATUS2 */
2211         tmp = RREG32(GRBM_STATUS2);
2212         if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2213                 reset_mask |= RADEON_RESET_RLC;
2214
2215         /* DMA_STATUS_REG 0 */
2216         tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2217         if (!(tmp & DMA_IDLE))
2218                 reset_mask |= RADEON_RESET_DMA;
2219
2220         /* DMA_STATUS_REG 1 */
2221         tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2222         if (!(tmp & DMA_IDLE))
2223                 reset_mask |= RADEON_RESET_DMA1;
2224
2225         /* SRBM_STATUS2 */
2226         tmp = RREG32(SRBM_STATUS2);
2227         if (tmp & DMA_BUSY)
2228                 reset_mask |= RADEON_RESET_DMA;
2229
2230         if (tmp & DMA1_BUSY)
2231                 reset_mask |= RADEON_RESET_DMA1;
2232
2233         /* SRBM_STATUS */
2234         tmp = RREG32(SRBM_STATUS);
2235
2236         if (tmp & IH_BUSY)
2237                 reset_mask |= RADEON_RESET_IH;
2238
2239         if (tmp & SEM_BUSY)
2240                 reset_mask |= RADEON_RESET_SEM;
2241
2242         if (tmp & GRBM_RQ_PENDING)
2243                 reset_mask |= RADEON_RESET_GRBM;
2244
2245         if (tmp & VMC_BUSY)
2246                 reset_mask |= RADEON_RESET_VMC;
2247
2248         if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2249                    MCC_BUSY | MCD_BUSY))
2250                 reset_mask |= RADEON_RESET_MC;
2251
2252         if (evergreen_is_display_hung(rdev))
2253                 reset_mask |= RADEON_RESET_DISPLAY;
2254
2255         /* VM_L2_STATUS */
2256         tmp = RREG32(VM_L2_STATUS);
2257         if (tmp & L2_BUSY)
2258                 reset_mask |= RADEON_RESET_VMC;
2259
2260         return reset_mask;
2261 }
2262
2263 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2264 {
2265         struct evergreen_mc_save save;
2266         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2267         u32 tmp;
2268
2269         if (reset_mask == 0)
2270                 return;
2271
2272         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2273
2274         evergreen_print_gpu_status_regs(rdev);
2275         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
2276                  RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2277         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2278                  RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2279
2280         /* Disable CP parsing/prefetching */
2281         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2282
2283         if (reset_mask & RADEON_RESET_DMA) {
2284                 /* dma0 */
2285                 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2286                 tmp &= ~DMA_RB_ENABLE;
2287                 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2288         }
2289         if (reset_mask & RADEON_RESET_DMA1) {
2290                 /* dma1 */
2291                 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2292                 tmp &= ~DMA_RB_ENABLE;
2293                 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2294         }
2295
2296         udelay(50);
2297
2298         evergreen_mc_stop(rdev, &save);
2299         if (evergreen_mc_wait_for_idle(rdev)) {
2300                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2301         }
2302
2303         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2304                 grbm_soft_reset = SOFT_RESET_CB |
2305                         SOFT_RESET_DB |
2306                         SOFT_RESET_GDS |
2307                         SOFT_RESET_PA |
2308                         SOFT_RESET_SC |
2309                         SOFT_RESET_BCI |
2310                         SOFT_RESET_SPI |
2311                         SOFT_RESET_SX |
2312                         SOFT_RESET_TC |
2313                         SOFT_RESET_TA |
2314                         SOFT_RESET_VGT |
2315                         SOFT_RESET_IA;
2316         }
2317
2318         if (reset_mask & RADEON_RESET_CP) {
2319                 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2320
2321                 srbm_soft_reset |= SOFT_RESET_GRBM;
2322         }
2323
2324         if (reset_mask & RADEON_RESET_DMA)
2325                 srbm_soft_reset |= SOFT_RESET_DMA;
2326
2327         if (reset_mask & RADEON_RESET_DMA1)
2328                 srbm_soft_reset |= SOFT_RESET_DMA1;
2329
2330         if (reset_mask & RADEON_RESET_DISPLAY)
2331                 srbm_soft_reset |= SOFT_RESET_DC;
2332
2333         if (reset_mask & RADEON_RESET_RLC)
2334                 grbm_soft_reset |= SOFT_RESET_RLC;
2335
2336         if (reset_mask & RADEON_RESET_SEM)
2337                 srbm_soft_reset |= SOFT_RESET_SEM;
2338
2339         if (reset_mask & RADEON_RESET_IH)
2340                 srbm_soft_reset |= SOFT_RESET_IH;
2341
2342         if (reset_mask & RADEON_RESET_GRBM)
2343                 srbm_soft_reset |= SOFT_RESET_GRBM;
2344
2345         if (reset_mask & RADEON_RESET_VMC)
2346                 srbm_soft_reset |= SOFT_RESET_VMC;
2347
2348         if (reset_mask & RADEON_RESET_MC)
2349                 srbm_soft_reset |= SOFT_RESET_MC;
2350
2351         if (grbm_soft_reset) {
2352                 tmp = RREG32(GRBM_SOFT_RESET);
2353                 tmp |= grbm_soft_reset;
2354                 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2355                 WREG32(GRBM_SOFT_RESET, tmp);
2356                 tmp = RREG32(GRBM_SOFT_RESET);
2357
2358                 udelay(50);
2359
2360                 tmp &= ~grbm_soft_reset;
2361                 WREG32(GRBM_SOFT_RESET, tmp);
2362                 tmp = RREG32(GRBM_SOFT_RESET);
2363         }
2364
2365         if (srbm_soft_reset) {
2366                 tmp = RREG32(SRBM_SOFT_RESET);
2367                 tmp |= srbm_soft_reset;
2368                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2369                 WREG32(SRBM_SOFT_RESET, tmp);
2370                 tmp = RREG32(SRBM_SOFT_RESET);
2371
2372                 udelay(50);
2373
2374                 tmp &= ~srbm_soft_reset;
2375                 WREG32(SRBM_SOFT_RESET, tmp);
2376                 tmp = RREG32(SRBM_SOFT_RESET);
2377         }
2378
2379         /* Wait a little for things to settle down */
2380         udelay(50);
2381
2382         evergreen_mc_resume(rdev, &save);
2383         udelay(50);
2384
2385         evergreen_print_gpu_status_regs(rdev);
2386 }
2387
2388 int si_asic_reset(struct radeon_device *rdev)
2389 {
2390         u32 reset_mask;
2391
2392         reset_mask = si_gpu_check_soft_reset(rdev);
2393
2394         if (reset_mask)
2395                 r600_set_bios_scratch_engine_hung(rdev, true);
2396
2397         si_gpu_soft_reset(rdev, reset_mask);
2398
2399         reset_mask = si_gpu_check_soft_reset(rdev);
2400
2401         if (!reset_mask)
2402                 r600_set_bios_scratch_engine_hung(rdev, false);
2403
2404         return 0;
2405 }
2406
2407 /**
2408  * si_gfx_is_lockup - Check if the GFX engine is locked up
2409  *
2410  * @rdev: radeon_device pointer
2411  * @ring: radeon_ring structure holding ring information
2412  *
2413  * Check if the GFX engine is locked up.
2414  * Returns true if the engine appears to be locked up, false if not.
2415  */
2416 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2417 {
2418         u32 reset_mask = si_gpu_check_soft_reset(rdev);
2419
2420         if (!(reset_mask & (RADEON_RESET_GFX |
2421                             RADEON_RESET_COMPUTE |
2422                             RADEON_RESET_CP))) {
2423                 radeon_ring_lockup_update(ring);
2424                 return false;
2425         }
2426         /* force CP activities */
2427         radeon_ring_force_activity(rdev, ring);
2428         return radeon_ring_test_lockup(rdev, ring);
2429 }
2430
2431 /**
2432  * si_dma_is_lockup - Check if the DMA engine is locked up
2433  *
2434  * @rdev: radeon_device pointer
2435  * @ring: radeon_ring structure holding ring information
2436  *
2437  * Check if the async DMA engine is locked up.
2438  * Returns true if the engine appears to be locked up, false if not.
2439  */
2440 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2441 {
2442         u32 reset_mask = si_gpu_check_soft_reset(rdev);
2443         u32 mask;
2444
2445         if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2446                 mask = RADEON_RESET_DMA;
2447         else
2448                 mask = RADEON_RESET_DMA1;
2449
2450         if (!(reset_mask & mask)) {
2451                 radeon_ring_lockup_update(ring);
2452                 return false;
2453         }
2454         /* force ring activities */
2455         radeon_ring_force_activity(rdev, ring);
2456         return radeon_ring_test_lockup(rdev, ring);
2457 }
2458
2459 /* MC */
2460 static void si_mc_program(struct radeon_device *rdev)
2461 {
2462         struct evergreen_mc_save save;
2463         u32 tmp;
2464         int i, j;
2465
2466         /* Initialize HDP */
2467         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2468                 WREG32((0x2c14 + j), 0x00000000);
2469                 WREG32((0x2c18 + j), 0x00000000);
2470                 WREG32((0x2c1c + j), 0x00000000);
2471                 WREG32((0x2c20 + j), 0x00000000);
2472                 WREG32((0x2c24 + j), 0x00000000);
2473         }
2474         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2475
2476         evergreen_mc_stop(rdev, &save);
2477         if (radeon_mc_wait_for_idle(rdev)) {
2478                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2479         }
2480         /* Lockout access through VGA aperture*/
2481         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2482         /* Update configuration */
2483         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2484                rdev->mc.vram_start >> 12);
2485         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2486                rdev->mc.vram_end >> 12);
2487         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2488                rdev->vram_scratch.gpu_addr >> 12);
2489         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2490         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2491         WREG32(MC_VM_FB_LOCATION, tmp);
2492         /* XXX double check these! */
2493         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2494         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2495         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2496         WREG32(MC_VM_AGP_BASE, 0);
2497         WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2498         WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2499         if (radeon_mc_wait_for_idle(rdev)) {
2500                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2501         }
2502         evergreen_mc_resume(rdev, &save);
2503         /* we need to own VRAM, so turn off the VGA renderer here
2504          * to stop it overwriting our objects */
2505         rv515_vga_render_disable(rdev);
2506 }
2507
2508 /* SI MC address space is 40 bits */
2509 static void si_vram_location(struct radeon_device *rdev,
2510                              struct radeon_mc *mc, u64 base)
2511 {
2512         mc->vram_start = base;
2513         if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) {
2514                 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
2515                 mc->real_vram_size = mc->aper_size;
2516                 mc->mc_vram_size = mc->aper_size;
2517         }
2518         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
2519         dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
2520                         mc->mc_vram_size >> 20, mc->vram_start,
2521                         mc->vram_end, mc->real_vram_size >> 20);
2522 }
2523
2524 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
2525 {
2526         u64 size_af, size_bf;
2527
2528         size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
2529         size_bf = mc->vram_start & ~mc->gtt_base_align;
2530         if (size_bf > size_af) {
2531                 if (mc->gtt_size > size_bf) {
2532                         dev_warn(rdev->dev, "limiting GTT\n");
2533                         mc->gtt_size = size_bf;
2534                 }
2535                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
2536         } else {
2537                 if (mc->gtt_size > size_af) {
2538                         dev_warn(rdev->dev, "limiting GTT\n");
2539                         mc->gtt_size = size_af;
2540                 }
2541                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
2542         }
2543         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
2544         dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
2545                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
2546 }
2547
2548 static void si_vram_gtt_location(struct radeon_device *rdev,
2549                                  struct radeon_mc *mc)
2550 {
2551         if (mc->mc_vram_size > 0xFFC0000000ULL) {
2552                 /* leave room for at least 1024M GTT */
2553                 dev_warn(rdev->dev, "limiting VRAM\n");
2554                 mc->real_vram_size = 0xFFC0000000ULL;
2555                 mc->mc_vram_size = 0xFFC0000000ULL;
2556         }
2557         si_vram_location(rdev, &rdev->mc, 0);
2558         rdev->mc.gtt_base_align = 0;
2559         si_gtt_location(rdev, mc);
2560 }
2561
2562 static int si_mc_init(struct radeon_device *rdev)
2563 {
2564         u32 tmp;
2565         int chansize, numchan;
2566
2567         /* Get VRAM informations */
2568         rdev->mc.vram_is_ddr = true;
2569         tmp = RREG32(MC_ARB_RAMCFG);
2570         if (tmp & CHANSIZE_OVERRIDE) {
2571                 chansize = 16;
2572         } else if (tmp & CHANSIZE_MASK) {
2573                 chansize = 64;
2574         } else {
2575                 chansize = 32;
2576         }
2577         tmp = RREG32(MC_SHARED_CHMAP);
2578         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2579         case 0:
2580         default:
2581                 numchan = 1;
2582                 break;
2583         case 1:
2584                 numchan = 2;
2585                 break;
2586         case 2:
2587                 numchan = 4;
2588                 break;
2589         case 3:
2590                 numchan = 8;
2591                 break;
2592         case 4:
2593                 numchan = 3;
2594                 break;
2595         case 5:
2596                 numchan = 6;
2597                 break;
2598         case 6:
2599                 numchan = 10;
2600                 break;
2601         case 7:
2602                 numchan = 12;
2603                 break;
2604         case 8:
2605                 numchan = 16;
2606                 break;
2607         }
2608         rdev->mc.vram_width = numchan * chansize;
2609         /* Could aper size report 0 ? */
2610         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2611         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2612         /* size in MB on si */
2613         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2614         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2615         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2616         si_vram_gtt_location(rdev, &rdev->mc);
2617         radeon_update_bandwidth_info(rdev);
2618
2619         return 0;
2620 }
2621
2622 /*
2623  * GART
2624  */
2625 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
2626 {
2627         /* flush hdp cache */
2628         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2629
2630         /* bits 0-15 are the VM contexts0-15 */
2631         WREG32(VM_INVALIDATE_REQUEST, 1);
2632 }
2633
2634 static int si_pcie_gart_enable(struct radeon_device *rdev)
2635 {
2636         int r, i;
2637
2638         if (rdev->gart.robj == NULL) {
2639                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2640                 return -EINVAL;
2641         }
2642         r = radeon_gart_table_vram_pin(rdev);
2643         if (r)
2644                 return r;
2645         radeon_gart_restore(rdev);
2646         /* Setup TLB control */
2647         WREG32(MC_VM_MX_L1_TLB_CNTL,
2648                (0xA << 7) |
2649                ENABLE_L1_TLB |
2650                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2651                ENABLE_ADVANCED_DRIVER_MODEL |
2652                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2653         /* Setup L2 cache */
2654         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
2655                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2656                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2657                EFFECTIVE_L2_QUEUE_SIZE(7) |
2658                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2659         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
2660         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2661                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2662         /* setup context0 */
2663         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2664         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2665         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2666         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2667                         (u32)(rdev->dummy_page.addr >> 12));
2668         WREG32(VM_CONTEXT0_CNTL2, 0);
2669         WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2670                                   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
2671
2672         WREG32(0x15D4, 0);
2673         WREG32(0x15D8, 0);
2674         WREG32(0x15DC, 0);
2675
2676         /* empty context1-15 */
2677         /* set vm size, must be a multiple of 4 */
2678         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2679         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2680         /* Assign the pt base to something valid for now; the pts used for
2681          * the VMs are determined by the application and setup and assigned
2682          * on the fly in the vm part of radeon_gart.c
2683          */
2684         for (i = 1; i < 16; i++) {
2685                 if (i < 8)
2686                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
2687                                rdev->gart.table_addr >> 12);
2688                 else
2689                         WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
2690                                rdev->gart.table_addr >> 12);
2691         }
2692
2693         /* enable context1-15 */
2694         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2695                (u32)(rdev->dummy_page.addr >> 12));
2696         WREG32(VM_CONTEXT1_CNTL2, 4);
2697         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
2698                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2699                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2700                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2701                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
2702                                 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
2703                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
2704                                 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
2705                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
2706                                 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
2707                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
2708                                 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
2709                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
2710
2711         si_pcie_gart_tlb_flush(rdev);
2712         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2713                  (unsigned)(rdev->mc.gtt_size >> 20),
2714                  (unsigned long long)rdev->gart.table_addr);
2715         rdev->gart.ready = true;
2716         return 0;
2717 }
2718
2719 static void si_pcie_gart_disable(struct radeon_device *rdev)
2720 {
2721         /* Disable all tables */
2722         WREG32(VM_CONTEXT0_CNTL, 0);
2723         WREG32(VM_CONTEXT1_CNTL, 0);
2724         /* Setup TLB control */
2725         WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2726                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
2727         /* Setup L2 cache */
2728         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2729                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
2730                EFFECTIVE_L2_QUEUE_SIZE(7) |
2731                CONTEXT1_IDENTITY_ACCESS_MODE(1));
2732         WREG32(VM_L2_CNTL2, 0);
2733         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
2734                L2_CACHE_BIGK_FRAGMENT_SIZE(0));
2735         radeon_gart_table_vram_unpin(rdev);
2736 }
2737
2738 static void si_pcie_gart_fini(struct radeon_device *rdev)
2739 {
2740         si_pcie_gart_disable(rdev);
2741         radeon_gart_table_vram_free(rdev);
2742         radeon_gart_fini(rdev);
2743 }
2744
2745 /* vm parser */
2746 static bool si_vm_reg_valid(u32 reg)
2747 {
2748         /* context regs are fine */
2749         if (reg >= 0x28000)
2750                 return true;
2751
2752         /* check config regs */
2753         switch (reg) {
2754         case GRBM_GFX_INDEX:
2755         case CP_STRMOUT_CNTL:
2756         case VGT_VTX_VECT_EJECT_REG:
2757         case VGT_CACHE_INVALIDATION:
2758         case VGT_ESGS_RING_SIZE:
2759         case VGT_GSVS_RING_SIZE:
2760         case VGT_GS_VERTEX_REUSE:
2761         case VGT_PRIMITIVE_TYPE:
2762         case VGT_INDEX_TYPE:
2763         case VGT_NUM_INDICES:
2764         case VGT_NUM_INSTANCES:
2765         case VGT_TF_RING_SIZE:
2766         case VGT_HS_OFFCHIP_PARAM:
2767         case VGT_TF_MEMORY_BASE:
2768         case PA_CL_ENHANCE:
2769         case PA_SU_LINE_STIPPLE_VALUE:
2770         case PA_SC_LINE_STIPPLE_STATE:
2771         case PA_SC_ENHANCE:
2772         case SQC_CACHES:
2773         case SPI_STATIC_THREAD_MGMT_1:
2774         case SPI_STATIC_THREAD_MGMT_2:
2775         case SPI_STATIC_THREAD_MGMT_3:
2776         case SPI_PS_MAX_WAVE_ID:
2777         case SPI_CONFIG_CNTL:
2778         case SPI_CONFIG_CNTL_1:
2779         case TA_CNTL_AUX:
2780                 return true;
2781         default:
2782                 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2783                 return false;
2784         }
2785 }
2786
2787 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
2788                                   u32 *ib, struct radeon_cs_packet *pkt)
2789 {
2790         switch (pkt->opcode) {
2791         case PACKET3_NOP:
2792         case PACKET3_SET_BASE:
2793         case PACKET3_SET_CE_DE_COUNTERS:
2794         case PACKET3_LOAD_CONST_RAM:
2795         case PACKET3_WRITE_CONST_RAM:
2796         case PACKET3_WRITE_CONST_RAM_OFFSET:
2797         case PACKET3_DUMP_CONST_RAM:
2798         case PACKET3_INCREMENT_CE_COUNTER:
2799         case PACKET3_WAIT_ON_DE_COUNTER:
2800         case PACKET3_CE_WRITE:
2801                 break;
2802         default:
2803                 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
2804                 return -EINVAL;
2805         }
2806         return 0;
2807 }
2808
2809 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
2810                                    u32 *ib, struct radeon_cs_packet *pkt)
2811 {
2812         u32 idx = pkt->idx + 1;
2813         u32 idx_value = ib[idx];
2814         u32 start_reg, end_reg, reg, i;
2815         u32 command, info;
2816
2817         switch (pkt->opcode) {
2818         case PACKET3_NOP:
2819         case PACKET3_SET_BASE:
2820         case PACKET3_CLEAR_STATE:
2821         case PACKET3_INDEX_BUFFER_SIZE:
2822         case PACKET3_DISPATCH_DIRECT:
2823         case PACKET3_DISPATCH_INDIRECT:
2824         case PACKET3_ALLOC_GDS:
2825         case PACKET3_WRITE_GDS_RAM:
2826         case PACKET3_ATOMIC_GDS:
2827         case PACKET3_ATOMIC:
2828         case PACKET3_OCCLUSION_QUERY:
2829         case PACKET3_SET_PREDICATION:
2830         case PACKET3_COND_EXEC:
2831         case PACKET3_PRED_EXEC:
2832         case PACKET3_DRAW_INDIRECT:
2833         case PACKET3_DRAW_INDEX_INDIRECT:
2834         case PACKET3_INDEX_BASE:
2835         case PACKET3_DRAW_INDEX_2:
2836         case PACKET3_CONTEXT_CONTROL:
2837         case PACKET3_INDEX_TYPE:
2838         case PACKET3_DRAW_INDIRECT_MULTI:
2839         case PACKET3_DRAW_INDEX_AUTO:
2840         case PACKET3_DRAW_INDEX_IMMD:
2841         case PACKET3_NUM_INSTANCES:
2842         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2843         case PACKET3_STRMOUT_BUFFER_UPDATE:
2844         case PACKET3_DRAW_INDEX_OFFSET_2:
2845         case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2846         case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
2847         case PACKET3_MPEG_INDEX:
2848         case PACKET3_WAIT_REG_MEM:
2849         case PACKET3_MEM_WRITE:
2850         case PACKET3_PFP_SYNC_ME:
2851         case PACKET3_SURFACE_SYNC:
2852         case PACKET3_EVENT_WRITE:
2853         case PACKET3_EVENT_WRITE_EOP:
2854         case PACKET3_EVENT_WRITE_EOS:
2855         case PACKET3_SET_CONTEXT_REG:
2856         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2857         case PACKET3_SET_SH_REG:
2858         case PACKET3_SET_SH_REG_OFFSET:
2859         case PACKET3_INCREMENT_DE_COUNTER:
2860         case PACKET3_WAIT_ON_CE_COUNTER:
2861         case PACKET3_WAIT_ON_AVAIL_BUFFER:
2862         case PACKET3_ME_WRITE:
2863                 break;
2864         case PACKET3_COPY_DATA:
2865                 if ((idx_value & 0xf00) == 0) {
2866                         reg = ib[idx + 3] * 4;
2867                         if (!si_vm_reg_valid(reg))
2868                                 return -EINVAL;
2869                 }
2870                 break;
2871         case PACKET3_WRITE_DATA:
2872                 if ((idx_value & 0xf00) == 0) {
2873                         start_reg = ib[idx + 1] * 4;
2874                         if (idx_value & 0x10000) {
2875                                 if (!si_vm_reg_valid(start_reg))
2876                                         return -EINVAL;
2877                         } else {
2878                                 for (i = 0; i < (pkt->count - 2); i++) {
2879                                         reg = start_reg + (4 * i);
2880                                         if (!si_vm_reg_valid(reg))
2881                                                 return -EINVAL;
2882                                 }
2883                         }
2884                 }
2885                 break;
2886         case PACKET3_COND_WRITE:
2887                 if (idx_value & 0x100) {
2888                         reg = ib[idx + 5] * 4;
2889                         if (!si_vm_reg_valid(reg))
2890                                 return -EINVAL;
2891                 }
2892                 break;
2893         case PACKET3_COPY_DW:
2894                 if (idx_value & 0x2) {
2895                         reg = ib[idx + 3] * 4;
2896                         if (!si_vm_reg_valid(reg))
2897                                 return -EINVAL;
2898                 }
2899                 break;
2900         case PACKET3_SET_CONFIG_REG:
2901                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2902                 end_reg = 4 * pkt->count + start_reg - 4;
2903                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2904                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2905                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2906                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2907                         return -EINVAL;
2908                 }
2909                 for (i = 0; i < pkt->count; i++) {
2910                         reg = start_reg + (4 * i);
2911                         if (!si_vm_reg_valid(reg))
2912                                 return -EINVAL;
2913                 }
2914                 break;
2915         case PACKET3_CP_DMA:
2916                 command = ib[idx + 4];
2917                 info = ib[idx + 1];
2918                 if (command & PACKET3_CP_DMA_CMD_SAS) {
2919                         /* src address space is register */
2920                         if (((info & 0x60000000) >> 29) == 0) {
2921                                 start_reg = idx_value << 2;
2922                                 if (command & PACKET3_CP_DMA_CMD_SAIC) {
2923                                         reg = start_reg;
2924                                         if (!si_vm_reg_valid(reg)) {
2925                                                 DRM_ERROR("CP DMA Bad SRC register\n");
2926                                                 return -EINVAL;
2927                                         }
2928                                 } else {
2929                                         for (i = 0; i < (command & 0x1fffff); i++) {
2930                                                 reg = start_reg + (4 * i);
2931                                                 if (!si_vm_reg_valid(reg)) {
2932                                                         DRM_ERROR("CP DMA Bad SRC register\n");
2933                                                         return -EINVAL;
2934                                                 }
2935                                         }
2936                                 }
2937                         }
2938                 }
2939                 if (command & PACKET3_CP_DMA_CMD_DAS) {
2940                         /* dst address space is register */
2941                         if (((info & 0x00300000) >> 20) == 0) {
2942                                 start_reg = ib[idx + 2];
2943                                 if (command & PACKET3_CP_DMA_CMD_DAIC) {
2944                                         reg = start_reg;
2945                                         if (!si_vm_reg_valid(reg)) {
2946                                                 DRM_ERROR("CP DMA Bad DST register\n");
2947                                                 return -EINVAL;
2948                                         }
2949                                 } else {
2950                                         for (i = 0; i < (command & 0x1fffff); i++) {
2951                                                 reg = start_reg + (4 * i);
2952                                                 if (!si_vm_reg_valid(reg)) {
2953                                                         DRM_ERROR("CP DMA Bad DST register\n");
2954                                                         return -EINVAL;
2955                                                 }
2956                                         }
2957                                 }
2958                         }
2959                 }
2960                 break;
2961         default:
2962                 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
2963                 return -EINVAL;
2964         }
2965         return 0;
2966 }
2967
2968 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
2969                                        u32 *ib, struct radeon_cs_packet *pkt)
2970 {
2971         u32 idx = pkt->idx + 1;
2972         u32 idx_value = ib[idx];
2973         u32 start_reg, reg, i;
2974
2975         switch (pkt->opcode) {
2976         case PACKET3_NOP:
2977         case PACKET3_SET_BASE:
2978         case PACKET3_CLEAR_STATE:
2979         case PACKET3_DISPATCH_DIRECT:
2980         case PACKET3_DISPATCH_INDIRECT:
2981         case PACKET3_ALLOC_GDS:
2982         case PACKET3_WRITE_GDS_RAM:
2983         case PACKET3_ATOMIC_GDS:
2984         case PACKET3_ATOMIC:
2985         case PACKET3_OCCLUSION_QUERY:
2986         case PACKET3_SET_PREDICATION:
2987         case PACKET3_COND_EXEC:
2988         case PACKET3_PRED_EXEC:
2989         case PACKET3_CONTEXT_CONTROL:
2990         case PACKET3_STRMOUT_BUFFER_UPDATE:
2991         case PACKET3_WAIT_REG_MEM:
2992         case PACKET3_MEM_WRITE:
2993         case PACKET3_PFP_SYNC_ME:
2994         case PACKET3_SURFACE_SYNC:
2995         case PACKET3_EVENT_WRITE:
2996         case PACKET3_EVENT_WRITE_EOP:
2997         case PACKET3_EVENT_WRITE_EOS:
2998         case PACKET3_SET_CONTEXT_REG:
2999         case PACKET3_SET_CONTEXT_REG_INDIRECT:
3000         case PACKET3_SET_SH_REG:
3001         case PACKET3_SET_SH_REG_OFFSET:
3002         case PACKET3_INCREMENT_DE_COUNTER:
3003         case PACKET3_WAIT_ON_CE_COUNTER:
3004         case PACKET3_WAIT_ON_AVAIL_BUFFER:
3005         case PACKET3_ME_WRITE:
3006                 break;
3007         case PACKET3_COPY_DATA:
3008                 if ((idx_value & 0xf00) == 0) {
3009                         reg = ib[idx + 3] * 4;
3010                         if (!si_vm_reg_valid(reg))
3011                                 return -EINVAL;
3012                 }
3013                 break;
3014         case PACKET3_WRITE_DATA:
3015                 if ((idx_value & 0xf00) == 0) {
3016                         start_reg = ib[idx + 1] * 4;
3017                         if (idx_value & 0x10000) {
3018                                 if (!si_vm_reg_valid(start_reg))
3019                                         return -EINVAL;
3020                         } else {
3021                                 for (i = 0; i < (pkt->count - 2); i++) {
3022                                         reg = start_reg + (4 * i);
3023                                         if (!si_vm_reg_valid(reg))
3024                                                 return -EINVAL;
3025                                 }
3026                         }
3027                 }
3028                 break;
3029         case PACKET3_COND_WRITE:
3030                 if (idx_value & 0x100) {
3031                         reg = ib[idx + 5] * 4;
3032                         if (!si_vm_reg_valid(reg))
3033                                 return -EINVAL;
3034                 }
3035                 break;
3036         case PACKET3_COPY_DW:
3037                 if (idx_value & 0x2) {
3038                         reg = ib[idx + 3] * 4;
3039                         if (!si_vm_reg_valid(reg))
3040                                 return -EINVAL;
3041                 }
3042                 break;
3043         default:
3044                 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
3045                 return -EINVAL;
3046         }
3047         return 0;
3048 }
3049
3050 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3051 {
3052         int ret = 0;
3053         u32 idx = 0;
3054         struct radeon_cs_packet pkt;
3055
3056         do {
3057                 pkt.idx = idx;
3058                 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
3059                 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
3060                 pkt.one_reg_wr = 0;
3061                 switch (pkt.type) {
3062                 case RADEON_PACKET_TYPE0:
3063                         dev_err(rdev->dev, "Packet0 not allowed!\n");
3064                         ret = -EINVAL;
3065                         break;
3066                 case RADEON_PACKET_TYPE2:
3067                         idx += 1;
3068                         break;
3069                 case RADEON_PACKET_TYPE3:
3070                         pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3071                         if (ib->is_const_ib)
3072                                 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
3073                         else {
3074                                 switch (ib->ring) {
3075                                 case RADEON_RING_TYPE_GFX_INDEX:
3076                                         ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
3077                                         break;
3078                                 case CAYMAN_RING_TYPE_CP1_INDEX:
3079                                 case CAYMAN_RING_TYPE_CP2_INDEX:
3080                                         ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
3081                                         break;
3082                                 default:
3083                                         dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
3084                                         ret = -EINVAL;
3085                                         break;
3086                                 }
3087                         }
3088                         idx += pkt.count + 2;
3089                         break;
3090                 default:
3091                         dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3092                         ret = -EINVAL;
3093                         break;
3094                 }
3095                 if (ret)
3096                         break;
3097         } while (idx < ib->length_dw);
3098
3099         return ret;
3100 }
3101
3102 /*
3103  * vm
3104  */
3105 int si_vm_init(struct radeon_device *rdev)
3106 {
3107         /* number of VMs */
3108         rdev->vm_manager.nvm = 16;
3109         /* base offset of vram pages */
3110         rdev->vm_manager.vram_base_offset = 0;
3111
3112         return 0;
3113 }
3114
3115 void si_vm_fini(struct radeon_device *rdev)
3116 {
3117 }
3118
3119 /**
3120  * si_vm_set_page - update the page tables using the CP
3121  *
3122  * @rdev: radeon_device pointer
3123  * @ib: indirect buffer to fill with commands
3124  * @pe: addr of the page entry
3125  * @addr: dst addr to write into pe
3126  * @count: number of page entries to update
3127  * @incr: increase next addr by incr bytes
3128  * @flags: access flags
3129  *
3130  * Update the page tables using the CP (SI).
3131  */
3132 void si_vm_set_page(struct radeon_device *rdev,
3133                     struct radeon_ib *ib,
3134                     uint64_t pe,
3135                     uint64_t addr, unsigned count,
3136                     uint32_t incr, uint32_t flags)
3137 {
3138         uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3139         uint64_t value;
3140         unsigned ndw;
3141
3142         if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
3143                 while (count) {
3144                         ndw = 2 + count * 2;
3145                         if (ndw > 0x3FFE)
3146                                 ndw = 0x3FFE;
3147
3148                         ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
3149                         ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
3150                                         WRITE_DATA_DST_SEL(1));
3151                         ib->ptr[ib->length_dw++] = pe;
3152                         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
3153                         for (; ndw > 2; ndw -= 2, --count, pe += 8) {
3154                                 if (flags & RADEON_VM_PAGE_SYSTEM) {
3155                                         value = radeon_vm_map_gart(rdev, addr);
3156                                         value &= 0xFFFFFFFFFFFFF000ULL;
3157                                 } else if (flags & RADEON_VM_PAGE_VALID) {
3158                                         value = addr;
3159                                 } else {
3160                                         value = 0;
3161                                 }
3162                                 addr += incr;
3163                                 value |= r600_flags;
3164                                 ib->ptr[ib->length_dw++] = value;
3165                                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3166                         }
3167                 }
3168         } else {
3169                 /* DMA */
3170                 if (flags & RADEON_VM_PAGE_SYSTEM) {
3171                         while (count) {
3172                                 ndw = count * 2;
3173                                 if (ndw > 0xFFFFE)
3174                                         ndw = 0xFFFFE;
3175
3176                                 /* for non-physically contiguous pages (system) */
3177                                 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
3178                                 ib->ptr[ib->length_dw++] = pe;
3179                                 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3180                                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
3181                                         if (flags & RADEON_VM_PAGE_SYSTEM) {
3182                                                 value = radeon_vm_map_gart(rdev, addr);
3183                                                 value &= 0xFFFFFFFFFFFFF000ULL;
3184                                         } else if (flags & RADEON_VM_PAGE_VALID) {
3185                                                 value = addr;
3186                                         } else {
3187                                                 value = 0;
3188                                         }
3189                                         addr += incr;
3190                                         value |= r600_flags;
3191                                         ib->ptr[ib->length_dw++] = value;
3192                                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
3193                                 }
3194                         }
3195                 } else {
3196                         while (count) {
3197                                 ndw = count * 2;
3198                                 if (ndw > 0xFFFFE)
3199                                         ndw = 0xFFFFE;
3200
3201                                 if (flags & RADEON_VM_PAGE_VALID)
3202                                         value = addr;
3203                                 else
3204                                         value = 0;
3205                                 /* for physically contiguous pages (vram) */
3206                                 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
3207                                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
3208                                 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3209                                 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
3210                                 ib->ptr[ib->length_dw++] = 0;
3211                                 ib->ptr[ib->length_dw++] = value; /* value */
3212                                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3213                                 ib->ptr[ib->length_dw++] = incr; /* increment size */
3214                                 ib->ptr[ib->length_dw++] = 0;
3215                                 pe += ndw * 4;
3216                                 addr += (ndw / 2) * incr;
3217                                 count -= ndw / 2;
3218                         }
3219                 }
3220                 while (ib->length_dw & 0x7)
3221                         ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
3222         }
3223 }
3224
3225 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3226 {
3227         struct radeon_ring *ring = &rdev->ring[ridx];
3228
3229         if (vm == NULL)
3230                 return;
3231
3232         /* write new base address */
3233         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3234         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3235                                  WRITE_DATA_DST_SEL(0)));
3236
3237         if (vm->id < 8) {
3238                 radeon_ring_write(ring,
3239                                   (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
3240         } else {
3241                 radeon_ring_write(ring,
3242                                   (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
3243         }
3244         radeon_ring_write(ring, 0);
3245         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3246
3247         /* flush hdp cache */
3248         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3249         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3250                                  WRITE_DATA_DST_SEL(0)));
3251         radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3252         radeon_ring_write(ring, 0);
3253         radeon_ring_write(ring, 0x1);
3254
3255         /* bits 0-15 are the VM contexts0-15 */
3256         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3257         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3258                                  WRITE_DATA_DST_SEL(0)));
3259         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3260         radeon_ring_write(ring, 0);
3261         radeon_ring_write(ring, 1 << vm->id);
3262
3263         /* sync PFP to ME, otherwise we might get invalid PFP reads */
3264         radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3265         radeon_ring_write(ring, 0x0);
3266 }
3267
3268 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3269 {
3270         struct radeon_ring *ring = &rdev->ring[ridx];
3271
3272         if (vm == NULL)
3273                 return;
3274
3275         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3276         if (vm->id < 8) {
3277                 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
3278         } else {
3279                 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
3280         }
3281         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3282
3283         /* flush hdp cache */
3284         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3285         radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3286         radeon_ring_write(ring, 1);
3287
3288         /* bits 0-7 are the VM contexts0-7 */
3289         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
3290         radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
3291         radeon_ring_write(ring, 1 << vm->id);
3292 }
3293
3294 /*
3295  * RLC
3296  */
3297 void si_rlc_fini(struct radeon_device *rdev)
3298 {
3299         int r;
3300
3301         /* save restore block */
3302         if (rdev->rlc.save_restore_obj) {
3303                 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3304                 if (unlikely(r != 0))
3305                         dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3306                 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3307                 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3308
3309                 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3310                 rdev->rlc.save_restore_obj = NULL;
3311         }
3312
3313         /* clear state block */
3314         if (rdev->rlc.clear_state_obj) {
3315                 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3316                 if (unlikely(r != 0))
3317                         dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3318                 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3319                 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3320
3321                 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3322                 rdev->rlc.clear_state_obj = NULL;
3323         }
3324 }
3325
3326 int si_rlc_init(struct radeon_device *rdev)
3327 {
3328         int r;
3329
3330         /* save restore block */
3331         if (rdev->rlc.save_restore_obj == NULL) {
3332                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3333                                      RADEON_GEM_DOMAIN_VRAM, NULL,
3334                                      &rdev->rlc.save_restore_obj);
3335                 if (r) {
3336                         dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3337                         return r;
3338                 }
3339         }
3340
3341         r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3342         if (unlikely(r != 0)) {
3343                 si_rlc_fini(rdev);
3344                 return r;
3345         }
3346         r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3347                           &rdev->rlc.save_restore_gpu_addr);
3348         radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3349         if (r) {
3350                 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3351                 si_rlc_fini(rdev);
3352                 return r;
3353         }
3354
3355         /* clear state block */
3356         if (rdev->rlc.clear_state_obj == NULL) {
3357                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
3358                                      RADEON_GEM_DOMAIN_VRAM, NULL,
3359                                      &rdev->rlc.clear_state_obj);
3360                 if (r) {
3361                         dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3362                         si_rlc_fini(rdev);
3363                         return r;
3364                 }
3365         }
3366         r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3367         if (unlikely(r != 0)) {
3368                 si_rlc_fini(rdev);
3369                 return r;
3370         }
3371         r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3372                           &rdev->rlc.clear_state_gpu_addr);
3373         radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3374         if (r) {
3375                 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3376                 si_rlc_fini(rdev);
3377                 return r;
3378         }
3379
3380         return 0;
3381 }
3382
3383 static void si_rlc_stop(struct radeon_device *rdev)
3384 {
3385         WREG32(RLC_CNTL, 0);
3386 }
3387
3388 static void si_rlc_start(struct radeon_device *rdev)
3389 {
3390         WREG32(RLC_CNTL, RLC_ENABLE);
3391 }
3392
3393 static int si_rlc_resume(struct radeon_device *rdev)
3394 {
3395         u32 i;
3396         const __be32 *fw_data;
3397
3398         if (!rdev->rlc_fw)
3399                 return -EINVAL;
3400
3401         si_rlc_stop(rdev);
3402
3403         WREG32(RLC_RL_BASE, 0);
3404         WREG32(RLC_RL_SIZE, 0);
3405         WREG32(RLC_LB_CNTL, 0);
3406         WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
3407         WREG32(RLC_LB_CNTR_INIT, 0);
3408
3409         WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3410         WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3411
3412         WREG32(RLC_MC_CNTL, 0);
3413         WREG32(RLC_UCODE_CNTL, 0);
3414
3415         fw_data = (const __be32 *)rdev->rlc_fw->data;
3416         for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
3417                 WREG32(RLC_UCODE_ADDR, i);
3418                 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3419         }
3420         WREG32(RLC_UCODE_ADDR, 0);
3421
3422         si_rlc_start(rdev);
3423
3424         return 0;
3425 }
3426
3427 static void si_enable_interrupts(struct radeon_device *rdev)
3428 {
3429         u32 ih_cntl = RREG32(IH_CNTL);
3430         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3431
3432         ih_cntl |= ENABLE_INTR;
3433         ih_rb_cntl |= IH_RB_ENABLE;
3434         WREG32(IH_CNTL, ih_cntl);
3435         WREG32(IH_RB_CNTL, ih_rb_cntl);
3436         rdev->ih.enabled = true;
3437 }
3438
3439 static void si_disable_interrupts(struct radeon_device *rdev)
3440 {
3441         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3442         u32 ih_cntl = RREG32(IH_CNTL);
3443
3444         ih_rb_cntl &= ~IH_RB_ENABLE;
3445         ih_cntl &= ~ENABLE_INTR;
3446         WREG32(IH_RB_CNTL, ih_rb_cntl);
3447         WREG32(IH_CNTL, ih_cntl);
3448         /* set rptr, wptr to 0 */
3449         WREG32(IH_RB_RPTR, 0);
3450         WREG32(IH_RB_WPTR, 0);
3451         rdev->ih.enabled = false;
3452         rdev->ih.rptr = 0;
3453 }
3454
3455 static void si_disable_interrupt_state(struct radeon_device *rdev)
3456 {
3457         u32 tmp;
3458
3459         WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3460         WREG32(CP_INT_CNTL_RING1, 0);
3461         WREG32(CP_INT_CNTL_RING2, 0);
3462         tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3463         WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
3464         tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3465         WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
3466         WREG32(GRBM_INT_CNTL, 0);
3467         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3468         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3469         if (rdev->num_crtc >= 4) {
3470                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3471                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3472         }
3473         if (rdev->num_crtc >= 6) {
3474                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3475                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3476         }
3477
3478         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3479         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3480         if (rdev->num_crtc >= 4) {
3481                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3482                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3483         }
3484         if (rdev->num_crtc >= 6) {
3485                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3486                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3487         }
3488
3489         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3490
3491         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3492         WREG32(DC_HPD1_INT_CONTROL, tmp);
3493         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3494         WREG32(DC_HPD2_INT_CONTROL, tmp);
3495         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3496         WREG32(DC_HPD3_INT_CONTROL, tmp);
3497         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3498         WREG32(DC_HPD4_INT_CONTROL, tmp);
3499         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3500         WREG32(DC_HPD5_INT_CONTROL, tmp);
3501         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3502         WREG32(DC_HPD6_INT_CONTROL, tmp);
3503
3504 }
3505
3506 static int si_irq_init(struct radeon_device *rdev)
3507 {
3508         int ret = 0;
3509         int rb_bufsz;
3510         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3511
3512         /* allocate ring */
3513         ret = r600_ih_ring_alloc(rdev);
3514         if (ret)
3515                 return ret;
3516
3517         /* disable irqs */
3518         si_disable_interrupts(rdev);
3519
3520         /* init rlc */
3521         ret = si_rlc_resume(rdev);
3522         if (ret) {
3523                 r600_ih_ring_fini(rdev);
3524                 return ret;
3525         }
3526
3527         /* setup interrupt control */
3528         /* set dummy read address to ring address */
3529         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3530         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3531         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3532          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3533          */
3534         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3535         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3536         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3537         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3538
3539         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3540         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3541
3542         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3543                       IH_WPTR_OVERFLOW_CLEAR |
3544                       (rb_bufsz << 1));
3545
3546         if (rdev->wb.enabled)
3547                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3548
3549         /* set the writeback address whether it's enabled or not */
3550         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3551         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3552
3553         WREG32(IH_RB_CNTL, ih_rb_cntl);
3554
3555         /* set rptr, wptr to 0 */
3556         WREG32(IH_RB_RPTR, 0);
3557         WREG32(IH_RB_WPTR, 0);
3558
3559         /* Default settings for IH_CNTL (disabled at first) */
3560         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3561         /* RPTR_REARM only works if msi's are enabled */
3562         if (rdev->msi_enabled)
3563                 ih_cntl |= RPTR_REARM;
3564         WREG32(IH_CNTL, ih_cntl);
3565
3566         /* force the active interrupt state to all disabled */
3567         si_disable_interrupt_state(rdev);
3568
3569         pci_set_master(rdev->pdev);
3570
3571         /* enable irqs */
3572         si_enable_interrupts(rdev);
3573
3574         return ret;
3575 }
3576
3577 int si_irq_set(struct radeon_device *rdev)
3578 {
3579         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3580         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
3581         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3582         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3583         u32 grbm_int_cntl = 0;
3584         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
3585         u32 dma_cntl, dma_cntl1;
3586
3587         if (!rdev->irq.installed) {
3588                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3589                 return -EINVAL;
3590         }
3591         /* don't enable anything if the ih is disabled */
3592         if (!rdev->ih.enabled) {
3593                 si_disable_interrupts(rdev);
3594                 /* force the active interrupt state to all disabled */
3595                 si_disable_interrupt_state(rdev);
3596                 return 0;
3597         }
3598
3599         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3600         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3601         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3602         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3603         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3604         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3605
3606         dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3607         dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3608
3609         /* enable CP interrupts on all rings */
3610         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3611                 DRM_DEBUG("si_irq_set: sw int gfx\n");
3612                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3613         }
3614         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
3615                 DRM_DEBUG("si_irq_set: sw int cp1\n");
3616                 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3617         }
3618         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
3619                 DRM_DEBUG("si_irq_set: sw int cp2\n");
3620                 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3621         }
3622         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3623                 DRM_DEBUG("si_irq_set: sw int dma\n");
3624                 dma_cntl |= TRAP_ENABLE;
3625         }
3626
3627         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3628                 DRM_DEBUG("si_irq_set: sw int dma1\n");
3629                 dma_cntl1 |= TRAP_ENABLE;
3630         }
3631         if (rdev->irq.crtc_vblank_int[0] ||
3632             atomic_read(&rdev->irq.pflip[0])) {
3633                 DRM_DEBUG("si_irq_set: vblank 0\n");
3634                 crtc1 |= VBLANK_INT_MASK;
3635         }
3636         if (rdev->irq.crtc_vblank_int[1] ||
3637             atomic_read(&rdev->irq.pflip[1])) {
3638                 DRM_DEBUG("si_irq_set: vblank 1\n");
3639                 crtc2 |= VBLANK_INT_MASK;
3640         }
3641         if (rdev->irq.crtc_vblank_int[2] ||
3642             atomic_read(&rdev->irq.pflip[2])) {
3643                 DRM_DEBUG("si_irq_set: vblank 2\n");
3644                 crtc3 |= VBLANK_INT_MASK;
3645         }
3646         if (rdev->irq.crtc_vblank_int[3] ||
3647             atomic_read(&rdev->irq.pflip[3])) {
3648                 DRM_DEBUG("si_irq_set: vblank 3\n");
3649                 crtc4 |= VBLANK_INT_MASK;
3650         }
3651         if (rdev->irq.crtc_vblank_int[4] ||
3652             atomic_read(&rdev->irq.pflip[4])) {
3653                 DRM_DEBUG("si_irq_set: vblank 4\n");
3654                 crtc5 |= VBLANK_INT_MASK;
3655         }
3656         if (rdev->irq.crtc_vblank_int[5] ||
3657             atomic_read(&rdev->irq.pflip[5])) {
3658                 DRM_DEBUG("si_irq_set: vblank 5\n");
3659                 crtc6 |= VBLANK_INT_MASK;
3660         }
3661         if (rdev->irq.hpd[0]) {
3662                 DRM_DEBUG("si_irq_set: hpd 1\n");
3663                 hpd1 |= DC_HPDx_INT_EN;
3664         }
3665         if (rdev->irq.hpd[1]) {
3666                 DRM_DEBUG("si_irq_set: hpd 2\n");
3667                 hpd2 |= DC_HPDx_INT_EN;
3668         }
3669         if (rdev->irq.hpd[2]) {
3670                 DRM_DEBUG("si_irq_set: hpd 3\n");
3671                 hpd3 |= DC_HPDx_INT_EN;
3672         }
3673         if (rdev->irq.hpd[3]) {
3674                 DRM_DEBUG("si_irq_set: hpd 4\n");
3675                 hpd4 |= DC_HPDx_INT_EN;
3676         }
3677         if (rdev->irq.hpd[4]) {
3678                 DRM_DEBUG("si_irq_set: hpd 5\n");
3679                 hpd5 |= DC_HPDx_INT_EN;
3680         }
3681         if (rdev->irq.hpd[5]) {
3682                 DRM_DEBUG("si_irq_set: hpd 6\n");
3683                 hpd6 |= DC_HPDx_INT_EN;
3684         }
3685
3686         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3687         WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
3688         WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
3689
3690         WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
3691         WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
3692
3693         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3694
3695         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3696         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3697         if (rdev->num_crtc >= 4) {
3698                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3699                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3700         }
3701         if (rdev->num_crtc >= 6) {
3702                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3703                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3704         }
3705
3706         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3707         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
3708         if (rdev->num_crtc >= 4) {
3709                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3710                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3711         }
3712         if (rdev->num_crtc >= 6) {
3713                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3714                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3715         }
3716
3717         WREG32(DC_HPD1_INT_CONTROL, hpd1);
3718         WREG32(DC_HPD2_INT_CONTROL, hpd2);
3719         WREG32(DC_HPD3_INT_CONTROL, hpd3);
3720         WREG32(DC_HPD4_INT_CONTROL, hpd4);
3721         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3722         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3723
3724         return 0;
3725 }
3726
3727 static inline void si_irq_ack(struct radeon_device *rdev)
3728 {
3729         u32 tmp;
3730
3731         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3732         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3733         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3734         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3735         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3736         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3737         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3738         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3739         if (rdev->num_crtc >= 4) {
3740                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3741                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3742         }
3743         if (rdev->num_crtc >= 6) {
3744                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3745                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3746         }
3747
3748         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3749                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3750         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3751                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3752         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
3753                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3754         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
3755                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3756         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3757                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3758         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3759                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3760
3761         if (rdev->num_crtc >= 4) {
3762                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3763                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3764                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3765                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3766                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3767                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3768                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3769                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3770                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3771                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3772                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3773                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3774         }
3775
3776         if (rdev->num_crtc >= 6) {
3777                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3778                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3779                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3780                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3781                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3782                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3783                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3784                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3785                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3786                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3787                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3788                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3789         }
3790
3791         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3792                 tmp = RREG32(DC_HPD1_INT_CONTROL);
3793                 tmp |= DC_HPDx_INT_ACK;
3794                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3795         }
3796         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3797                 tmp = RREG32(DC_HPD2_INT_CONTROL);
3798                 tmp |= DC_HPDx_INT_ACK;
3799                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3800         }
3801         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3802                 tmp = RREG32(DC_HPD3_INT_CONTROL);
3803                 tmp |= DC_HPDx_INT_ACK;
3804                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3805         }
3806         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3807                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3808                 tmp |= DC_HPDx_INT_ACK;
3809                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3810         }
3811         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3812                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3813                 tmp |= DC_HPDx_INT_ACK;
3814                 WREG32(DC_HPD5_INT_CONTROL, tmp);
3815         }
3816         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3817                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3818                 tmp |= DC_HPDx_INT_ACK;
3819                 WREG32(DC_HPD6_INT_CONTROL, tmp);
3820         }
3821 }
3822
3823 static void si_irq_disable(struct radeon_device *rdev)
3824 {
3825         si_disable_interrupts(rdev);
3826         /* Wait and acknowledge irq */
3827         mdelay(1);
3828         si_irq_ack(rdev);
3829         si_disable_interrupt_state(rdev);
3830 }
3831
3832 static void si_irq_suspend(struct radeon_device *rdev)
3833 {
3834         si_irq_disable(rdev);
3835         si_rlc_stop(rdev);
3836 }
3837
3838 static void si_irq_fini(struct radeon_device *rdev)
3839 {
3840         si_irq_suspend(rdev);
3841         r600_ih_ring_fini(rdev);
3842 }
3843
3844 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
3845 {
3846         u32 wptr, tmp;
3847
3848         if (rdev->wb.enabled)
3849                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3850         else
3851                 wptr = RREG32(IH_RB_WPTR);
3852
3853         if (wptr & RB_OVERFLOW) {
3854                 /* When a ring buffer overflow happen start parsing interrupt
3855                  * from the last not overwritten vector (wptr + 16). Hopefully
3856                  * this should allow us to catchup.
3857                  */
3858                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3859                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3860                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3861                 tmp = RREG32(IH_RB_CNTL);
3862                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3863                 WREG32(IH_RB_CNTL, tmp);
3864         }
3865         return (wptr & rdev->ih.ptr_mask);
3866 }
3867
3868 /*        SI IV Ring
3869  * Each IV ring entry is 128 bits:
3870  * [7:0]    - interrupt source id
3871  * [31:8]   - reserved
3872  * [59:32]  - interrupt source data
3873  * [63:60]  - reserved
3874  * [71:64]  - RINGID
3875  * [79:72]  - VMID
3876  * [127:80] - reserved
3877  */
3878 int si_irq_process(struct radeon_device *rdev)
3879 {
3880         u32 wptr;
3881         u32 rptr;
3882         u32 src_id, src_data, ring_id;
3883         u32 ring_index;
3884         bool queue_hotplug = false;
3885
3886         if (!rdev->ih.enabled || rdev->shutdown)
3887                 return IRQ_NONE;
3888
3889         wptr = si_get_ih_wptr(rdev);
3890
3891 restart_ih:
3892         /* is somebody else already processing irqs? */
3893         if (atomic_xchg(&rdev->ih.lock, 1))
3894                 return IRQ_NONE;
3895
3896         rptr = rdev->ih.rptr;
3897         DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3898
3899         /* Order reading of wptr vs. reading of IH ring data */
3900         rmb();
3901
3902         /* display interrupts */
3903         si_irq_ack(rdev);
3904
3905         while (rptr != wptr) {
3906                 /* wptr/rptr are in bytes! */
3907                 ring_index = rptr / 4;
3908                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3909                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3910                 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
3911
3912                 switch (src_id) {
3913                 case 1: /* D1 vblank/vline */
3914                         switch (src_data) {
3915                         case 0: /* D1 vblank */
3916                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3917                                         if (rdev->irq.crtc_vblank_int[0]) {
3918                                                 drm_handle_vblank(rdev->ddev, 0);
3919                                                 rdev->pm.vblank_sync = true;
3920                                                 wake_up(&rdev->irq.vblank_queue);
3921                                         }
3922                                         if (atomic_read(&rdev->irq.pflip[0]))
3923                                                 radeon_crtc_handle_flip(rdev, 0);
3924                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3925                                         DRM_DEBUG("IH: D1 vblank\n");
3926                                 }
3927                                 break;
3928                         case 1: /* D1 vline */
3929                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3930                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3931                                         DRM_DEBUG("IH: D1 vline\n");
3932                                 }
3933                                 break;
3934                         default:
3935                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3936                                 break;
3937                         }
3938                         break;
3939                 case 2: /* D2 vblank/vline */
3940                         switch (src_data) {
3941                         case 0: /* D2 vblank */
3942                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3943                                         if (rdev->irq.crtc_vblank_int[1]) {
3944                                                 drm_handle_vblank(rdev->ddev, 1);
3945                                                 rdev->pm.vblank_sync = true;
3946                                                 wake_up(&rdev->irq.vblank_queue);
3947                                         }
3948                                         if (atomic_read(&rdev->irq.pflip[1]))
3949                                                 radeon_crtc_handle_flip(rdev, 1);
3950                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3951                                         DRM_DEBUG("IH: D2 vblank\n");
3952                                 }
3953                                 break;
3954                         case 1: /* D2 vline */
3955                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3956                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3957                                         DRM_DEBUG("IH: D2 vline\n");
3958                                 }
3959                                 break;
3960                         default:
3961                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3962                                 break;
3963                         }
3964                         break;
3965                 case 3: /* D3 vblank/vline */
3966                         switch (src_data) {
3967                         case 0: /* D3 vblank */
3968                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3969                                         if (rdev->irq.crtc_vblank_int[2]) {
3970                                                 drm_handle_vblank(rdev->ddev, 2);
3971                                                 rdev->pm.vblank_sync = true;
3972                                                 wake_up(&rdev->irq.vblank_queue);
3973                                         }
3974                                         if (atomic_read(&rdev->irq.pflip[2]))
3975                                                 radeon_crtc_handle_flip(rdev, 2);
3976                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3977                                         DRM_DEBUG("IH: D3 vblank\n");
3978                                 }
3979                                 break;
3980                         case 1: /* D3 vline */
3981                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3982                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3983                                         DRM_DEBUG("IH: D3 vline\n");
3984                                 }
3985                                 break;
3986                         default:
3987                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3988                                 break;
3989                         }
3990                         break;
3991                 case 4: /* D4 vblank/vline */
3992                         switch (src_data) {
3993                         case 0: /* D4 vblank */
3994                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3995                                         if (rdev->irq.crtc_vblank_int[3]) {
3996                                                 drm_handle_vblank(rdev->ddev, 3);
3997                                                 rdev->pm.vblank_sync = true;
3998                                                 wake_up(&rdev->irq.vblank_queue);
3999                                         }
4000                                         if (atomic_read(&rdev->irq.pflip[3]))
4001                                                 radeon_crtc_handle_flip(rdev, 3);
4002                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
4003                                         DRM_DEBUG("IH: D4 vblank\n");
4004                                 }
4005                                 break;
4006                         case 1: /* D4 vline */
4007                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
4008                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
4009                                         DRM_DEBUG("IH: D4 vline\n");
4010                                 }
4011                                 break;
4012                         default:
4013                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4014                                 break;
4015                         }
4016                         break;
4017                 case 5: /* D5 vblank/vline */
4018                         switch (src_data) {
4019                         case 0: /* D5 vblank */
4020                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
4021                                         if (rdev->irq.crtc_vblank_int[4]) {
4022                                                 drm_handle_vblank(rdev->ddev, 4);
4023                                                 rdev->pm.vblank_sync = true;
4024                                                 wake_up(&rdev->irq.vblank_queue);
4025                                         }
4026                                         if (atomic_read(&rdev->irq.pflip[4]))
4027                                                 radeon_crtc_handle_flip(rdev, 4);
4028                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
4029                                         DRM_DEBUG("IH: D5 vblank\n");
4030                                 }
4031                                 break;
4032                         case 1: /* D5 vline */
4033                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
4034                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
4035                                         DRM_DEBUG("IH: D5 vline\n");
4036                                 }
4037                                 break;
4038                         default:
4039                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4040                                 break;
4041                         }
4042                         break;
4043                 case 6: /* D6 vblank/vline */
4044                         switch (src_data) {
4045                         case 0: /* D6 vblank */
4046                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
4047                                         if (rdev->irq.crtc_vblank_int[5]) {
4048                                                 drm_handle_vblank(rdev->ddev, 5);
4049                                                 rdev->pm.vblank_sync = true;
4050                                                 wake_up(&rdev->irq.vblank_queue);
4051                                         }
4052                                         if (atomic_read(&rdev->irq.pflip[5]))
4053                                                 radeon_crtc_handle_flip(rdev, 5);
4054                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
4055                                         DRM_DEBUG("IH: D6 vblank\n");
4056                                 }
4057                                 break;
4058                         case 1: /* D6 vline */
4059                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
4060                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
4061                                         DRM_DEBUG("IH: D6 vline\n");
4062                                 }
4063                                 break;
4064                         default:
4065                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4066                                 break;
4067                         }
4068                         break;
4069                 case 42: /* HPD hotplug */
4070                         switch (src_data) {
4071                         case 0:
4072                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
4073                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
4074                                         queue_hotplug = true;
4075                                         DRM_DEBUG("IH: HPD1\n");
4076                                 }
4077                                 break;
4078                         case 1:
4079                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
4080                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
4081                                         queue_hotplug = true;
4082                                         DRM_DEBUG("IH: HPD2\n");
4083                                 }
4084                                 break;
4085                         case 2:
4086                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4087                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
4088                                         queue_hotplug = true;
4089                                         DRM_DEBUG("IH: HPD3\n");
4090                                 }
4091                                 break;
4092                         case 3:
4093                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4094                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
4095                                         queue_hotplug = true;
4096                                         DRM_DEBUG("IH: HPD4\n");
4097                                 }
4098                                 break;
4099                         case 4:
4100                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4101                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
4102                                         queue_hotplug = true;
4103                                         DRM_DEBUG("IH: HPD5\n");
4104                                 }
4105                                 break;
4106                         case 5:
4107                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4108                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
4109                                         queue_hotplug = true;
4110                                         DRM_DEBUG("IH: HPD6\n");
4111                                 }
4112                                 break;
4113                         default:
4114                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4115                                 break;
4116                         }
4117                         break;
4118                 case 146:
4119                 case 147:
4120                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4121                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
4122                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4123                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4124                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4125                         /* reset addr and status */
4126                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4127                         break;
4128                 case 176: /* RINGID0 CP_INT */
4129                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4130                         break;
4131                 case 177: /* RINGID1 CP_INT */
4132                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4133                         break;
4134                 case 178: /* RINGID2 CP_INT */
4135                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4136                         break;
4137                 case 181: /* CP EOP event */
4138                         DRM_DEBUG("IH: CP EOP\n");
4139                         switch (ring_id) {
4140                         case 0:
4141                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4142                                 break;
4143                         case 1:
4144                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4145                                 break;
4146                         case 2:
4147                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4148                                 break;
4149                         }
4150                         break;
4151                 case 224: /* DMA trap event */
4152                         DRM_DEBUG("IH: DMA trap\n");
4153                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4154                         break;
4155                 case 233: /* GUI IDLE */
4156                         DRM_DEBUG("IH: GUI idle\n");
4157                         break;
4158                 case 244: /* DMA trap event */
4159                         DRM_DEBUG("IH: DMA1 trap\n");
4160                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4161                         break;
4162                 default:
4163                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4164                         break;
4165                 }
4166
4167                 /* wptr/rptr are in bytes! */
4168                 rptr += 16;
4169                 rptr &= rdev->ih.ptr_mask;
4170         }
4171         if (queue_hotplug)
4172                 schedule_work(&rdev->hotplug_work);
4173         rdev->ih.rptr = rptr;
4174         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4175         atomic_set(&rdev->ih.lock, 0);
4176
4177         /* make sure wptr hasn't changed while processing */
4178         wptr = si_get_ih_wptr(rdev);
4179         if (wptr != rptr)
4180                 goto restart_ih;
4181
4182         return IRQ_HANDLED;
4183 }
4184
4185 /**
4186  * si_copy_dma - copy pages using the DMA engine
4187  *
4188  * @rdev: radeon_device pointer
4189  * @src_offset: src GPU address
4190  * @dst_offset: dst GPU address
4191  * @num_gpu_pages: number of GPU pages to xfer
4192  * @fence: radeon fence object
4193  *
4194  * Copy GPU paging using the DMA engine (SI).
4195  * Used by the radeon ttm implementation to move pages if
4196  * registered as the asic copy callback.
4197  */
4198 int si_copy_dma(struct radeon_device *rdev,
4199                 uint64_t src_offset, uint64_t dst_offset,
4200                 unsigned num_gpu_pages,
4201                 struct radeon_fence **fence)
4202 {
4203         struct radeon_semaphore *sem = NULL;
4204         int ring_index = rdev->asic->copy.dma_ring_index;
4205         struct radeon_ring *ring = &rdev->ring[ring_index];
4206         u32 size_in_bytes, cur_size_in_bytes;
4207         int i, num_loops;
4208         int r = 0;
4209
4210         r = radeon_semaphore_create(rdev, &sem);
4211         if (r) {
4212                 DRM_ERROR("radeon: moving bo (%d).\n", r);
4213                 return r;
4214         }
4215
4216         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4217         num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
4218         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
4219         if (r) {
4220                 DRM_ERROR("radeon: moving bo (%d).\n", r);
4221                 radeon_semaphore_free(rdev, &sem, NULL);
4222                 return r;
4223         }
4224
4225         if (radeon_fence_need_sync(*fence, ring->idx)) {
4226                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
4227                                             ring->idx);
4228                 radeon_fence_note_sync(*fence, ring->idx);
4229         } else {
4230                 radeon_semaphore_free(rdev, &sem, NULL);
4231         }
4232
4233         for (i = 0; i < num_loops; i++) {
4234                 cur_size_in_bytes = size_in_bytes;
4235                 if (cur_size_in_bytes > 0xFFFFF)
4236                         cur_size_in_bytes = 0xFFFFF;
4237                 size_in_bytes -= cur_size_in_bytes;
4238                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
4239                 radeon_ring_write(ring, dst_offset & 0xffffffff);
4240                 radeon_ring_write(ring, src_offset & 0xffffffff);
4241                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
4242                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
4243                 src_offset += cur_size_in_bytes;
4244                 dst_offset += cur_size_in_bytes;
4245         }
4246
4247         r = radeon_fence_emit(rdev, fence, ring->idx);
4248         if (r) {
4249                 radeon_ring_unlock_undo(rdev, ring);
4250                 return r;
4251         }
4252
4253         radeon_ring_unlock_commit(rdev, ring);
4254         radeon_semaphore_free(rdev, &sem, *fence);
4255
4256         return r;
4257 }
4258
4259 /*
4260  * startup/shutdown callbacks
4261  */
4262 static int si_startup(struct radeon_device *rdev)
4263 {
4264         struct radeon_ring *ring;
4265         int r;
4266
4267         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
4268             !rdev->rlc_fw || !rdev->mc_fw) {
4269                 r = si_init_microcode(rdev);
4270                 if (r) {
4271                         DRM_ERROR("Failed to load firmware!\n");
4272                         return r;
4273                 }
4274         }
4275
4276         r = si_mc_load_microcode(rdev);
4277         if (r) {
4278                 DRM_ERROR("Failed to load MC firmware!\n");
4279                 return r;
4280         }
4281
4282         r = r600_vram_scratch_init(rdev);
4283         if (r)
4284                 return r;
4285
4286         si_mc_program(rdev);
4287         r = si_pcie_gart_enable(rdev);
4288         if (r)
4289                 return r;
4290         si_gpu_init(rdev);
4291
4292 #if 0
4293         r = evergreen_blit_init(rdev);
4294         if (r) {
4295                 r600_blit_fini(rdev);
4296                 rdev->asic->copy = NULL;
4297                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
4298         }
4299 #endif
4300         /* allocate rlc buffers */
4301         r = si_rlc_init(rdev);
4302         if (r) {
4303                 DRM_ERROR("Failed to init rlc BOs!\n");
4304                 return r;
4305         }
4306
4307         /* allocate wb buffer */
4308         r = radeon_wb_init(rdev);
4309         if (r)
4310                 return r;
4311
4312         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4313         if (r) {
4314                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4315                 return r;
4316         }
4317
4318         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4319         if (r) {
4320                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4321                 return r;
4322         }
4323
4324         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4325         if (r) {
4326                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4327                 return r;
4328         }
4329
4330         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
4331         if (r) {
4332                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4333                 return r;
4334         }
4335
4336         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4337         if (r) {
4338                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
4339                 return r;
4340         }
4341
4342         /* Enable IRQ */
4343         r = si_irq_init(rdev);
4344         if (r) {
4345                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
4346                 radeon_irq_kms_fini(rdev);
4347                 return r;
4348         }
4349         si_irq_set(rdev);
4350
4351         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4352         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
4353                              CP_RB0_RPTR, CP_RB0_WPTR,
4354                              0, 0xfffff, RADEON_CP_PACKET2);
4355         if (r)
4356                 return r;
4357
4358         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4359         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
4360                              CP_RB1_RPTR, CP_RB1_WPTR,
4361                              0, 0xfffff, RADEON_CP_PACKET2);
4362         if (r)
4363                 return r;
4364
4365         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4366         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
4367                              CP_RB2_RPTR, CP_RB2_WPTR,
4368                              0, 0xfffff, RADEON_CP_PACKET2);
4369         if (r)
4370                 return r;
4371
4372         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4373         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
4374                              DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
4375                              DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
4376                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4377         if (r)
4378                 return r;
4379
4380         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4381         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
4382                              DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
4383                              DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
4384                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
4385         if (r)
4386                 return r;
4387
4388         r = si_cp_load_microcode(rdev);
4389         if (r)
4390                 return r;
4391         r = si_cp_resume(rdev);
4392         if (r)
4393                 return r;
4394
4395         r = cayman_dma_resume(rdev);
4396         if (r)
4397                 return r;
4398
4399         r = radeon_ib_pool_init(rdev);
4400         if (r) {
4401                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4402                 return r;
4403         }
4404
4405         r = radeon_vm_manager_init(rdev);
4406         if (r) {
4407                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
4408                 return r;
4409         }
4410
4411         return 0;
4412 }
4413
4414 int si_resume(struct radeon_device *rdev)
4415 {
4416         int r;
4417
4418         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
4419          * posting will perform necessary task to bring back GPU into good
4420          * shape.
4421          */
4422         /* post card */
4423         atom_asic_init(rdev->mode_info.atom_context);
4424
4425         rdev->accel_working = true;
4426         r = si_startup(rdev);
4427         if (r) {
4428                 DRM_ERROR("si startup failed on resume\n");
4429                 rdev->accel_working = false;
4430                 return r;
4431         }
4432
4433         return r;
4434
4435 }
4436
4437 int si_suspend(struct radeon_device *rdev)
4438 {
4439         si_cp_enable(rdev, false);
4440         cayman_dma_stop(rdev);
4441         si_irq_suspend(rdev);
4442         radeon_wb_disable(rdev);
4443         si_pcie_gart_disable(rdev);
4444         return 0;
4445 }
4446
4447 /* Plan is to move initialization in that function and use
4448  * helper function so that radeon_device_init pretty much
4449  * do nothing more than calling asic specific function. This
4450  * should also allow to remove a bunch of callback function
4451  * like vram_info.
4452  */
4453 int si_init(struct radeon_device *rdev)
4454 {
4455         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4456         int r;
4457
4458         /* Read BIOS */
4459         if (!radeon_get_bios(rdev)) {
4460                 if (ASIC_IS_AVIVO(rdev))
4461                         return -EINVAL;
4462         }
4463         /* Must be an ATOMBIOS */
4464         if (!rdev->is_atom_bios) {
4465                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
4466                 return -EINVAL;
4467         }
4468         r = radeon_atombios_init(rdev);
4469         if (r)
4470                 return r;
4471
4472         /* Post card if necessary */
4473         if (!radeon_card_posted(rdev)) {
4474                 if (!rdev->bios) {
4475                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4476                         return -EINVAL;
4477                 }
4478                 DRM_INFO("GPU not posted. posting now...\n");
4479                 atom_asic_init(rdev->mode_info.atom_context);
4480         }
4481         /* Initialize scratch registers */
4482         si_scratch_init(rdev);
4483         /* Initialize surface registers */
4484         radeon_surface_init(rdev);
4485         /* Initialize clocks */
4486         radeon_get_clock_info(rdev->ddev);
4487
4488         /* Fence driver */
4489         r = radeon_fence_driver_init(rdev);
4490         if (r)
4491                 return r;
4492
4493         /* initialize memory controller */
4494         r = si_mc_init(rdev);
4495         if (r)
4496                 return r;
4497         /* Memory manager */
4498         r = radeon_bo_init(rdev);
4499         if (r)
4500                 return r;
4501
4502         r = radeon_irq_kms_init(rdev);
4503         if (r)
4504                 return r;
4505
4506         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4507         ring->ring_obj = NULL;
4508         r600_ring_init(rdev, ring, 1024 * 1024);
4509
4510         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
4511         ring->ring_obj = NULL;
4512         r600_ring_init(rdev, ring, 1024 * 1024);
4513
4514         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
4515         ring->ring_obj = NULL;
4516         r600_ring_init(rdev, ring, 1024 * 1024);
4517
4518         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
4519         ring->ring_obj = NULL;
4520         r600_ring_init(rdev, ring, 64 * 1024);
4521
4522         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
4523         ring->ring_obj = NULL;
4524         r600_ring_init(rdev, ring, 64 * 1024);
4525
4526         rdev->ih.ring_obj = NULL;
4527         r600_ih_ring_init(rdev, 64 * 1024);
4528
4529         r = r600_pcie_gart_init(rdev);
4530         if (r)
4531                 return r;
4532
4533         rdev->accel_working = true;
4534         r = si_startup(rdev);
4535         if (r) {
4536                 dev_err(rdev->dev, "disabling GPU acceleration\n");
4537                 si_cp_fini(rdev);
4538                 cayman_dma_fini(rdev);
4539                 si_irq_fini(rdev);
4540                 si_rlc_fini(rdev);
4541                 radeon_wb_fini(rdev);
4542                 radeon_ib_pool_fini(rdev);
4543                 radeon_vm_manager_fini(rdev);
4544                 radeon_irq_kms_fini(rdev);
4545                 si_pcie_gart_fini(rdev);
4546                 rdev->accel_working = false;
4547         }
4548
4549         /* Don't start up if the MC ucode is missing.
4550          * The default clocks and voltages before the MC ucode
4551          * is loaded are not suffient for advanced operations.
4552          */
4553         if (!rdev->mc_fw) {
4554                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4555                 return -EINVAL;
4556         }
4557
4558         return 0;
4559 }
4560
4561 void si_fini(struct radeon_device *rdev)
4562 {
4563 #if 0
4564         r600_blit_fini(rdev);
4565 #endif
4566         si_cp_fini(rdev);
4567         cayman_dma_fini(rdev);
4568         si_irq_fini(rdev);
4569         si_rlc_fini(rdev);
4570         radeon_wb_fini(rdev);
4571         radeon_vm_manager_fini(rdev);
4572         radeon_ib_pool_fini(rdev);
4573         radeon_irq_kms_fini(rdev);
4574         si_pcie_gart_fini(rdev);
4575         r600_vram_scratch_fini(rdev);
4576         radeon_gem_fini(rdev);
4577         radeon_fence_driver_fini(rdev);
4578         radeon_bo_fini(rdev);
4579         radeon_atombios_fini(rdev);
4580         kfree(rdev->bios);
4581         rdev->bios = NULL;
4582 }
4583
4584 /**
4585  * si_get_gpu_clock - return GPU clock counter snapshot
4586  *
4587  * @rdev: radeon_device pointer
4588  *
4589  * Fetches a GPU clock counter snapshot (SI).
4590  * Returns the 64 bit clock counter snapshot.
4591  */
4592 uint64_t si_get_gpu_clock(struct radeon_device *rdev)
4593 {
4594         uint64_t clock;
4595
4596         mutex_lock(&rdev->gpu_clock_mutex);
4597         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4598         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4599                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4600         mutex_unlock(&rdev->gpu_clock_mutex);
4601         return clock;
4602 }