drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_R600           "radeon/R600_uvd.bin"
  44 #define FIRMWARE_RS780          "radeon/RS780_uvd.bin"
  45 #define FIRMWARE_RV770          "radeon/RV770_uvd.bin"
  46 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  47 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  48 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  49 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  50 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  51
  52 MODULE_FIRMWARE(FIRMWARE_R600);
  53 MODULE_FIRMWARE(FIRMWARE_RS780);
  54 MODULE_FIRMWARE(FIRMWARE_RV770);
  55 MODULE_FIRMWARE(FIRMWARE_RV710);
  56 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  57 MODULE_FIRMWARE(FIRMWARE_SUMO);
  58 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  59 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  60
  61 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  62
  63 int radeon_uvd_init(struct radeon_device *rdev)
  64 {
  65         unsigned long bo_size;
  66         const char *fw_name;
  67         int i, r;
  68
  69         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  70
  71         switch (rdev->family) {
  72         case CHIP_RV610:
  73         case CHIP_RV630:
  74         case CHIP_RV670:
  75         case CHIP_RV620:
  76         case CHIP_RV635:
  77                 fw_name = FIRMWARE_R600;
  78                 break;
  79
  80         case CHIP_RS780:
  81         case CHIP_RS880:
  82                 fw_name = FIRMWARE_RS780;
  83                 break;
  84
  85         case CHIP_RV770:
  86                 fw_name = FIRMWARE_RV770;
  87                 break;
  88
  89         case CHIP_RV710:
  90         case CHIP_RV730:
  91         case CHIP_RV740:
  92                 fw_name = FIRMWARE_RV710;
  93                 break;
  94
  95         case CHIP_CYPRESS:
  96         case CHIP_HEMLOCK:
  97         case CHIP_JUNIPER:
  98         case CHIP_REDWOOD:
  99         case CHIP_CEDAR:
 100                 fw_name = FIRMWARE_CYPRESS;
 101                 break;
 102
 103         case CHIP_SUMO:
 104         case CHIP_SUMO2:
 105         case CHIP_PALM:
 106         case CHIP_CAYMAN:
 107         case CHIP_BARTS:
 108         case CHIP_TURKS:
 109         case CHIP_CAICOS:
 110                 fw_name = FIRMWARE_SUMO;
 111                 break;
 112
 113         case CHIP_TAHITI:
 114         case CHIP_VERDE:
 115         case CHIP_PITCAIRN:
 116         case CHIP_ARUBA:
 117         case CHIP_OLAND:
 118                 fw_name = FIRMWARE_TAHITI;
 119                 break;
 120
 121         case CHIP_BONAIRE:
 122         case CHIP_KABINI:
 123         case CHIP_KAVERI:
 124         case CHIP_HAWAII:
 125         case CHIP_MULLINS:
 126                 fw_name = FIRMWARE_BONAIRE;
 127                 break;
 128
 129         default:
 130                 return -EINVAL;
 131         }
 132
 133         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 134         if (r) {
 135                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 136                         fw_name);
 137                 return r;
 138         }
 139
 140         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 141                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 142         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 143                              RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->uvd.vcpu_bo);
 144         if (r) {
 145                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 146                 return r;
 147         }
 148
 149         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 150         if (r) {
 151                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 152                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 153                 return r;
 154         }
 155
 156         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 157                           &rdev->uvd.gpu_addr);
 158         if (r) {
 159                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 160                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 161                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 162                 return r;
 163         }
 164
 165         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 166         if (r) {
 167                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 168                 return r;
 169         }
 170
 171         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 172
 173         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 174                 atomic_set(&rdev->uvd.handles[i], 0);
 175                 rdev->uvd.filp[i] = NULL;
 176                 rdev->uvd.img_size[i] = 0;
 177         }
 178
 179         return 0;
 180 }
 181
 182 void radeon_uvd_fini(struct radeon_device *rdev)
 183 {
 184         int r;
 185
 186         if (rdev->uvd.vcpu_bo == NULL)
 187                 return;
 188
 189         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 190         if (!r) {
 191                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 192                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 193                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 194         }
 195
 196         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 197
 198         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
 199
 200         release_firmware(rdev->uvd_fw);
 201 }
 202
 203 int radeon_uvd_suspend(struct radeon_device *rdev)
 204 {
 205         unsigned size;
 206         void *ptr;
 207         int i;
 208
 209         if (rdev->uvd.vcpu_bo == NULL)
 210                 return 0;
 211
 212         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 213                 if (atomic_read(&rdev->uvd.handles[i]))
 214                         break;
 215
 216         if (i == RADEON_MAX_UVD_HANDLES)
 217                 return 0;
 218
 219         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 220         size -= rdev->uvd_fw->size;
 221
 222         ptr = rdev->uvd.cpu_addr;
 223         ptr += rdev->uvd_fw->size;
 224
 225         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 226         memcpy(rdev->uvd.saved_bo, ptr, size);
 227
 228         return 0;
 229 }
 230
 231 int radeon_uvd_resume(struct radeon_device *rdev)
 232 {
 233         unsigned size;
 234         void *ptr;
 235
 236         if (rdev->uvd.vcpu_bo == NULL)
 237                 return -EINVAL;
 238
 239         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 240
 241         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 242         size -= rdev->uvd_fw->size;
 243
 244         ptr = rdev->uvd.cpu_addr;
 245         ptr += rdev->uvd_fw->size;
 246
 247         if (rdev->uvd.saved_bo != NULL) {
 248                 memcpy(ptr, rdev->uvd.saved_bo, size);
 249                 kfree(rdev->uvd.saved_bo);
 250                 rdev->uvd.saved_bo = NULL;
 251         } else
 252                 memset(ptr, 0, size);
 253
 254         return 0;
 255 }
 256
 257 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 258 {
 259         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 260         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 261 }
 262
 263 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 264 {
 265         int i, r;
 266         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 267                 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 268                 if (handle != 0 && rdev->uvd.filp[i] == filp) {
 269                         struct radeon_fence *fence;
 270
 271                         radeon_uvd_note_usage(rdev);
 272
 273                         r = radeon_uvd_get_destroy_msg(rdev,
 274                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 275                         if (r) {
 276                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 277                                 continue;
 278                         }
 279
 280                         radeon_fence_wait(fence, false);
 281                         radeon_fence_unref(&fence);
 282
 283                         rdev->uvd.filp[i] = NULL;
 284                         atomic_set(&rdev->uvd.handles[i], 0);
 285                 }
 286         }
 287 }
 288
 289 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 290 {
 291         unsigned stream_type = msg[4];
 292         unsigned width = msg[6];
 293         unsigned height = msg[7];
 294         unsigned dpb_size = msg[9];
 295         unsigned pitch = msg[28];
 296
 297         unsigned width_in_mb = width / 16;
 298         unsigned height_in_mb = ALIGN(height / 16, 2);
 299
 300         unsigned image_size, tmp, min_dpb_size;
 301
 302         image_size = width * height;
 303         image_size += image_size / 2;
 304         image_size = ALIGN(image_size, 1024);
 305
 306         switch (stream_type) {
 307         case 0: /* H264 */
 308
 309                 /* reference picture buffer */
 310                 min_dpb_size = image_size * 17;
 311
 312                 /* macroblock context buffer */
 313                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 314
 315                 /* IT surface buffer */
 316                 min_dpb_size += width_in_mb * height_in_mb * 32;
 317                 break;
 318
 319         case 1: /* VC1 */
 320
 321                 /* reference picture buffer */
 322                 min_dpb_size = image_size * 3;
 323
 324                 /* CONTEXT_BUFFER */
 325                 min_dpb_size += width_in_mb * height_in_mb * 128;
 326
 327                 /* IT surface buffer */
 328                 min_dpb_size += width_in_mb * 64;
 329
 330                 /* DB surface buffer */
 331                 min_dpb_size += width_in_mb * 128;
 332
 333                 /* BP */
 334                 tmp = max(width_in_mb, height_in_mb);
 335                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 336                 break;
 337
 338         case 3: /* MPEG2 */
 339
 340                 /* reference picture buffer */
 341                 min_dpb_size = image_size * 3;
 342                 break;
 343
 344         case 4: /* MPEG4 */
 345
 346                 /* reference picture buffer */
 347                 min_dpb_size = image_size * 3;
 348
 349                 /* CM */
 350                 min_dpb_size += width_in_mb * height_in_mb * 64;
 351
 352                 /* IT surface buffer */
 353                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 354                 break;
 355
 356         default:
 357                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 358                 return -EINVAL;
 359         }
 360
 361         if (width > pitch) {
 362                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 363                 return -EINVAL;
 364         }
 365
 366         if (dpb_size < min_dpb_size) {
 367                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 368                           dpb_size, min_dpb_size);
 369                 return -EINVAL;
 370         }
 371
 372         buf_sizes[0x1] = dpb_size;
 373         buf_sizes[0x2] = image_size;
 374         return 0;
 375 }
 376
 377 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 378                              unsigned offset, unsigned buf_sizes[])
 379 {
 380         int32_t *msg, msg_type, handle;
 381         unsigned img_size = 0;
 382         void *ptr;
 383
 384         int i, r;
 385
 386         if (offset & 0x3F) {
 387                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 388                 return -EINVAL;
 389         }
 390
 391         if (bo->tbo.sync_obj) {
 392                 r = radeon_fence_wait(bo->tbo.sync_obj, false);
 393                 if (r) {
 394                         DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
 395                         return r;
 396                 }
 397         }
 398
 399         r = radeon_bo_kmap(bo, &ptr);
 400         if (r) {
 401                 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
 402                 return r;
 403         }
 404
 405         msg = ptr + offset;
 406
 407         msg_type = msg[1];
 408         handle = msg[2];
 409
 410         if (handle == 0) {
 411                 DRM_ERROR("Invalid UVD handle!\n");
 412                 return -EINVAL;
 413         }
 414
 415         if (msg_type == 1) {
 416                 /* it's a decode msg, calc buffer sizes */
 417                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 418                 /* calc image size (width * height) */
 419                 img_size = msg[6] * msg[7];
 420                 radeon_bo_kunmap(bo);
 421                 if (r)
 422                         return r;
 423
 424         } else if (msg_type == 2) {
 425                 /* it's a destroy msg, free the handle */
 426                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 427                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 428                 radeon_bo_kunmap(bo);
 429                 return 0;
 430         } else {
 431                 /* it's a create msg, calc image size (width * height) */
 432                 img_size = msg[7] * msg[8];
 433                 radeon_bo_kunmap(bo);
 434
 435                 if (msg_type != 0) {
 436                         DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 437                         return -EINVAL;
 438                 }
 439
 440                 /* it's a create msg, no special handling needed */
 441         }
 442
 443         /* create or decode, validate the handle */
 444         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 445                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 446                         return 0;
 447         }
 448
 449         /* handle not found try to alloc a new one */
 450         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 451                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 452                         p->rdev->uvd.filp[i] = p->filp;
 453                         p->rdev->uvd.img_size[i] = img_size;
 454                         return 0;
 455                 }
 456         }
 457
 458         DRM_ERROR("No more free UVD handles!\n");
 459         return -EINVAL;
 460 }
 461
 462 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 463                                int data0, int data1,
 464                                unsigned buf_sizes[], bool *has_msg_cmd)
 465 {
 466         struct radeon_cs_chunk *relocs_chunk;
 467         struct radeon_cs_reloc *reloc;
 468         unsigned idx, cmd, offset;
 469         uint64_t start, end;
 470         int r;
 471
 472         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 473         offset = radeon_get_ib_value(p, data0);
 474         idx = radeon_get_ib_value(p, data1);
 475         if (idx >= relocs_chunk->length_dw) {
 476                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 477                           idx, relocs_chunk->length_dw);
 478                 return -EINVAL;
 479         }
 480
 481         reloc = p->relocs_ptr[(idx / 4)];
 482         start = reloc->gpu_offset;
 483         end = start + radeon_bo_size(reloc->robj);
 484         start += offset;
 485
 486         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 487         p->ib.ptr[data1] = start >> 32;
 488
 489         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 490
 491         if (cmd < 0x4) {
 492                 if (end <= start) {
 493                         DRM_ERROR("invalid reloc offset %X!\n", offset);
 494                         return -EINVAL;
 495                 }
 496                 if ((end - start) < buf_sizes[cmd]) {
 497                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 498                                   (unsigned)(end - start), buf_sizes[cmd]);
 499                         return -EINVAL;
 500                 }
 501
 502         } else if (cmd != 0x100) {
 503                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 504                 return -EINVAL;
 505         }
 506
 507         if ((start >> 28) != ((end - 1) >> 28)) {
 508                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 509                           start, end);
 510                 return -EINVAL;
 511         }
 512
 513         /* TODO: is this still necessary on NI+ ? */
 514         if ((cmd == 0 || cmd == 0x3) &&
 515             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 516                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 517                           start, end);
 518                 return -EINVAL;
 519         }
 520
 521         if (cmd == 0) {
 522                 if (*has_msg_cmd) {
 523                         DRM_ERROR("More than one message in a UVD-IB!\n");
 524                         return -EINVAL;
 525                 }
 526                 *has_msg_cmd = true;
 527                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 528                 if (r)
 529                         return r;
 530         } else if (!*has_msg_cmd) {
 531                 DRM_ERROR("Message needed before other commands are send!\n");
 532                 return -EINVAL;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 539                              struct radeon_cs_packet *pkt,
 540                              int *data0, int *data1,
 541                              unsigned buf_sizes[],
 542                              bool *has_msg_cmd)
 543 {
 544         int i, r;
 545
 546         p->idx++;
 547         for (i = 0; i <= pkt->count; ++i) {
 548                 switch (pkt->reg + i*4) {
 549                 case UVD_GPCOM_VCPU_DATA0:
 550                         *data0 = p->idx;
 551                         break;
 552                 case UVD_GPCOM_VCPU_DATA1:
 553                         *data1 = p->idx;
 554                         break;
 555                 case UVD_GPCOM_VCPU_CMD:
 556                         r = radeon_uvd_cs_reloc(p, *data0, *data1,
 557                                                 buf_sizes, has_msg_cmd);
 558                         if (r)
 559                                 return r;
 560                         break;
 561                 case UVD_ENGINE_CNTL:
 562                         break;
 563                 default:
 564                         DRM_ERROR("Invalid reg 0x%X!\n",
 565                                   pkt->reg + i*4);
 566                         return -EINVAL;
 567                 }
 568                 p->idx++;
 569         }
 570         return 0;
 571 }
 572
 573 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 574 {
 575         struct radeon_cs_packet pkt;
 576         int r, data0 = 0, data1 = 0;
 577
 578         /* does the IB has a msg command */
 579         bool has_msg_cmd = false;
 580
 581         /* minimum buffer sizes */
 582         unsigned buf_sizes[] = {
 583                 [0x00000000]    =       2048,
 584                 [0x00000001]    =       32 * 1024 * 1024,
 585                 [0x00000002]    =       2048 * 1152 * 3,
 586                 [0x00000003]    =       2048,
 587         };
 588
 589         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 590                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 591                           p->chunks[p->chunk_ib_idx].length_dw);
 592                 return -EINVAL;
 593         }
 594
 595         if (p->chunk_relocs_idx == -1) {
 596                 DRM_ERROR("No relocation chunk !\n");
 597                 return -EINVAL;
 598         }
 599
 600
 601         do {
 602                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 603                 if (r)
 604                         return r;
 605                 switch (pkt.type) {
 606                 case RADEON_PACKET_TYPE0:
 607                         r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
 608                                               buf_sizes, &has_msg_cmd);
 609                         if (r)
 610                                 return r;
 611                         break;
 612                 case RADEON_PACKET_TYPE2:
 613                         p->idx += pkt.count + 2;
 614                         break;
 615                 default:
 616                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 617                         return -EINVAL;
 618                 }
 619         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 620
 621         if (!has_msg_cmd) {
 622                 DRM_ERROR("UVD-IBs need a msg command!\n");
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 630                                int ring, struct radeon_bo *bo,
 631                                struct radeon_fence **fence)
 632 {
 633         struct ttm_validate_buffer tv;
 634         struct ww_acquire_ctx ticket;
 635         struct list_head head;
 636         struct radeon_ib ib;
 637         uint64_t addr;
 638         int i, r;
 639
 640         memset(&tv, 0, sizeof(tv));
 641         tv.bo = &bo->tbo;
 642
 643         INIT_LIST_HEAD(&head);
 644         list_add(&tv.head, &head);
 645
 646         r = ttm_eu_reserve_buffers(&ticket, &head);
 647         if (r)
 648                 return r;
 649
 650         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 651         radeon_uvd_force_into_uvd_segment(bo);
 652
 653         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 654         if (r)
 655                 goto err;
 656
 657         r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
 658         if (r)
 659                 goto err;
 660
 661         addr = radeon_bo_gpu_offset(bo);
 662         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 663         ib.ptr[1] = addr;
 664         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 665         ib.ptr[3] = addr >> 32;
 666         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 667         ib.ptr[5] = 0;
 668         for (i = 6; i < 16; ++i)
 669                 ib.ptr[i] = PACKET2(0);
 670         ib.length_dw = 16;
 671
 672         r = radeon_ib_schedule(rdev, &ib, NULL, false);
 673         if (r)
 674                 goto err;
 675         ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 676
 677         if (fence)
 678                 *fence = radeon_fence_ref(ib.fence);
 679
 680         radeon_ib_free(rdev, &ib);
 681         radeon_bo_unref(&bo);
 682         return 0;
 683
 684 err:
 685         ttm_eu_backoff_reservation(&ticket, &head);
 686         return r;
 687 }
 688
 689 /* multiple fence commands without any stream commands in between can
 690    crash the vcpu so just try to emmit a dummy create/destroy msg to
 691    avoid this */
 692 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 693                               uint32_t handle, struct radeon_fence **fence)
 694 {
 695         struct radeon_bo *bo;
 696         uint32_t *msg;
 697         int r, i;
 698
 699         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 700                              RADEON_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 701         if (r)
 702                 return r;
 703
 704         r = radeon_bo_reserve(bo, false);
 705         if (r) {
 706                 radeon_bo_unref(&bo);
 707                 return r;
 708         }
 709
 710         r = radeon_bo_kmap(bo, (void **)&msg);
 711         if (r) {
 712                 radeon_bo_unreserve(bo);
 713                 radeon_bo_unref(&bo);
 714                 return r;
 715         }
 716
 717         /* stitch together an UVD create msg */
 718         msg[0] = cpu_to_le32(0x00000de4);
 719         msg[1] = cpu_to_le32(0x00000000);
 720         msg[2] = cpu_to_le32(handle);
 721         msg[3] = cpu_to_le32(0x00000000);
 722         msg[4] = cpu_to_le32(0x00000000);
 723         msg[5] = cpu_to_le32(0x00000000);
 724         msg[6] = cpu_to_le32(0x00000000);
 725         msg[7] = cpu_to_le32(0x00000780);
 726         msg[8] = cpu_to_le32(0x00000440);
 727         msg[9] = cpu_to_le32(0x00000000);
 728         msg[10] = cpu_to_le32(0x01b37000);
 729         for (i = 11; i < 1024; ++i)
 730                 msg[i] = cpu_to_le32(0x0);
 731
 732         radeon_bo_kunmap(bo);
 733         radeon_bo_unreserve(bo);
 734
 735         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 736 }
 737
 738 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 739                                uint32_t handle, struct radeon_fence **fence)
 740 {
 741         struct radeon_bo *bo;
 742         uint32_t *msg;
 743         int r, i;
 744
 745         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 746                              RADEON_GEM_DOMAIN_VRAM, 0, NULL, &bo);
 747         if (r)
 748                 return r;
 749
 750         r = radeon_bo_reserve(bo, false);
 751         if (r) {
 752                 radeon_bo_unref(&bo);
 753                 return r;
 754         }
 755
 756         r = radeon_bo_kmap(bo, (void **)&msg);
 757         if (r) {
 758                 radeon_bo_unreserve(bo);
 759                 radeon_bo_unref(&bo);
 760                 return r;
 761         }
 762
 763         /* stitch together an UVD destroy msg */
 764         msg[0] = cpu_to_le32(0x00000de4);
 765         msg[1] = cpu_to_le32(0x00000002);
 766         msg[2] = cpu_to_le32(handle);
 767         msg[3] = cpu_to_le32(0x00000000);
 768         for (i = 4; i < 1024; ++i)
 769                 msg[i] = cpu_to_le32(0x0);
 770
 771         radeon_bo_kunmap(bo);
 772         radeon_bo_unreserve(bo);
 773
 774         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 775 }
 776
 777 /**
 778  * radeon_uvd_count_handles - count number of open streams
 779  *
 780  * @rdev: radeon_device pointer
 781  * @sd: number of SD streams
 782  * @hd: number of HD streams
 783  *
 784  * Count the number of open SD/HD streams as a hint for power mangement
 785  */
 786 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 787                                      unsigned *sd, unsigned *hd)
 788 {
 789         unsigned i;
 790
 791         *sd = 0;
 792         *hd = 0;
 793
 794         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 795                 if (!atomic_read(&rdev->uvd.handles[i]))
 796                         continue;
 797
 798                 if (rdev->uvd.img_size[i] >= 720*576)
 799                         ++(*hd);
 800                 else
 801                         ++(*sd);
 802         }
 803 }
 804
 805 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 806 {
 807         struct radeon_device *rdev =
 808                 container_of(work, struct radeon_device, uvd.idle_work.work);
 809
 810         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 811                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 812                         radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
 813                                                  &rdev->pm.dpm.hd);
 814                         radeon_dpm_enable_uvd(rdev, false);
 815                 } else {
 816                         radeon_set_uvd_clocks(rdev, 0, 0);
 817                 }
 818         } else {
 819                 schedule_delayed_work(&rdev->uvd.idle_work,
 820                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 821         }
 822 }
 823
 824 void radeon_uvd_note_usage(struct radeon_device *rdev)
 825 {
 826         bool streams_changed = false;
 827         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 828         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 829                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 830
 831         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 832                 unsigned hd = 0, sd = 0;
 833                 radeon_uvd_count_handles(rdev, &sd, &hd);
 834                 if ((rdev->pm.dpm.sd != sd) ||
 835                     (rdev->pm.dpm.hd != hd)) {
 836                         rdev->pm.dpm.sd = sd;
 837                         rdev->pm.dpm.hd = hd;
 838                         /* disable this for now */
 839                         /*streams_changed = true;*/
 840                 }
 841         }
 842
 843         if (set_clocks || streams_changed) {
 844                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 845                         radeon_dpm_enable_uvd(rdev, true);
 846                 } else {
 847                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 848                 }
 849         }
 850 }
 851
 852 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 853                                               unsigned target_freq,
 854                                               unsigned pd_min,
 855                                               unsigned pd_even)
 856 {
 857         unsigned post_div = vco_freq / target_freq;
 858
 859         /* adjust to post divider minimum value */
 860         if (post_div < pd_min)
 861                 post_div = pd_min;
 862
 863         /* we alway need a frequency less than or equal the target */
 864         if ((vco_freq / post_div) > target_freq)
 865                 post_div += 1;
 866
 867         /* post dividers above a certain value must be even */
 868         if (post_div > pd_even && post_div % 2)
 869                 post_div += 1;
 870
 871         return post_div;
 872 }
 873
 874 /**
 875  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 876  *
 877  * @rdev: radeon_device pointer
 878  * @vclk: wanted VCLK
 879  * @dclk: wanted DCLK
 880  * @vco_min: minimum VCO frequency
 881  * @vco_max: maximum VCO frequency
 882  * @fb_factor: factor to multiply vco freq with
 883  * @fb_mask: limit and bitmask for feedback divider
 884  * @pd_min: post divider minimum
 885  * @pd_max: post divider maximum
 886  * @pd_even: post divider must be even above this value
 887  * @optimal_fb_div: resulting feedback divider
 888  * @optimal_vclk_div: resulting vclk post divider
 889  * @optimal_dclk_div: resulting dclk post divider
 890  *
 891  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 892  * Returns zero on success -EINVAL on error.
 893  */
 894 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 895                                   unsigned vclk, unsigned dclk,
 896                                   unsigned vco_min, unsigned vco_max,
 897                                   unsigned fb_factor, unsigned fb_mask,
 898                                   unsigned pd_min, unsigned pd_max,
 899                                   unsigned pd_even,
 900                                   unsigned *optimal_fb_div,
 901                                   unsigned *optimal_vclk_div,
 902                                   unsigned *optimal_dclk_div)
 903 {
 904         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 905
 906         /* start off with something large */
 907         unsigned optimal_score = ~0;
 908
 909         /* loop through vco from low to high */
 910         vco_min = max(max(vco_min, vclk), dclk);
 911         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 912
 913                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 914                 unsigned vclk_div, dclk_div, score;
 915
 916                 do_div(fb_div, ref_freq);
 917
 918                 /* fb div out of range ? */
 919                 if (fb_div > fb_mask)
 920                         break; /* it can oly get worse */
 921
 922                 fb_div &= fb_mask;
 923
 924                 /* calc vclk divider with current vco freq */
 925                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 926                                                          pd_min, pd_even);
 927                 if (vclk_div > pd_max)
 928                         break; /* vco is too big, it has to stop */
 929
 930                 /* calc dclk divider with current vco freq */
 931                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 932                                                          pd_min, pd_even);
 933                 if (vclk_div > pd_max)
 934                         break; /* vco is too big, it has to stop */
 935
 936                 /* calc score with current vco freq */
 937                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 938
 939                 /* determine if this vco setting is better than current optimal settings */
 940                 if (score < optimal_score) {
 941                         *optimal_fb_div = fb_div;
 942                         *optimal_vclk_div = vclk_div;
 943                         *optimal_dclk_div = dclk_div;
 944                         optimal_score = score;
 945                         if (optimal_score == 0)
 946                                 break; /* it can't get better than this */
 947                 }
 948         }
 949
 950         /* did we found a valid setup ? */
 951         if (optimal_score == ~0)
 952                 return -EINVAL;
 953
 954         return 0;
 955 }
 956
 957 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 958                                 unsigned cg_upll_func_cntl)
 959 {
 960         unsigned i;
 961
 962         /* make sure UPLL_CTLREQ is deasserted */
 963         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 964
 965         mdelay(10);
 966
 967         /* assert UPLL_CTLREQ */
 968         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 969
 970         /* wait for CTLACK and CTLACK2 to get asserted */
 971         for (i = 0; i < 100; ++i) {
 972                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 973                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 974                         break;
 975                 mdelay(10);
 976         }
 977
 978         /* deassert UPLL_CTLREQ */
 979         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 980
 981         if (i == 100) {
 982                 DRM_ERROR("Timeout setting UVD clocks!\n");
 983                 return -ETIMEDOUT;
 984         }
 985
 986         return 0;
 987 }