2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35 static const char *radeon_pm_state_type_name[5] = {
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
55 int found_instance = -1;
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
60 if (found_instance == instance)
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
102 if (rdev->pm.active_crtc_count > 1)
103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
143 struct radeon_bo *bo, *n;
145 if (list_empty(&rdev->gem.objects))
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 static void radeon_set_power_state(struct radeon_device *rdev)
167 bool misc_after = false;
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
201 radeon_sync_with_vblank(rdev);
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
208 radeon_pm_prepare(rdev);
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
223 /* set memory clock */
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
236 radeon_pm_finish(rdev);
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
253 mutex_lock(&rdev->ddev->struct_mutex);
254 down_write(&rdev->pm.mclk_lock);
255 mutex_lock(&rdev->ring_lock);
257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
263 r = radeon_fence_wait_empty_locked(rdev, i);
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
273 radeon_unmap_vram_bos(rdev);
275 if (rdev->irq.installed) {
276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
284 radeon_set_power_state(rdev);
286 if (rdev->irq.installed) {
287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
302 mutex_unlock(&rdev->ring_lock);
303 up_write(&rdev->pm.mclk_lock);
304 mutex_unlock(&rdev->ddev->struct_mutex);
307 static void radeon_pm_print_states(struct radeon_device *rdev)
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
330 clock_info->sclk * 10);
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
345 struct drm_device *ddev = dev_get_drvdata(dev);
346 struct radeon_device *rdev = ddev->dev_private;
347 int cp = rdev->pm.profile;
349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
352 (cp == PM_PROFILE_MID) ? "mid" :
353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
364 mutex_lock(&rdev->pm.mutex);
365 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 if (strncmp("default", buf, strlen("default")) == 0)
367 rdev->pm.profile = PM_PROFILE_DEFAULT;
368 else if (strncmp("auto", buf, strlen("auto")) == 0)
369 rdev->pm.profile = PM_PROFILE_AUTO;
370 else if (strncmp("low", buf, strlen("low")) == 0)
371 rdev->pm.profile = PM_PROFILE_LOW;
372 else if (strncmp("mid", buf, strlen("mid")) == 0)
373 rdev->pm.profile = PM_PROFILE_MID;
374 else if (strncmp("high", buf, strlen("high")) == 0)
375 rdev->pm.profile = PM_PROFILE_HIGH;
380 radeon_pm_update_profile(rdev);
381 radeon_pm_set_clocks(rdev);
386 mutex_unlock(&rdev->pm.mutex);
391 static ssize_t radeon_get_pm_method(struct device *dev,
392 struct device_attribute *attr,
395 struct drm_device *ddev = dev_get_drvdata(dev);
396 struct radeon_device *rdev = ddev->dev_private;
397 int pm = rdev->pm.pm_method;
399 return snprintf(buf, PAGE_SIZE, "%s\n",
400 (pm == PM_METHOD_DYNPM) ? "dynpm" :
401 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
404 static ssize_t radeon_set_pm_method(struct device *dev,
405 struct device_attribute *attr,
409 struct drm_device *ddev = dev_get_drvdata(dev);
410 struct radeon_device *rdev = ddev->dev_private;
412 /* we don't support the legacy modes with dpm */
413 if (rdev->pm.pm_method == PM_METHOD_DPM) {
418 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
419 mutex_lock(&rdev->pm.mutex);
420 rdev->pm.pm_method = PM_METHOD_DYNPM;
421 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
422 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
423 mutex_unlock(&rdev->pm.mutex);
424 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
425 mutex_lock(&rdev->pm.mutex);
427 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
428 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
429 rdev->pm.pm_method = PM_METHOD_PROFILE;
430 mutex_unlock(&rdev->pm.mutex);
431 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
436 radeon_pm_compute_clocks(rdev);
441 static ssize_t radeon_get_dpm_state(struct device *dev,
442 struct device_attribute *attr,
445 struct drm_device *ddev = dev_get_drvdata(dev);
446 struct radeon_device *rdev = ddev->dev_private;
447 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
449 return snprintf(buf, PAGE_SIZE, "%s\n",
450 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
451 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
454 static ssize_t radeon_set_dpm_state(struct device *dev,
455 struct device_attribute *attr,
459 struct drm_device *ddev = dev_get_drvdata(dev);
460 struct radeon_device *rdev = ddev->dev_private;
462 mutex_lock(&rdev->pm.mutex);
463 if (strncmp("battery", buf, strlen("battery")) == 0)
464 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
465 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
466 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
467 else if (strncmp("performance", buf, strlen("performance")) == 0)
468 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
470 mutex_unlock(&rdev->pm.mutex);
474 mutex_unlock(&rdev->pm.mutex);
475 radeon_pm_compute_clocks(rdev);
480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
481 struct device_attribute *attr,
484 struct drm_device *ddev = dev_get_drvdata(dev);
485 struct radeon_device *rdev = ddev->dev_private;
486 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
488 return snprintf(buf, PAGE_SIZE, "%s\n",
489 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
490 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
494 struct device_attribute *attr,
498 struct drm_device *ddev = dev_get_drvdata(dev);
499 struct radeon_device *rdev = ddev->dev_private;
500 enum radeon_dpm_forced_level level;
503 mutex_lock(&rdev->pm.mutex);
504 if (strncmp("low", buf, strlen("low")) == 0) {
505 level = RADEON_DPM_FORCED_LEVEL_LOW;
506 } else if (strncmp("high", buf, strlen("high")) == 0) {
507 level = RADEON_DPM_FORCED_LEVEL_HIGH;
508 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
509 level = RADEON_DPM_FORCED_LEVEL_AUTO;
514 if (rdev->asic->dpm.force_performance_level) {
515 if (rdev->pm.dpm.thermal_active) {
519 ret = radeon_dpm_force_performance_level(rdev, level);
524 mutex_unlock(&rdev->pm.mutex);
529 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
530 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
531 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
532 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
533 radeon_get_dpm_forced_performance_level,
534 radeon_set_dpm_forced_performance_level);
536 static ssize_t radeon_hwmon_show_temp(struct device *dev,
537 struct device_attribute *attr,
540 struct radeon_device *rdev = dev_get_drvdata(dev);
543 if (rdev->asic->pm.get_temperature)
544 temp = radeon_get_temperature(rdev);
548 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
551 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
552 struct device_attribute *attr,
555 struct radeon_device *rdev = dev_get_drvdata(dev);
556 int hyst = to_sensor_dev_attr(attr)->index;
560 temp = rdev->pm.dpm.thermal.min_temp;
562 temp = rdev->pm.dpm.thermal.max_temp;
564 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
567 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
568 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
569 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
571 static struct attribute *hwmon_attributes[] = {
572 &sensor_dev_attr_temp1_input.dev_attr.attr,
573 &sensor_dev_attr_temp1_crit.dev_attr.attr,
574 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
578 static umode_t hwmon_attributes_visible(struct kobject *kobj,
579 struct attribute *attr, int index)
581 struct device *dev = container_of(kobj, struct device, kobj);
582 struct radeon_device *rdev = dev_get_drvdata(dev);
584 /* Skip limit attributes if DPM is not enabled */
585 if (rdev->pm.pm_method != PM_METHOD_DPM &&
586 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
587 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
593 static const struct attribute_group hwmon_attrgroup = {
594 .attrs = hwmon_attributes,
595 .is_visible = hwmon_attributes_visible,
598 static const struct attribute_group *hwmon_groups[] = {
603 static int radeon_hwmon_init(struct radeon_device *rdev)
606 struct device *hwmon_dev;
608 switch (rdev->pm.int_thermal_type) {
609 case THERMAL_TYPE_RV6XX:
610 case THERMAL_TYPE_RV770:
611 case THERMAL_TYPE_EVERGREEN:
612 case THERMAL_TYPE_NI:
613 case THERMAL_TYPE_SUMO:
614 case THERMAL_TYPE_SI:
615 case THERMAL_TYPE_CI:
616 case THERMAL_TYPE_KV:
617 if (rdev->asic->pm.get_temperature == NULL)
619 hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
622 if (IS_ERR(hwmon_dev)) {
623 err = PTR_ERR(hwmon_dev);
625 "Unable to register hwmon device: %d\n", err);
635 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
637 struct radeon_device *rdev =
638 container_of(work, struct radeon_device,
639 pm.dpm.thermal.work);
640 /* switch to the thermal state */
641 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
643 if (!rdev->pm.dpm_enabled)
646 if (rdev->asic->pm.get_temperature) {
647 int temp = radeon_get_temperature(rdev);
649 if (temp < rdev->pm.dpm.thermal.min_temp)
650 /* switch back the user state */
651 dpm_state = rdev->pm.dpm.user_state;
653 if (rdev->pm.dpm.thermal.high_to_low)
654 /* switch back the user state */
655 dpm_state = rdev->pm.dpm.user_state;
657 mutex_lock(&rdev->pm.mutex);
658 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
659 rdev->pm.dpm.thermal_active = true;
661 rdev->pm.dpm.thermal_active = false;
662 rdev->pm.dpm.state = dpm_state;
663 mutex_unlock(&rdev->pm.mutex);
665 radeon_pm_compute_clocks(rdev);
668 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
669 enum radeon_pm_state_type dpm_state)
672 struct radeon_ps *ps;
674 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
677 /* check if the vblank period is too short to adjust the mclk */
678 if (single_display && rdev->asic->dpm.vblank_too_short) {
679 if (radeon_dpm_vblank_too_short(rdev))
680 single_display = false;
683 /* certain older asics have a separare 3D performance state,
684 * so try that first if the user selected performance
686 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
687 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
688 /* balanced states don't exist at the moment */
689 if (dpm_state == POWER_STATE_TYPE_BALANCED)
690 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
693 /* Pick the best power state based on current conditions */
694 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
695 ps = &rdev->pm.dpm.ps[i];
696 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
699 case POWER_STATE_TYPE_BATTERY:
700 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
701 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
708 case POWER_STATE_TYPE_BALANCED:
709 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
710 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
717 case POWER_STATE_TYPE_PERFORMANCE:
718 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
719 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
726 /* internal states */
727 case POWER_STATE_TYPE_INTERNAL_UVD:
728 if (rdev->pm.dpm.uvd_ps)
729 return rdev->pm.dpm.uvd_ps;
732 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
733 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
736 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
737 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
740 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
741 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
744 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
745 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
748 case POWER_STATE_TYPE_INTERNAL_BOOT:
749 return rdev->pm.dpm.boot_ps;
750 case POWER_STATE_TYPE_INTERNAL_THERMAL:
751 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
754 case POWER_STATE_TYPE_INTERNAL_ACPI:
755 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
758 case POWER_STATE_TYPE_INTERNAL_ULV:
759 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
762 case POWER_STATE_TYPE_INTERNAL_3DPERF:
763 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
770 /* use a fallback state if we didn't match */
772 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
773 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
775 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
776 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
777 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
778 if (rdev->pm.dpm.uvd_ps) {
779 return rdev->pm.dpm.uvd_ps;
781 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
784 case POWER_STATE_TYPE_INTERNAL_THERMAL:
785 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
787 case POWER_STATE_TYPE_INTERNAL_ACPI:
788 dpm_state = POWER_STATE_TYPE_BATTERY;
790 case POWER_STATE_TYPE_BATTERY:
791 case POWER_STATE_TYPE_BALANCED:
792 case POWER_STATE_TYPE_INTERNAL_3DPERF:
793 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
802 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
805 struct radeon_ps *ps;
806 enum radeon_pm_state_type dpm_state;
809 /* if dpm init failed */
810 if (!rdev->pm.dpm_enabled)
813 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
814 /* add other state override checks here */
815 if ((!rdev->pm.dpm.thermal_active) &&
816 (!rdev->pm.dpm.uvd_active))
817 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
819 dpm_state = rdev->pm.dpm.state;
821 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
823 rdev->pm.dpm.requested_ps = ps;
827 /* no need to reprogram if nothing changed unless we are on BTC+ */
828 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
829 /* vce just modifies an existing state so force a change */
830 if (ps->vce_active != rdev->pm.dpm.vce_active)
832 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
833 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
834 * all we need to do is update the display configuration.
836 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
837 /* update display watermarks based on new power state */
838 radeon_bandwidth_update(rdev);
839 /* update displays */
840 radeon_dpm_display_configuration_changed(rdev);
841 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
842 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
846 /* for BTC+ if the num crtcs hasn't changed and state is the same,
847 * nothing to do, if the num crtcs is > 1 and state is the same,
848 * update display configuration.
850 if (rdev->pm.dpm.new_active_crtcs ==
851 rdev->pm.dpm.current_active_crtcs) {
854 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
855 (rdev->pm.dpm.new_active_crtc_count > 1)) {
856 /* update display watermarks based on new power state */
857 radeon_bandwidth_update(rdev);
858 /* update displays */
859 radeon_dpm_display_configuration_changed(rdev);
860 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
861 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
869 if (radeon_dpm == 1) {
870 printk("switching from power state:\n");
871 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
872 printk("switching to power state:\n");
873 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
876 mutex_lock(&rdev->ddev->struct_mutex);
877 down_write(&rdev->pm.mclk_lock);
878 mutex_lock(&rdev->ring_lock);
880 /* update whether vce is active */
881 ps->vce_active = rdev->pm.dpm.vce_active;
883 ret = radeon_dpm_pre_set_power_state(rdev);
887 /* update display watermarks based on new power state */
888 radeon_bandwidth_update(rdev);
889 /* update displays */
890 radeon_dpm_display_configuration_changed(rdev);
892 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
893 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
895 /* wait for the rings to drain */
896 for (i = 0; i < RADEON_NUM_RINGS; i++) {
897 struct radeon_ring *ring = &rdev->ring[i];
899 radeon_fence_wait_empty_locked(rdev, i);
902 /* program the new power state */
903 radeon_dpm_set_power_state(rdev);
905 /* update current power state */
906 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
908 radeon_dpm_post_set_power_state(rdev);
910 if (rdev->asic->dpm.force_performance_level) {
911 if (rdev->pm.dpm.thermal_active) {
912 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
913 /* force low perf level for thermal */
914 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
915 /* save the user's level */
916 rdev->pm.dpm.forced_level = level;
918 /* otherwise, user selected level */
919 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
924 mutex_unlock(&rdev->ring_lock);
925 up_write(&rdev->pm.mclk_lock);
926 mutex_unlock(&rdev->ddev->struct_mutex);
929 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
931 enum radeon_pm_state_type dpm_state;
933 if (rdev->asic->dpm.powergate_uvd) {
934 mutex_lock(&rdev->pm.mutex);
935 /* don't powergate anything if we
936 have active but pause streams */
937 enable |= rdev->pm.dpm.sd > 0;
938 enable |= rdev->pm.dpm.hd > 0;
939 /* enable/disable UVD */
940 radeon_dpm_powergate_uvd(rdev, !enable);
941 mutex_unlock(&rdev->pm.mutex);
944 mutex_lock(&rdev->pm.mutex);
945 rdev->pm.dpm.uvd_active = true;
946 /* disable this for now */
948 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
949 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
950 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
952 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
953 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
954 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
958 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
959 rdev->pm.dpm.state = dpm_state;
960 mutex_unlock(&rdev->pm.mutex);
962 mutex_lock(&rdev->pm.mutex);
963 rdev->pm.dpm.uvd_active = false;
964 mutex_unlock(&rdev->pm.mutex);
967 radeon_pm_compute_clocks(rdev);
971 static void radeon_pm_suspend_old(struct radeon_device *rdev)
973 mutex_lock(&rdev->pm.mutex);
974 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
975 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
976 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
978 mutex_unlock(&rdev->pm.mutex);
980 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
983 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
985 mutex_lock(&rdev->pm.mutex);
987 radeon_dpm_disable(rdev);
988 /* reset the power state */
989 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
990 rdev->pm.dpm_enabled = false;
991 mutex_unlock(&rdev->pm.mutex);
994 void radeon_pm_suspend(struct radeon_device *rdev)
996 if (rdev->pm.pm_method == PM_METHOD_DPM)
997 radeon_pm_suspend_dpm(rdev);
999 radeon_pm_suspend_old(rdev);
1002 static void radeon_pm_resume_old(struct radeon_device *rdev)
1004 /* set up the default clocks if the MC ucode is loaded */
1005 if ((rdev->family >= CHIP_BARTS) &&
1006 (rdev->family <= CHIP_CAYMAN) &&
1008 if (rdev->pm.default_vddc)
1009 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1010 SET_VOLTAGE_TYPE_ASIC_VDDC);
1011 if (rdev->pm.default_vddci)
1012 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1013 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1014 if (rdev->pm.default_sclk)
1015 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1016 if (rdev->pm.default_mclk)
1017 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1019 /* asic init will reset the default power state */
1020 mutex_lock(&rdev->pm.mutex);
1021 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1022 rdev->pm.current_clock_mode_index = 0;
1023 rdev->pm.current_sclk = rdev->pm.default_sclk;
1024 rdev->pm.current_mclk = rdev->pm.default_mclk;
1025 if (rdev->pm.power_state) {
1026 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1027 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1029 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1030 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1031 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1032 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1033 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1035 mutex_unlock(&rdev->pm.mutex);
1036 radeon_pm_compute_clocks(rdev);
1039 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1043 /* asic init will reset to the boot state */
1044 mutex_lock(&rdev->pm.mutex);
1045 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1046 radeon_dpm_setup_asic(rdev);
1047 ret = radeon_dpm_enable(rdev);
1048 mutex_unlock(&rdev->pm.mutex);
1050 goto dpm_resume_fail;
1051 rdev->pm.dpm_enabled = true;
1052 radeon_pm_compute_clocks(rdev);
1056 DRM_ERROR("radeon: dpm resume failed\n");
1057 if ((rdev->family >= CHIP_BARTS) &&
1058 (rdev->family <= CHIP_CAYMAN) &&
1060 if (rdev->pm.default_vddc)
1061 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1062 SET_VOLTAGE_TYPE_ASIC_VDDC);
1063 if (rdev->pm.default_vddci)
1064 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1065 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1066 if (rdev->pm.default_sclk)
1067 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1068 if (rdev->pm.default_mclk)
1069 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1073 void radeon_pm_resume(struct radeon_device *rdev)
1075 if (rdev->pm.pm_method == PM_METHOD_DPM)
1076 radeon_pm_resume_dpm(rdev);
1078 radeon_pm_resume_old(rdev);
1081 static int radeon_pm_init_old(struct radeon_device *rdev)
1085 rdev->pm.profile = PM_PROFILE_DEFAULT;
1086 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1087 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1088 rdev->pm.dynpm_can_upclock = true;
1089 rdev->pm.dynpm_can_downclock = true;
1090 rdev->pm.default_sclk = rdev->clock.default_sclk;
1091 rdev->pm.default_mclk = rdev->clock.default_mclk;
1092 rdev->pm.current_sclk = rdev->clock.default_sclk;
1093 rdev->pm.current_mclk = rdev->clock.default_mclk;
1094 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1097 if (rdev->is_atom_bios)
1098 radeon_atombios_get_power_modes(rdev);
1100 radeon_combios_get_power_modes(rdev);
1101 radeon_pm_print_states(rdev);
1102 radeon_pm_init_profile(rdev);
1103 /* set up the default clocks if the MC ucode is loaded */
1104 if ((rdev->family >= CHIP_BARTS) &&
1105 (rdev->family <= CHIP_CAYMAN) &&
1107 if (rdev->pm.default_vddc)
1108 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1109 SET_VOLTAGE_TYPE_ASIC_VDDC);
1110 if (rdev->pm.default_vddci)
1111 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1112 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1113 if (rdev->pm.default_sclk)
1114 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1115 if (rdev->pm.default_mclk)
1116 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1120 /* set up the internal thermal sensor if applicable */
1121 ret = radeon_hwmon_init(rdev);
1125 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1127 if (rdev->pm.num_power_states > 1) {
1128 /* where's the best place to put these? */
1129 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1131 DRM_ERROR("failed to create device file for power profile\n");
1132 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1134 DRM_ERROR("failed to create device file for power method\n");
1136 if (radeon_debugfs_pm_init(rdev)) {
1137 DRM_ERROR("Failed to register debugfs file for PM!\n");
1140 DRM_INFO("radeon: power management initialized\n");
1146 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1150 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1151 printk("== power state %d ==\n", i);
1152 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1156 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1160 /* default to balanced state */
1161 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1162 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1163 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1164 rdev->pm.default_sclk = rdev->clock.default_sclk;
1165 rdev->pm.default_mclk = rdev->clock.default_mclk;
1166 rdev->pm.current_sclk = rdev->clock.default_sclk;
1167 rdev->pm.current_mclk = rdev->clock.default_mclk;
1168 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1170 if (rdev->bios && rdev->is_atom_bios)
1171 radeon_atombios_get_power_modes(rdev);
1175 /* set up the internal thermal sensor if applicable */
1176 ret = radeon_hwmon_init(rdev);
1180 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1181 mutex_lock(&rdev->pm.mutex);
1182 radeon_dpm_init(rdev);
1183 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1184 if (radeon_dpm == 1)
1185 radeon_dpm_print_power_states(rdev);
1186 radeon_dpm_setup_asic(rdev);
1187 ret = radeon_dpm_enable(rdev);
1188 mutex_unlock(&rdev->pm.mutex);
1191 rdev->pm.dpm_enabled = true;
1193 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1195 DRM_ERROR("failed to create device file for dpm state\n");
1196 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1198 DRM_ERROR("failed to create device file for dpm state\n");
1199 /* XXX: these are noops for dpm but are here for backwards compat */
1200 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1202 DRM_ERROR("failed to create device file for power profile\n");
1203 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1205 DRM_ERROR("failed to create device file for power method\n");
1207 if (radeon_debugfs_pm_init(rdev)) {
1208 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1211 DRM_INFO("radeon: dpm initialized\n");
1216 rdev->pm.dpm_enabled = false;
1217 if ((rdev->family >= CHIP_BARTS) &&
1218 (rdev->family <= CHIP_CAYMAN) &&
1220 if (rdev->pm.default_vddc)
1221 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1222 SET_VOLTAGE_TYPE_ASIC_VDDC);
1223 if (rdev->pm.default_vddci)
1224 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1225 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1226 if (rdev->pm.default_sclk)
1227 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1228 if (rdev->pm.default_mclk)
1229 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1231 DRM_ERROR("radeon: dpm initialization failed\n");
1235 int radeon_pm_init(struct radeon_device *rdev)
1237 /* enable dpm on rv6xx+ */
1238 switch (rdev->family) {
1250 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1252 rdev->pm.pm_method = PM_METHOD_PROFILE;
1253 else if ((rdev->family >= CHIP_RV770) &&
1254 (!(rdev->flags & RADEON_IS_IGP)) &&
1256 rdev->pm.pm_method = PM_METHOD_PROFILE;
1257 else if (radeon_dpm == 1)
1258 rdev->pm.pm_method = PM_METHOD_DPM;
1260 rdev->pm.pm_method = PM_METHOD_PROFILE;
1284 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1286 rdev->pm.pm_method = PM_METHOD_PROFILE;
1287 else if ((rdev->family >= CHIP_RV770) &&
1288 (!(rdev->flags & RADEON_IS_IGP)) &&
1290 rdev->pm.pm_method = PM_METHOD_PROFILE;
1291 else if (radeon_dpm == 0)
1292 rdev->pm.pm_method = PM_METHOD_PROFILE;
1294 rdev->pm.pm_method = PM_METHOD_DPM;
1297 /* default to profile method */
1298 rdev->pm.pm_method = PM_METHOD_PROFILE;
1302 if (rdev->pm.pm_method == PM_METHOD_DPM)
1303 return radeon_pm_init_dpm(rdev);
1305 return radeon_pm_init_old(rdev);
1308 int radeon_pm_late_init(struct radeon_device *rdev)
1312 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1313 mutex_lock(&rdev->pm.mutex);
1314 ret = radeon_dpm_late_enable(rdev);
1315 mutex_unlock(&rdev->pm.mutex);
1320 static void radeon_pm_fini_old(struct radeon_device *rdev)
1322 if (rdev->pm.num_power_states > 1) {
1323 mutex_lock(&rdev->pm.mutex);
1324 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1325 rdev->pm.profile = PM_PROFILE_DEFAULT;
1326 radeon_pm_update_profile(rdev);
1327 radeon_pm_set_clocks(rdev);
1328 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1329 /* reset default clocks */
1330 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1331 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1332 radeon_pm_set_clocks(rdev);
1334 mutex_unlock(&rdev->pm.mutex);
1336 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1338 device_remove_file(rdev->dev, &dev_attr_power_profile);
1339 device_remove_file(rdev->dev, &dev_attr_power_method);
1342 if (rdev->pm.power_state)
1343 kfree(rdev->pm.power_state);
1346 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1348 if (rdev->pm.num_power_states > 1) {
1349 mutex_lock(&rdev->pm.mutex);
1350 radeon_dpm_disable(rdev);
1351 mutex_unlock(&rdev->pm.mutex);
1353 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1354 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1355 /* XXX backwards compat */
1356 device_remove_file(rdev->dev, &dev_attr_power_profile);
1357 device_remove_file(rdev->dev, &dev_attr_power_method);
1359 radeon_dpm_fini(rdev);
1361 if (rdev->pm.power_state)
1362 kfree(rdev->pm.power_state);
1365 void radeon_pm_fini(struct radeon_device *rdev)
1367 if (rdev->pm.pm_method == PM_METHOD_DPM)
1368 radeon_pm_fini_dpm(rdev);
1370 radeon_pm_fini_old(rdev);
1373 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1375 struct drm_device *ddev = rdev->ddev;
1376 struct drm_crtc *crtc;
1377 struct radeon_crtc *radeon_crtc;
1379 if (rdev->pm.num_power_states < 2)
1382 mutex_lock(&rdev->pm.mutex);
1384 rdev->pm.active_crtcs = 0;
1385 rdev->pm.active_crtc_count = 0;
1386 list_for_each_entry(crtc,
1387 &ddev->mode_config.crtc_list, head) {
1388 radeon_crtc = to_radeon_crtc(crtc);
1389 if (radeon_crtc->enabled) {
1390 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1391 rdev->pm.active_crtc_count++;
1395 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1396 radeon_pm_update_profile(rdev);
1397 radeon_pm_set_clocks(rdev);
1398 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1399 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1400 if (rdev->pm.active_crtc_count > 1) {
1401 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1402 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1404 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1405 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1406 radeon_pm_get_dynpm_state(rdev);
1407 radeon_pm_set_clocks(rdev);
1409 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1411 } else if (rdev->pm.active_crtc_count == 1) {
1412 /* TODO: Increase clocks if needed for current mode */
1414 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1415 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1416 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1417 radeon_pm_get_dynpm_state(rdev);
1418 radeon_pm_set_clocks(rdev);
1420 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1421 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1422 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1423 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1424 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1425 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1426 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1428 } else { /* count == 0 */
1429 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1430 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1432 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1433 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1434 radeon_pm_get_dynpm_state(rdev);
1435 radeon_pm_set_clocks(rdev);
1441 mutex_unlock(&rdev->pm.mutex);
1444 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1446 struct drm_device *ddev = rdev->ddev;
1447 struct drm_crtc *crtc;
1448 struct radeon_crtc *radeon_crtc;
1450 if (!rdev->pm.dpm_enabled)
1453 mutex_lock(&rdev->pm.mutex);
1455 /* update active crtc counts */
1456 rdev->pm.dpm.new_active_crtcs = 0;
1457 rdev->pm.dpm.new_active_crtc_count = 0;
1458 list_for_each_entry(crtc,
1459 &ddev->mode_config.crtc_list, head) {
1460 radeon_crtc = to_radeon_crtc(crtc);
1461 if (crtc->enabled) {
1462 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1463 rdev->pm.dpm.new_active_crtc_count++;
1467 /* update battery/ac status */
1468 if (power_supply_is_system_supplied() > 0)
1469 rdev->pm.dpm.ac_power = true;
1471 rdev->pm.dpm.ac_power = false;
1473 radeon_dpm_change_power_state_locked(rdev);
1475 mutex_unlock(&rdev->pm.mutex);
1479 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1481 if (rdev->pm.pm_method == PM_METHOD_DPM)
1482 radeon_pm_compute_clocks_dpm(rdev);
1484 radeon_pm_compute_clocks_old(rdev);
1487 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1489 int crtc, vpos, hpos, vbl_status;
1492 /* Iterate over all active crtc's. All crtc's must be in vblank,
1493 * otherwise return in_vbl == false.
1495 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1496 if (rdev->pm.active_crtcs & (1 << crtc)) {
1497 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1498 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1499 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1507 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1510 bool in_vbl = radeon_pm_in_vbl(rdev);
1512 if (in_vbl == false)
1513 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1514 finish ? "exit" : "entry");
1518 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1520 struct radeon_device *rdev;
1522 rdev = container_of(work, struct radeon_device,
1523 pm.dynpm_idle_work.work);
1525 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1526 mutex_lock(&rdev->pm.mutex);
1527 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1528 int not_processed = 0;
1531 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1532 struct radeon_ring *ring = &rdev->ring[i];
1535 not_processed += radeon_fence_count_emitted(rdev, i);
1536 if (not_processed >= 3)
1541 if (not_processed >= 3) { /* should upclock */
1542 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1543 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1544 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1545 rdev->pm.dynpm_can_upclock) {
1546 rdev->pm.dynpm_planned_action =
1547 DYNPM_ACTION_UPCLOCK;
1548 rdev->pm.dynpm_action_timeout = jiffies +
1549 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1551 } else if (not_processed == 0) { /* should downclock */
1552 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1553 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1554 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1555 rdev->pm.dynpm_can_downclock) {
1556 rdev->pm.dynpm_planned_action =
1557 DYNPM_ACTION_DOWNCLOCK;
1558 rdev->pm.dynpm_action_timeout = jiffies +
1559 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1563 /* Note, radeon_pm_set_clocks is called with static_switch set
1564 * to false since we want to wait for vbl to avoid flicker.
1566 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1567 jiffies > rdev->pm.dynpm_action_timeout) {
1568 radeon_pm_get_dynpm_state(rdev);
1569 radeon_pm_set_clocks(rdev);
1572 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1573 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1575 mutex_unlock(&rdev->pm.mutex);
1576 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1582 #if defined(CONFIG_DEBUG_FS)
1584 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1586 struct drm_info_node *node = (struct drm_info_node *) m->private;
1587 struct drm_device *dev = node->minor->dev;
1588 struct radeon_device *rdev = dev->dev_private;
1590 if (rdev->pm.dpm_enabled) {
1591 mutex_lock(&rdev->pm.mutex);
1592 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1593 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1595 seq_printf(m, "Debugfs support not implemented for this asic\n");
1596 mutex_unlock(&rdev->pm.mutex);
1598 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1599 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1600 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1601 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1603 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1604 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1605 if (rdev->asic->pm.get_memory_clock)
1606 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1607 if (rdev->pm.current_vddc)
1608 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1609 if (rdev->asic->pm.get_pcie_lanes)
1610 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1616 static struct drm_info_list radeon_pm_info_list[] = {
1617 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1621 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1623 #if defined(CONFIG_DEBUG_FS)
1624 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));