2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/radeon_drm.h>
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_update_memory_usage(struct radeon_bo *bo,
50 unsigned mem_type, int sign)
52 struct radeon_device *rdev = bo->rdev;
53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
58 atomic64_add(size, &rdev->gtt_usage);
60 atomic64_sub(size, &rdev->gtt_usage);
64 atomic64_add(size, &rdev->vram_usage);
66 atomic64_sub(size, &rdev->vram_usage);
71 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
75 bo = container_of(tbo, struct radeon_bo, tbo);
77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
79 mutex_lock(&bo->rdev->gem.mutex);
80 list_del_init(&bo->list);
81 mutex_unlock(&bo->rdev->gem.mutex);
82 radeon_bo_clear_surface_reg(bo);
83 WARN_ON(!list_empty(&bo->va));
84 drm_gem_object_release(&bo->gem_base);
88 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90 if (bo->destroy == &radeon_ttm_bo_destroy)
95 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
99 rbo->placement.fpfn = 0;
100 rbo->placement.lpfn = 0;
101 rbo->placement.placement = rbo->placements;
102 rbo->placement.busy_placement = rbo->placements;
103 if (domain & RADEON_GEM_DOMAIN_VRAM)
104 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
106 if (domain & RADEON_GEM_DOMAIN_GTT) {
107 if (rbo->flags & RADEON_GEM_GTT_UC) {
108 rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_TT;
109 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
110 (rbo->rdev->flags & RADEON_IS_AGP)) {
111 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
114 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
117 if (domain & RADEON_GEM_DOMAIN_CPU) {
118 if (rbo->flags & RADEON_GEM_GTT_UC) {
119 rbo->placements[c++] = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_SYSTEM;
120 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
121 rbo->rdev->flags & RADEON_IS_AGP) {
122 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
125 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
129 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
130 rbo->placement.num_placement = c;
131 rbo->placement.num_busy_placement = c;
134 * Use two-ended allocation depending on the buffer size to
135 * improve fragmentation quality.
136 * 512kb was measured as the most optimal number.
138 if (rbo->tbo.mem.size > 512 * 1024) {
139 for (i = 0; i < c; i++) {
140 rbo->placements[i] |= TTM_PL_FLAG_TOPDOWN;
145 int radeon_bo_create(struct radeon_device *rdev,
146 unsigned long size, int byte_align, bool kernel, u32 domain,
147 u32 flags, struct sg_table *sg, struct radeon_bo **bo_ptr)
149 struct radeon_bo *bo;
150 enum ttm_bo_type type;
151 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
155 size = ALIGN(size, PAGE_SIZE);
158 type = ttm_bo_type_kernel;
160 type = ttm_bo_type_sg;
162 type = ttm_bo_type_device;
166 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
167 sizeof(struct radeon_bo));
169 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
172 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
178 bo->surface_reg = -1;
179 INIT_LIST_HEAD(&bo->list);
180 INIT_LIST_HEAD(&bo->va);
181 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
182 RADEON_GEM_DOMAIN_GTT |
183 RADEON_GEM_DOMAIN_CPU);
186 /* PCI GART is always snooped */
187 if (!(rdev->flags & RADEON_IS_PCIE))
188 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
190 radeon_ttm_placement_from_domain(bo, domain);
191 /* Kernel allocation are uninterruptible */
192 down_read(&rdev->pm.mclk_lock);
193 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
194 &bo->placement, page_align, !kernel, NULL,
195 acc_size, sg, &radeon_ttm_bo_destroy);
196 up_read(&rdev->pm.mclk_lock);
197 if (unlikely(r != 0)) {
202 trace_radeon_bo_create(bo);
207 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
218 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
222 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
226 radeon_bo_check_tiling(bo, 0, 0);
230 void radeon_bo_kunmap(struct radeon_bo *bo)
232 if (bo->kptr == NULL)
235 radeon_bo_check_tiling(bo, 0, 0);
236 ttm_bo_kunmap(&bo->kmap);
239 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
244 ttm_bo_reference(&bo->tbo);
248 void radeon_bo_unref(struct radeon_bo **bo)
250 struct ttm_buffer_object *tbo;
251 struct radeon_device *rdev;
262 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
267 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
273 *gpu_addr = radeon_bo_gpu_offset(bo);
275 if (max_offset != 0) {
278 if (domain == RADEON_GEM_DOMAIN_VRAM)
279 domain_start = bo->rdev->mc.vram_start;
281 domain_start = bo->rdev->mc.gtt_start;
282 WARN_ON_ONCE(max_offset <
283 (radeon_bo_gpu_offset(bo) - domain_start));
288 radeon_ttm_placement_from_domain(bo, domain);
289 if (domain == RADEON_GEM_DOMAIN_VRAM) {
290 /* force to pin into visible video ram */
291 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
294 u64 lpfn = max_offset >> PAGE_SHIFT;
296 if (!bo->placement.lpfn)
297 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
299 if (lpfn < bo->placement.lpfn)
300 bo->placement.lpfn = lpfn;
302 for (i = 0; i < bo->placement.num_placement; i++)
303 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
304 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
305 if (likely(r == 0)) {
307 if (gpu_addr != NULL)
308 *gpu_addr = radeon_bo_gpu_offset(bo);
309 if (domain == RADEON_GEM_DOMAIN_VRAM)
310 bo->rdev->vram_pin_size += radeon_bo_size(bo);
312 bo->rdev->gart_pin_size += radeon_bo_size(bo);
314 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
319 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
321 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
324 int radeon_bo_unpin(struct radeon_bo *bo)
328 if (!bo->pin_count) {
329 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
335 for (i = 0; i < bo->placement.num_placement; i++)
336 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
337 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
338 if (likely(r == 0)) {
339 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
340 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
342 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
344 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
349 int radeon_bo_evict_vram(struct radeon_device *rdev)
351 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
352 if (0 && (rdev->flags & RADEON_IS_IGP)) {
353 if (rdev->mc.igp_sideport_enabled == false)
354 /* Useless to evict on IGP chips */
357 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
360 void radeon_bo_force_delete(struct radeon_device *rdev)
362 struct radeon_bo *bo, *n;
364 if (list_empty(&rdev->gem.objects)) {
367 dev_err(rdev->dev, "Userspace still has active objects !\n");
368 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
369 mutex_lock(&rdev->ddev->struct_mutex);
370 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
371 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
372 *((unsigned long *)&bo->gem_base.refcount));
373 mutex_lock(&bo->rdev->gem.mutex);
374 list_del_init(&bo->list);
375 mutex_unlock(&bo->rdev->gem.mutex);
376 /* this should unref the ttm bo */
377 drm_gem_object_unreference(&bo->gem_base);
378 mutex_unlock(&rdev->ddev->struct_mutex);
382 int radeon_bo_init(struct radeon_device *rdev)
384 /* Add an MTRR for the VRAM */
385 if (!rdev->fastfb_working) {
386 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
389 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
390 rdev->mc.mc_vram_size >> 20,
391 (unsigned long long)rdev->mc.aper_size >> 20);
392 DRM_INFO("RAM width %dbits %cDR\n",
393 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
394 return radeon_ttm_init(rdev);
397 void radeon_bo_fini(struct radeon_device *rdev)
399 radeon_ttm_fini(rdev);
400 arch_phys_wc_del(rdev->mc.vram_mtrr);
403 /* Returns how many bytes TTM can move per IB.
405 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
407 u64 real_vram_size = rdev->mc.real_vram_size;
408 u64 vram_usage = atomic64_read(&rdev->vram_usage);
410 /* This function is based on the current VRAM usage.
412 * - If all of VRAM is free, allow relocating the number of bytes that
413 * is equal to 1/4 of the size of VRAM for this IB.
415 * - If more than one half of VRAM is occupied, only allow relocating
416 * 1 MB of data for this IB.
418 * - From 0 to one half of used VRAM, the threshold decreases
433 * Note: It's a threshold, not a limit. The threshold must be crossed
434 * for buffer relocations to stop, so any buffer of an arbitrary size
435 * can be moved as long as the threshold isn't crossed before
436 * the relocation takes place. We don't want to disable buffer
437 * relocations completely.
439 * The idea is that buffers should be placed in VRAM at creation time
440 * and TTM should only do a minimum number of relocations during
441 * command submission. In practice, you need to submit at least
442 * a dozen IBs to move all buffers to VRAM if they are in GTT.
444 * Also, things can get pretty crazy under memory pressure and actual
445 * VRAM usage can change a lot, so playing safe even at 50% does
446 * consistently increase performance.
449 u64 half_vram = real_vram_size >> 1;
450 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
451 u64 bytes_moved_threshold = half_free_vram >> 1;
452 return max(bytes_moved_threshold, 1024*1024ull);
455 int radeon_bo_list_validate(struct radeon_device *rdev,
456 struct ww_acquire_ctx *ticket,
457 struct list_head *head, int ring)
459 struct radeon_cs_reloc *lobj;
460 struct radeon_bo *bo;
462 u64 bytes_moved = 0, initial_bytes_moved;
463 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
465 r = ttm_eu_reserve_buffers(ticket, head);
466 if (unlikely(r != 0)) {
470 list_for_each_entry(lobj, head, tv.head) {
472 if (!bo->pin_count) {
473 u32 domain = lobj->prefered_domains;
475 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
477 /* Check if this buffer will be moved and don't move it
478 * if we have moved too many buffers for this IB already.
480 * Note that this allows moving at least one buffer of
481 * any size, because it doesn't take the current "bo"
482 * into account. We don't want to disallow buffer moves
485 if ((lobj->allowed_domains & current_domain) != 0 &&
486 (domain & current_domain) == 0 && /* will be moved */
487 bytes_moved > bytes_moved_threshold) {
489 domain = current_domain;
493 radeon_ttm_placement_from_domain(bo, domain);
494 if (ring == R600_RING_TYPE_UVD_INDEX)
495 radeon_uvd_force_into_uvd_segment(bo);
497 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
498 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
499 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
503 if (r != -ERESTARTSYS &&
504 domain != lobj->allowed_domains) {
505 domain = lobj->allowed_domains;
508 ttm_eu_backoff_reservation(ticket, head);
512 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
513 lobj->tiling_flags = bo->tiling_flags;
518 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
519 struct vm_area_struct *vma)
521 return ttm_fbdev_mmap(vma, &bo->tbo);
524 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
526 struct radeon_device *rdev = bo->rdev;
527 struct radeon_surface_reg *reg;
528 struct radeon_bo *old_object;
532 lockdep_assert_held(&bo->tbo.resv->lock.base);
534 if (!bo->tiling_flags)
537 if (bo->surface_reg >= 0) {
538 reg = &rdev->surface_regs[bo->surface_reg];
544 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
546 reg = &rdev->surface_regs[i];
550 old_object = reg->bo;
551 if (old_object->pin_count == 0)
555 /* if we are all out */
556 if (i == RADEON_GEM_MAX_SURFACES) {
559 /* find someone with a surface reg and nuke their BO */
560 reg = &rdev->surface_regs[steal];
561 old_object = reg->bo;
562 /* blow away the mapping */
563 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
564 ttm_bo_unmap_virtual(&old_object->tbo);
565 old_object->surface_reg = -1;
573 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
574 bo->tbo.mem.start << PAGE_SHIFT,
575 bo->tbo.num_pages << PAGE_SHIFT);
579 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
581 struct radeon_device *rdev = bo->rdev;
582 struct radeon_surface_reg *reg;
584 if (bo->surface_reg == -1)
587 reg = &rdev->surface_regs[bo->surface_reg];
588 radeon_clear_surface_reg(rdev, bo->surface_reg);
591 bo->surface_reg = -1;
594 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
595 uint32_t tiling_flags, uint32_t pitch)
597 struct radeon_device *rdev = bo->rdev;
600 if (rdev->family >= CHIP_CEDAR) {
601 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
603 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
604 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
605 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
606 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
607 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
641 if (stilesplit > 6) {
645 r = radeon_bo_reserve(bo, false);
646 if (unlikely(r != 0))
648 bo->tiling_flags = tiling_flags;
650 radeon_bo_unreserve(bo);
654 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
655 uint32_t *tiling_flags,
658 lockdep_assert_held(&bo->tbo.resv->lock.base);
661 *tiling_flags = bo->tiling_flags;
666 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
670 lockdep_assert_held(&bo->tbo.resv->lock.base);
672 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
676 radeon_bo_clear_surface_reg(bo);
680 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
684 if (bo->surface_reg >= 0)
685 radeon_bo_clear_surface_reg(bo);
689 if ((bo->surface_reg >= 0) && !has_moved)
692 return radeon_bo_get_surface_reg(bo);
695 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
696 struct ttm_mem_reg *new_mem)
698 struct radeon_bo *rbo;
700 if (!radeon_ttm_bo_is_radeon_bo(bo))
703 rbo = container_of(bo, struct radeon_bo, tbo);
704 radeon_bo_check_tiling(rbo, 0, 1);
705 radeon_vm_bo_invalidate(rbo->rdev, rbo);
707 /* update statistics */
711 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
712 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
715 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
717 struct radeon_device *rdev;
718 struct radeon_bo *rbo;
719 unsigned long offset, size;
722 if (!radeon_ttm_bo_is_radeon_bo(bo))
724 rbo = container_of(bo, struct radeon_bo, tbo);
725 radeon_bo_check_tiling(rbo, 0, 0);
727 if (bo->mem.mem_type != TTM_PL_VRAM)
730 size = bo->mem.num_pages << PAGE_SHIFT;
731 offset = bo->mem.start << PAGE_SHIFT;
732 if ((offset + size) <= rdev->mc.visible_vram_size)
735 /* hurrah the memory is not visible ! */
736 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
737 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
738 r = ttm_bo_validate(bo, &rbo->placement, false, false);
739 if (unlikely(r == -ENOMEM)) {
740 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
741 return ttm_bo_validate(bo, &rbo->placement, false, false);
742 } else if (unlikely(r != 0)) {
746 offset = bo->mem.start << PAGE_SHIFT;
747 /* this should never happen */
748 if ((offset + size) > rdev->mc.visible_vram_size)
754 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
758 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
759 if (unlikely(r != 0))
761 spin_lock(&bo->tbo.bdev->fence_lock);
763 *mem_type = bo->tbo.mem.mem_type;
764 if (bo->tbo.sync_obj)
765 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
766 spin_unlock(&bo->tbo.bdev->fence_lock);
767 ttm_bo_unreserve(&bo->tbo);