2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
33 static void radeon_overscan_setup(struct drm_crtc *crtc,
34 struct drm_display_mode *mode)
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46 struct drm_display_mode *mode)
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 int xres = mode->hdisplay;
52 int yres = mode->vdisplay;
53 bool hscale = true, vscale = true;
58 u32 scale, inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65 (RADEON_VERT_STRETCH_RESERVED |
66 RADEON_VERT_AUTO_RATIO_INC);
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68 (RADEON_HORZ_FP_LOOP_STRETCH |
69 RADEON_HORZ_AUTO_RATIO_INC);
72 if ((rdev->family == CHIP_RS100) ||
73 (rdev->family == CHIP_RS200)) {
74 /* This is to workaround the asic bug for RMX, some versions
75 of BIOS dosen't have this register initialized correctly. */
76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
86 hsync_start = mode->crtc_hsync_start - 8;
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91 ? RADEON_CRTC_H_SYNC_POL
94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95 | ((mode->crtc_vdisplay - 1) << 16));
97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102 | ((vsync_wid & 0x1f) << 16)
103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104 ? RADEON_CRTC_V_SYNC_POL
107 fp_horz_vert_active = 0;
109 if (native_mode->hdisplay == 0 ||
110 native_mode->vdisplay == 0) {
114 if (xres > native_mode->hdisplay)
115 xres = native_mode->hdisplay;
116 if (yres > native_mode->vdisplay)
117 yres = native_mode->vdisplay;
119 if (xres == native_mode->hdisplay)
121 if (yres == native_mode->vdisplay)
125 switch (radeon_crtc->rmx_type) {
129 fp_horz_stretch |= ((xres/8-1) << 16);
131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133 / native_mode->hdisplay + 1;
134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135 RADEON_HORZ_STRETCH_BLEND |
136 RADEON_HORZ_STRETCH_ENABLE |
137 ((native_mode->hdisplay/8-1) << 16));
141 fp_vert_stretch |= ((yres-1) << 12);
143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145 / native_mode->vdisplay + 1;
146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147 RADEON_VERT_STRETCH_ENABLE |
148 RADEON_VERT_STRETCH_BLEND |
149 ((native_mode->vdisplay-1) << 12));
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157 RADEON_CRTC_AUTO_VERT_CENTER_EN);
159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160 if (blank_width > 110)
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171 | ((hsync_wid & 0x3f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173 ? RADEON_CRTC_H_SYNC_POL
176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177 | ((mode->crtc_vdisplay - 1) << 16));
179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184 | ((vsync_wid & 0x1f) << 16)
185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186 ? RADEON_CRTC_V_SYNC_POL
189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
209 void radeon_restore_common_regs(struct drm_device *dev)
211 /* don't need this yet */
214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
216 struct radeon_device *rdev = dev->dev_private;
219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
220 the cause yet, but this workaround will mask the problem for now.
221 Other chips usually will pass at the very first test, so the
222 workaround shouldn't have any effect on them. */
225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
229 static void radeon_pll_write_update(struct drm_device *dev)
231 struct radeon_device *rdev = dev->dev_private;
233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
235 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236 RADEON_PPLL_ATOMIC_UPDATE_W,
237 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
242 struct radeon_device *rdev = dev->dev_private;
246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
247 the cause yet, but this workaround will mask the problem for now.
248 Other chips usually will pass at the very first test, so the
249 workaround shouldn't have any effect on them. */
252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
256 static void radeon_pll2_write_update(struct drm_device *dev)
258 struct radeon_device *rdev = dev->dev_private;
260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263 RADEON_P2PLL_ATOMIC_UPDATE_W,
264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
270 unsigned int vcoFreq;
275 vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
278 * This is horribly crude: the VCO frequency range is divided into
279 * 3 parts, each part having a fixed PLL gain value.
281 if (vcoFreq >= 30000)
286 else if (vcoFreq >= 18000)
298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
305 if (radeon_crtc->crtc_id)
306 mask = (RADEON_CRTC2_DISP_DIS |
307 RADEON_CRTC2_VSYNC_DIS |
308 RADEON_CRTC2_HSYNC_DIS |
309 RADEON_CRTC2_DISP_REQ_EN_B);
311 mask = (RADEON_CRTC_DISPLAY_DIS |
312 RADEON_CRTC_VSYNC_DIS |
313 RADEON_CRTC_HSYNC_DIS);
316 case DRM_MODE_DPMS_ON:
317 if (radeon_crtc->crtc_id)
318 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
320 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
321 RADEON_CRTC_DISP_REQ_EN_B));
322 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
324 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
325 radeon_crtc_load_lut(crtc);
327 case DRM_MODE_DPMS_STANDBY:
328 case DRM_MODE_DPMS_SUSPEND:
329 case DRM_MODE_DPMS_OFF:
330 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
331 if (radeon_crtc->crtc_id)
332 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
334 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
335 RADEON_CRTC_DISP_REQ_EN_B));
336 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
342 /* properly set crtc bpp when using atombios */
343 void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
345 struct drm_device *dev = crtc->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
349 uint32_t crtc_gen_cntl;
350 uint32_t disp_merge_cntl;
353 switch (crtc->fb->bits_per_pixel) {
373 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
374 ((crtc->fb->bits_per_pixel * 8) - 1)) /
375 (crtc->fb->bits_per_pixel * 8));
376 crtc_pitch |= crtc_pitch << 16;
378 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
380 switch (radeon_crtc->crtc_id) {
382 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
386 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
389 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
392 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
393 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
394 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
396 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
397 crtc_gen_cntl |= (format << 8);
398 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
399 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
400 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
405 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
406 struct drm_framebuffer *old_fb)
408 struct drm_device *dev = crtc->dev;
409 struct radeon_device *rdev = dev->dev_private;
410 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
411 struct radeon_framebuffer *radeon_fb;
412 struct drm_gem_object *obj;
413 struct radeon_bo *rbo;
415 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
416 uint32_t crtc_pitch, pitch_pixels;
417 uint32_t tiling_flags;
419 uint32_t gen_cntl_reg, gen_cntl_val;
425 DRM_DEBUG("No FB bound\n");
429 radeon_fb = to_radeon_framebuffer(crtc->fb);
431 switch (crtc->fb->bits_per_pixel) {
451 /* Pin framebuffer & get tilling informations */
452 obj = radeon_fb->obj;
453 rbo = obj->driver_private;
454 r = radeon_bo_reserve(rbo, false);
455 if (unlikely(r != 0))
457 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
458 if (unlikely(r != 0)) {
459 radeon_bo_unreserve(rbo);
462 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
463 radeon_bo_unreserve(rbo);
464 if (tiling_flags & RADEON_TILING_MICRO)
465 DRM_ERROR("trying to scanout microtiled buffer\n");
467 /* if scanout was in GTT this really wouldn't work */
468 /* crtc offset is from display base addr not FB location */
469 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
471 base -= radeon_crtc->legacy_display_base_addr;
473 crtc_offset_cntl = 0;
475 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
476 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
477 ((crtc->fb->bits_per_pixel * 8) - 1)) /
478 (crtc->fb->bits_per_pixel * 8));
479 crtc_pitch |= crtc_pitch << 16;
482 if (tiling_flags & RADEON_TILING_MACRO) {
483 if (ASIC_IS_R300(rdev))
484 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
485 R300_CRTC_MICRO_TILE_BUFFER_DIS |
486 R300_CRTC_MACRO_TILE_EN);
488 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
490 if (ASIC_IS_R300(rdev))
491 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
492 R300_CRTC_MICRO_TILE_BUFFER_DIS |
493 R300_CRTC_MACRO_TILE_EN);
495 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
498 if (tiling_flags & RADEON_TILING_MACRO) {
499 if (ASIC_IS_R300(rdev)) {
500 crtc_tile_x0_y0 = x | (y << 16);
503 int byteshift = crtc->fb->bits_per_pixel >> 4;
504 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
505 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
506 crtc_offset_cntl |= (y % 16);
509 int offset = y * pitch_pixels + x;
510 switch (crtc->fb->bits_per_pixel) {
532 if (radeon_crtc->crtc_id == 1)
533 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
535 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
537 gen_cntl_val = RREG32(gen_cntl_reg);
538 gen_cntl_val &= ~(0xf << 8);
539 gen_cntl_val |= (format << 8);
540 WREG32(gen_cntl_reg, gen_cntl_val);
542 crtc_offset = (u32)base;
544 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
546 if (ASIC_IS_R300(rdev)) {
547 if (radeon_crtc->crtc_id)
548 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
550 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
552 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
553 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
554 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
556 if (old_fb && old_fb != crtc->fb) {
557 radeon_fb = to_radeon_framebuffer(old_fb);
558 rbo = radeon_fb->obj->driver_private;
559 r = radeon_bo_reserve(rbo, false);
560 if (unlikely(r != 0))
562 radeon_bo_unpin(rbo);
563 radeon_bo_unreserve(rbo);
566 /* Bytes per pixel may have changed */
567 radeon_bandwidth_update(rdev);
572 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
574 struct drm_device *dev = crtc->dev;
575 struct radeon_device *rdev = dev->dev_private;
576 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
577 struct drm_encoder *encoder;
582 uint32_t crtc_h_total_disp;
583 uint32_t crtc_h_sync_strt_wid;
584 uint32_t crtc_v_total_disp;
585 uint32_t crtc_v_sync_strt_wid;
589 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
590 if (encoder->crtc == crtc) {
591 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
592 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
594 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
600 switch (crtc->fb->bits_per_pixel) {
620 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
621 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
623 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
626 hsync_start = mode->crtc_hsync_start - 8;
628 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
629 | ((hsync_wid & 0x3f) << 16)
630 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
631 ? RADEON_CRTC_H_SYNC_POL
634 /* This works for double scan mode. */
635 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
636 | ((mode->crtc_vdisplay - 1) << 16));
638 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
642 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
643 | ((vsync_wid & 0x1f) << 16)
644 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
645 ? RADEON_CRTC_V_SYNC_POL
648 /* TODO -> Dell Server */
650 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
651 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
652 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
653 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
655 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
656 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
658 /* For CRT on DAC2, don't turn it on if BIOS didn't
659 enable it, even it's detected.
661 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
662 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
663 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
665 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
666 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
667 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
668 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
671 if (radeon_crtc->crtc_id) {
672 uint32_t crtc2_gen_cntl;
673 uint32_t disp2_merge_cntl;
675 /* if TV DAC is enabled for another crtc and keep it enabled */
676 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
677 crtc2_gen_cntl |= ((format << 8)
678 | RADEON_CRTC2_VSYNC_DIS
679 | RADEON_CRTC2_HSYNC_DIS
680 | RADEON_CRTC2_DISP_DIS
681 | RADEON_CRTC2_DISP_REQ_EN_B
682 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
683 ? RADEON_CRTC2_DBL_SCAN_EN
685 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
686 ? RADEON_CRTC2_CSYNC_EN
688 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
689 ? RADEON_CRTC2_INTERLACE_EN
692 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
693 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
695 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
696 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
698 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
699 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
701 uint32_t crtc_gen_cntl;
702 uint32_t crtc_ext_cntl;
703 uint32_t disp_merge_cntl;
705 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
706 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
708 | RADEON_CRTC_DISP_REQ_EN_B
709 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
710 ? RADEON_CRTC_DBL_SCAN_EN
712 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
713 ? RADEON_CRTC_CSYNC_EN
715 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
716 ? RADEON_CRTC_INTERLACE_EN
719 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
720 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
721 RADEON_CRTC_VSYNC_DIS |
722 RADEON_CRTC_HSYNC_DIS |
723 RADEON_CRTC_DISPLAY_DIS);
725 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
726 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
728 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
729 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
730 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
734 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
735 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
736 &crtc_v_sync_strt_wid);
738 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
739 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
740 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
741 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
746 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
748 struct drm_device *dev = crtc->dev;
749 struct radeon_device *rdev = dev->dev_private;
750 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
751 struct drm_encoder *encoder;
752 uint32_t feedback_div = 0;
753 uint32_t frac_fb_div = 0;
754 uint32_t reference_div = 0;
755 uint32_t post_divider = 0;
758 int pll_flags = RADEON_PLL_LEGACY;
759 bool use_bios_divs = false;
761 uint32_t pll_ref_div = 0;
762 uint32_t pll_fb_post_div = 0;
763 uint32_t htotal_cntl = 0;
765 struct radeon_pll *pll;
770 } *post_div, post_divs[] = {
771 /* From RAGE 128 VR/RAGE 128 GL Register
772 * Reference Manual (Technical Reference
773 * Manual P/N RRG-G04100-C Rev. 0.04), page
774 * 3-17 (PLL_DIV_[3:0]).
776 { 1, 0 }, /* VCLK_SRC */
777 { 2, 1 }, /* VCLK_SRC/2 */
778 { 4, 2 }, /* VCLK_SRC/4 */
779 { 8, 3 }, /* VCLK_SRC/8 */
780 { 3, 4 }, /* VCLK_SRC/3 */
781 { 16, 5 }, /* VCLK_SRC/16 */
782 { 6, 6 }, /* VCLK_SRC/6 */
783 { 12, 7 }, /* VCLK_SRC/12 */
787 if (radeon_crtc->crtc_id)
788 pll = &rdev->clock.p2pll;
790 pll = &rdev->clock.p1pll;
792 if (mode->clock > 200000) /* range limits??? */
793 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
795 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
797 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
798 if (encoder->crtc == crtc) {
799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
801 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
806 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
807 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
808 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
809 if (!rdev->is_atom_bios) {
810 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
811 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
813 if (lvds->use_bios_dividers) {
814 pll_ref_div = lvds->panel_ref_divider;
815 pll_fb_post_div = (lvds->panel_fb_divider |
816 (lvds->panel_post_divider << 16));
818 use_bios_divs = true;
822 pll_flags |= RADEON_PLL_USE_REF_DIV;
829 if (!use_bios_divs) {
830 radeon_compute_pll(pll, mode->clock,
831 &freq, &feedback_div, &frac_fb_div,
832 &reference_div, &post_divider,
835 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
836 if (post_div->divider == post_divider)
840 if (!post_div->divider)
841 post_div = &post_divs[0];
843 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
849 pll_ref_div = reference_div;
850 #if defined(__powerpc__) && (0) /* TODO */
851 /* apparently programming this otherwise causes a hang??? */
852 if (info->MacModel == RADEON_MAC_IBOOK)
853 pll_fb_post_div = 0x000600ad;
856 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
858 htotal_cntl = mode->htotal & 0x7;
862 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
864 pll_fb_post_div & 0x7ff);
866 if (radeon_crtc->crtc_id) {
867 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
868 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
869 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
872 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
873 &pll_ref_div, &pll_fb_post_div,
877 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
878 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
879 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
881 WREG32_PLL_P(RADEON_P2PLL_CNTL,
883 | RADEON_P2PLL_ATOMIC_UPDATE_EN
884 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
886 | RADEON_P2PLL_ATOMIC_UPDATE_EN
887 | RADEON_P2PLL_PVG_MASK));
889 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
891 ~RADEON_P2PLL_REF_DIV_MASK);
893 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
895 ~RADEON_P2PLL_FB0_DIV_MASK);
897 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
899 ~RADEON_P2PLL_POST0_DIV_MASK);
901 radeon_pll2_write_update(dev);
902 radeon_pll2_wait_for_read_update_complete(dev);
904 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
906 WREG32_PLL_P(RADEON_P2PLL_CNTL,
910 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
912 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
913 (unsigned)pll_ref_div,
914 (unsigned)pll_fb_post_div,
915 (unsigned)htotal_cntl,
916 RREG32_PLL(RADEON_P2PLL_CNTL));
917 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
918 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
919 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
920 (unsigned)((pll_fb_post_div &
921 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
923 mdelay(50); /* Let the clock to lock */
925 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
926 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
927 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
929 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
931 uint32_t pixclks_cntl;
935 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
936 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
937 &pll_fb_post_div, &pixclks_cntl);
940 if (rdev->flags & RADEON_IS_MOBILITY) {
941 /* A temporal workaround for the occational blanking on certain laptop panels.
942 This appears to related to the PLL divider registers (fail to lock?).
943 It occurs even when all dividers are the same with their old settings.
944 In this case we really don't need to fiddle with PLL registers.
945 By doing this we can avoid the blanking problem with some panels.
947 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
948 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
949 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
950 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
952 ~(RADEON_PLL_DIV_SEL));
953 r100_pll_errata_after_index(rdev);
958 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
959 RADEON_VCLK_SRC_SEL_CPUCLK,
960 ~(RADEON_VCLK_SRC_SEL_MASK));
961 WREG32_PLL_P(RADEON_PPLL_CNTL,
963 | RADEON_PPLL_ATOMIC_UPDATE_EN
964 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
965 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
967 | RADEON_PPLL_ATOMIC_UPDATE_EN
968 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
969 | RADEON_PPLL_PVG_MASK));
971 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
973 ~(RADEON_PLL_DIV_SEL));
974 r100_pll_errata_after_index(rdev);
976 if (ASIC_IS_R300(rdev) ||
977 (rdev->family == CHIP_RS300) ||
978 (rdev->family == CHIP_RS400) ||
979 (rdev->family == CHIP_RS480)) {
980 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
981 /* When restoring console mode, use saved PPLL_REF_DIV
984 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
988 /* R300 uses ref_div_acc field as real ref divider */
989 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
990 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
991 ~R300_PPLL_REF_DIV_ACC_MASK);
994 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
996 ~RADEON_PPLL_REF_DIV_MASK);
998 WREG32_PLL_P(RADEON_PPLL_DIV_3,
1000 ~RADEON_PPLL_FB3_DIV_MASK);
1002 WREG32_PLL_P(RADEON_PPLL_DIV_3,
1004 ~RADEON_PPLL_POST3_DIV_MASK);
1006 radeon_pll_write_update(dev);
1007 radeon_pll_wait_for_read_update_complete(dev);
1009 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1011 WREG32_PLL_P(RADEON_PPLL_CNTL,
1015 | RADEON_PPLL_ATOMIC_UPDATE_EN
1016 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1018 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1021 (unsigned)htotal_cntl,
1022 RREG32_PLL(RADEON_PPLL_CNTL));
1023 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
1024 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1025 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1026 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1028 mdelay(50); /* Let the clock to lock */
1030 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1031 RADEON_VCLK_SRC_SEL_PPLLCLK,
1032 ~(RADEON_VCLK_SRC_SEL_MASK));
1035 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1039 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1040 struct drm_display_mode *mode,
1041 struct drm_display_mode *adjusted_mode)
1043 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1048 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1049 struct drm_display_mode *mode,
1050 struct drm_display_mode *adjusted_mode,
1051 int x, int y, struct drm_framebuffer *old_fb)
1053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1056 radeon_crtc_set_base(crtc, x, y, old_fb);
1057 radeon_set_crtc_timing(crtc, adjusted_mode);
1058 radeon_set_pll(crtc, adjusted_mode);
1059 radeon_overscan_setup(crtc, adjusted_mode);
1060 if (radeon_crtc->crtc_id == 0) {
1061 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1063 if (radeon_crtc->rmx_type != RMX_OFF) {
1064 /* FIXME: only first crtc has rmx what should we
1067 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1073 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1075 struct drm_device *dev = crtc->dev;
1076 struct drm_crtc *crtci;
1079 * The hardware wedges sometimes if you reconfigure one CRTC
1080 * whilst another is running (see fdo bug #24611).
1082 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1083 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1086 static void radeon_crtc_commit(struct drm_crtc *crtc)
1088 struct drm_device *dev = crtc->dev;
1089 struct drm_crtc *crtci;
1092 * Reenable the CRTCs that should be running.
1094 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1096 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1100 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1101 .dpms = radeon_crtc_dpms,
1102 .mode_fixup = radeon_crtc_mode_fixup,
1103 .mode_set = radeon_crtc_mode_set,
1104 .mode_set_base = radeon_crtc_set_base,
1105 .prepare = radeon_crtc_prepare,
1106 .commit = radeon_crtc_commit,
1107 .load_lut = radeon_crtc_load_lut,
1111 void radeon_legacy_init_crtc(struct drm_device *dev,
1112 struct radeon_crtc *radeon_crtc)
1114 if (radeon_crtc->crtc_id == 1)
1115 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1116 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);