2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/radeon_drm.h>
30 #include <drm/drm_fixed.h>
34 static void radeon_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode)
37 struct drm_device *dev = crtc->dev;
38 struct radeon_device *rdev = dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
43 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
46 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
47 struct drm_display_mode *mode)
49 struct drm_device *dev = crtc->dev;
50 struct radeon_device *rdev = dev->dev_private;
51 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
52 int xres = mode->hdisplay;
53 int yres = mode->vdisplay;
54 bool hscale = true, vscale = true;
59 u32 scale, inc, crtc_more_cntl;
60 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
61 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
62 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
63 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
65 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
66 (RADEON_VERT_STRETCH_RESERVED |
67 RADEON_VERT_AUTO_RATIO_INC);
68 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
69 (RADEON_HORZ_FP_LOOP_STRETCH |
70 RADEON_HORZ_AUTO_RATIO_INC);
73 if ((rdev->family == CHIP_RS100) ||
74 (rdev->family == CHIP_RS200)) {
75 /* This is to workaround the asic bug for RMX, some versions
76 of BIOS dosen't have this register initialized correctly. */
77 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
81 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
82 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
84 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
87 hsync_start = mode->crtc_hsync_start - 8;
89 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
90 | ((hsync_wid & 0x3f) << 16)
91 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
92 ? RADEON_CRTC_H_SYNC_POL
95 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
96 | ((mode->crtc_vdisplay - 1) << 16));
98 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
102 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
103 | ((vsync_wid & 0x1f) << 16)
104 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
105 ? RADEON_CRTC_V_SYNC_POL
108 fp_horz_vert_active = 0;
110 if (native_mode->hdisplay == 0 ||
111 native_mode->vdisplay == 0) {
115 if (xres > native_mode->hdisplay)
116 xres = native_mode->hdisplay;
117 if (yres > native_mode->vdisplay)
118 yres = native_mode->vdisplay;
120 if (xres == native_mode->hdisplay)
122 if (yres == native_mode->vdisplay)
126 switch (radeon_crtc->rmx_type) {
130 fp_horz_stretch |= ((xres/8-1) << 16);
132 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
134 / native_mode->hdisplay + 1;
135 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
136 RADEON_HORZ_STRETCH_BLEND |
137 RADEON_HORZ_STRETCH_ENABLE |
138 ((native_mode->hdisplay/8-1) << 16));
142 fp_vert_stretch |= ((yres-1) << 12);
144 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
145 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
146 / native_mode->vdisplay + 1;
147 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
148 RADEON_VERT_STRETCH_ENABLE |
149 RADEON_VERT_STRETCH_BLEND |
150 ((native_mode->vdisplay-1) << 12));
154 fp_horz_stretch |= ((xres/8-1) << 16);
155 fp_vert_stretch |= ((yres-1) << 12);
157 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
158 RADEON_CRTC_AUTO_VERT_CENTER_EN);
160 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
161 if (blank_width > 110)
164 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
165 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
167 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
171 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
172 | ((hsync_wid & 0x3f) << 16)
173 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
174 ? RADEON_CRTC_H_SYNC_POL
177 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
178 | ((mode->crtc_vdisplay - 1) << 16));
180 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
184 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
185 | ((vsync_wid & 0x1f) << 16)
186 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
187 ? RADEON_CRTC_V_SYNC_POL
190 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
191 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
195 fp_horz_stretch |= ((xres/8-1) << 16);
196 fp_vert_stretch |= ((yres-1) << 12);
200 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
201 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
202 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
203 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
204 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
205 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
206 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
207 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
210 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
212 struct radeon_device *rdev = dev->dev_private;
215 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
216 the cause yet, but this workaround will mask the problem for now.
217 Other chips usually will pass at the very first test, so the
218 workaround shouldn't have any effect on them. */
221 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
225 static void radeon_pll_write_update(struct drm_device *dev)
227 struct radeon_device *rdev = dev->dev_private;
229 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
231 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
232 RADEON_PPLL_ATOMIC_UPDATE_W,
233 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
236 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
238 struct radeon_device *rdev = dev->dev_private;
242 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
243 the cause yet, but this workaround will mask the problem for now.
244 Other chips usually will pass at the very first test, so the
245 workaround shouldn't have any effect on them. */
248 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
252 static void radeon_pll2_write_update(struct drm_device *dev)
254 struct radeon_device *rdev = dev->dev_private;
256 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
258 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
259 RADEON_P2PLL_ATOMIC_UPDATE_W,
260 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
263 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
266 unsigned int vcoFreq;
271 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
274 * This is horribly crude: the VCO frequency range is divided into
275 * 3 parts, each part having a fixed PLL gain value.
277 if (vcoFreq >= 30000)
282 else if (vcoFreq >= 18000)
294 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
296 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
297 struct drm_device *dev = crtc->dev;
298 struct radeon_device *rdev = dev->dev_private;
299 uint32_t crtc_ext_cntl = 0;
302 if (radeon_crtc->crtc_id)
303 mask = (RADEON_CRTC2_DISP_DIS |
304 RADEON_CRTC2_VSYNC_DIS |
305 RADEON_CRTC2_HSYNC_DIS |
306 RADEON_CRTC2_DISP_REQ_EN_B);
308 mask = (RADEON_CRTC_DISPLAY_DIS |
309 RADEON_CRTC_VSYNC_DIS |
310 RADEON_CRTC_HSYNC_DIS);
313 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
314 * Therefore it is set in the DAC DMPS function.
315 * This is different for GPU's with a single CRTC but a primary and a
316 * TV DAC: here it controls the single CRTC no matter where it is
317 * routed. Therefore we set it here.
319 if (rdev->flags & RADEON_SINGLE_CRTC)
320 crtc_ext_cntl = RADEON_CRTC_CRT_ON;
323 case DRM_MODE_DPMS_ON:
324 radeon_crtc->enabled = true;
325 /* adjust pm to dpms changes BEFORE enabling crtcs */
326 radeon_pm_compute_clocks(rdev);
327 if (radeon_crtc->crtc_id)
328 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
330 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
331 RADEON_CRTC_DISP_REQ_EN_B));
332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
334 drm_vblank_on(dev, radeon_crtc->crtc_id);
335 radeon_crtc_load_lut(crtc);
337 case DRM_MODE_DPMS_STANDBY:
338 case DRM_MODE_DPMS_SUSPEND:
339 case DRM_MODE_DPMS_OFF:
340 drm_vblank_off(dev, radeon_crtc->crtc_id);
341 if (radeon_crtc->crtc_id)
342 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
344 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
345 RADEON_CRTC_DISP_REQ_EN_B));
346 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
348 radeon_crtc->enabled = false;
349 /* adjust pm to dpms changes AFTER disabling crtcs */
350 radeon_pm_compute_clocks(rdev);
355 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
356 struct drm_framebuffer *old_fb)
358 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
361 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
362 struct drm_framebuffer *fb,
363 int x, int y, enum mode_set_atomic state)
365 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
368 int radeon_crtc_do_set_base(struct drm_crtc *crtc,
369 struct drm_framebuffer *fb,
370 int x, int y, int atomic)
372 struct drm_device *dev = crtc->dev;
373 struct radeon_device *rdev = dev->dev_private;
374 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
375 struct radeon_framebuffer *radeon_fb;
376 struct drm_framebuffer *target_fb;
377 struct drm_gem_object *obj;
378 struct radeon_bo *rbo;
380 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
381 uint32_t crtc_pitch, pitch_pixels;
382 uint32_t tiling_flags;
384 uint32_t gen_cntl_reg, gen_cntl_val;
389 if (!atomic && !crtc->primary->fb) {
390 DRM_DEBUG_KMS("No FB bound\n");
395 radeon_fb = to_radeon_framebuffer(fb);
399 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
400 target_fb = crtc->primary->fb;
403 switch (target_fb->bits_per_pixel) {
423 /* Pin framebuffer & get tilling informations */
424 obj = radeon_fb->obj;
425 rbo = gem_to_radeon_bo(obj);
427 r = radeon_bo_reserve(rbo, false);
428 if (unlikely(r != 0))
430 /* Only 27 bit offset for legacy CRTC */
431 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
433 if (unlikely(r != 0)) {
434 radeon_bo_unreserve(rbo);
436 /* On old GPU like RN50 with little vram pining can fails because
437 * current fb is taking all space needed. So instead of unpining
438 * the old buffer after pining the new one, first unpin old one
439 * and then retry pining new one.
441 * As only master can set mode only master can pin and it is
442 * unlikely the master client will race with itself especialy
443 * on those old gpu with single crtc.
445 * We don't shutdown the display controller because new buffer
446 * will end up in same spot.
448 if (!atomic && fb && fb != crtc->primary->fb) {
449 struct radeon_bo *old_rbo;
450 unsigned long nsize, osize;
452 old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
453 osize = radeon_bo_size(old_rbo);
454 nsize = radeon_bo_size(rbo);
455 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
456 radeon_bo_unpin(old_rbo);
457 radeon_bo_unreserve(old_rbo);
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
465 radeon_bo_unreserve(rbo);
466 if (tiling_flags & RADEON_TILING_MICRO)
467 DRM_ERROR("trying to scanout microtiled buffer\n");
469 /* if scanout was in GTT this really wouldn't work */
470 /* crtc offset is from display base addr not FB location */
471 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
473 base -= radeon_crtc->legacy_display_base_addr;
475 crtc_offset_cntl = 0;
477 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
478 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) +
479 ((target_fb->bits_per_pixel * 8) - 1)) /
480 (target_fb->bits_per_pixel * 8));
481 crtc_pitch |= crtc_pitch << 16;
483 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
484 if (tiling_flags & RADEON_TILING_MACRO) {
485 if (ASIC_IS_R300(rdev))
486 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
487 R300_CRTC_MICRO_TILE_BUFFER_DIS |
488 R300_CRTC_MACRO_TILE_EN);
490 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
492 if (ASIC_IS_R300(rdev))
493 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
494 R300_CRTC_MICRO_TILE_BUFFER_DIS |
495 R300_CRTC_MACRO_TILE_EN);
497 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
500 if (tiling_flags & RADEON_TILING_MACRO) {
501 if (ASIC_IS_R300(rdev)) {
502 crtc_tile_x0_y0 = x | (y << 16);
505 int byteshift = target_fb->bits_per_pixel >> 4;
506 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
507 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
508 crtc_offset_cntl |= (y % 16);
511 int offset = y * pitch_pixels + x;
512 switch (target_fb->bits_per_pixel) {
534 if (radeon_crtc->crtc_id == 1)
535 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
537 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
539 gen_cntl_val = RREG32(gen_cntl_reg);
540 gen_cntl_val &= ~(0xf << 8);
541 gen_cntl_val |= (format << 8);
542 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
543 WREG32(gen_cntl_reg, gen_cntl_val);
545 crtc_offset = (u32)base;
547 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
549 if (ASIC_IS_R300(rdev)) {
550 if (radeon_crtc->crtc_id)
551 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
553 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
555 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
556 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
557 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
559 if (!atomic && fb && fb != crtc->primary->fb) {
560 radeon_fb = to_radeon_framebuffer(fb);
561 rbo = gem_to_radeon_bo(radeon_fb->obj);
562 r = radeon_bo_reserve(rbo, false);
563 if (unlikely(r != 0))
565 radeon_bo_unpin(rbo);
566 radeon_bo_unreserve(rbo);
569 /* Bytes per pixel may have changed */
570 radeon_bandwidth_update(rdev);
575 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
577 struct drm_device *dev = crtc->dev;
578 struct radeon_device *rdev = dev->dev_private;
579 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
580 struct drm_encoder *encoder;
585 uint32_t crtc_h_total_disp;
586 uint32_t crtc_h_sync_strt_wid;
587 uint32_t crtc_v_total_disp;
588 uint32_t crtc_v_sync_strt_wid;
592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
593 if (encoder->crtc == crtc) {
594 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
595 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
597 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
603 switch (crtc->primary->fb->bits_per_pixel) {
623 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
624 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
626 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
629 hsync_start = mode->crtc_hsync_start - 8;
631 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
632 | ((hsync_wid & 0x3f) << 16)
633 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
634 ? RADEON_CRTC_H_SYNC_POL
637 /* This works for double scan mode. */
638 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
639 | ((mode->crtc_vdisplay - 1) << 16));
641 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
645 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
646 | ((vsync_wid & 0x1f) << 16)
647 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
648 ? RADEON_CRTC_V_SYNC_POL
651 if (radeon_crtc->crtc_id) {
652 uint32_t crtc2_gen_cntl;
653 uint32_t disp2_merge_cntl;
655 /* if TV DAC is enabled for another crtc and keep it enabled */
656 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
657 crtc2_gen_cntl |= ((format << 8)
658 | RADEON_CRTC2_VSYNC_DIS
659 | RADEON_CRTC2_HSYNC_DIS
660 | RADEON_CRTC2_DISP_DIS
661 | RADEON_CRTC2_DISP_REQ_EN_B
662 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
663 ? RADEON_CRTC2_DBL_SCAN_EN
665 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
666 ? RADEON_CRTC2_CSYNC_EN
668 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
669 ? RADEON_CRTC2_INTERLACE_EN
672 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
673 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
674 crtc2_gen_cntl |= RADEON_CRTC2_EN;
676 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
677 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
679 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
680 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
682 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
683 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
685 uint32_t crtc_gen_cntl;
686 uint32_t crtc_ext_cntl;
687 uint32_t disp_merge_cntl;
689 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
690 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
692 | RADEON_CRTC_DISP_REQ_EN_B
693 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
694 ? RADEON_CRTC_DBL_SCAN_EN
696 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
697 ? RADEON_CRTC_CSYNC_EN
699 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
700 ? RADEON_CRTC_INTERLACE_EN
703 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
704 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
705 crtc_gen_cntl |= RADEON_CRTC_EN;
707 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
708 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
709 RADEON_CRTC_VSYNC_DIS |
710 RADEON_CRTC_HSYNC_DIS |
711 RADEON_CRTC_DISPLAY_DIS);
713 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
714 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
716 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
717 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
718 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
722 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
723 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
724 &crtc_v_sync_strt_wid);
726 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
727 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
728 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
729 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
734 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
736 struct drm_device *dev = crtc->dev;
737 struct radeon_device *rdev = dev->dev_private;
738 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
739 struct drm_encoder *encoder;
740 uint32_t feedback_div = 0;
741 uint32_t frac_fb_div = 0;
742 uint32_t reference_div = 0;
743 uint32_t post_divider = 0;
746 bool use_bios_divs = false;
748 uint32_t pll_ref_div = 0;
749 uint32_t pll_fb_post_div = 0;
750 uint32_t htotal_cntl = 0;
752 struct radeon_pll *pll;
757 } *post_div, post_divs[] = {
758 /* From RAGE 128 VR/RAGE 128 GL Register
759 * Reference Manual (Technical Reference
760 * Manual P/N RRG-G04100-C Rev. 0.04), page
761 * 3-17 (PLL_DIV_[3:0]).
763 { 1, 0 }, /* VCLK_SRC */
764 { 2, 1 }, /* VCLK_SRC/2 */
765 { 4, 2 }, /* VCLK_SRC/4 */
766 { 8, 3 }, /* VCLK_SRC/8 */
767 { 3, 4 }, /* VCLK_SRC/3 */
768 { 16, 5 }, /* VCLK_SRC/16 */
769 { 6, 6 }, /* VCLK_SRC/6 */
770 { 12, 7 }, /* VCLK_SRC/12 */
774 if (radeon_crtc->crtc_id)
775 pll = &rdev->clock.p2pll;
777 pll = &rdev->clock.p1pll;
779 pll->flags = RADEON_PLL_LEGACY;
781 if (mode->clock > 200000) /* range limits??? */
782 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
784 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
787 if (encoder->crtc == crtc) {
788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
790 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
795 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
796 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
797 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
798 if (!rdev->is_atom_bios) {
799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
800 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
802 if (lvds->use_bios_dividers) {
803 pll_ref_div = lvds->panel_ref_divider;
804 pll_fb_post_div = (lvds->panel_fb_divider |
805 (lvds->panel_post_divider << 16));
807 use_bios_divs = true;
811 pll->flags |= RADEON_PLL_USE_REF_DIV;
818 if (!use_bios_divs) {
819 radeon_compute_pll_legacy(pll, mode->clock,
820 &freq, &feedback_div, &frac_fb_div,
821 &reference_div, &post_divider);
823 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
824 if (post_div->divider == post_divider)
828 if (!post_div->divider)
829 post_div = &post_divs[0];
831 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
837 pll_ref_div = reference_div;
838 #if defined(__powerpc__) && (0) /* TODO */
839 /* apparently programming this otherwise causes a hang??? */
840 if (info->MacModel == RADEON_MAC_IBOOK)
841 pll_fb_post_div = 0x000600ad;
844 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
846 htotal_cntl = mode->htotal & 0x7;
850 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
852 pll_fb_post_div & 0x7ff);
854 if (radeon_crtc->crtc_id) {
855 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
856 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
857 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
860 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
861 &pll_ref_div, &pll_fb_post_div,
865 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
866 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
867 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
869 WREG32_PLL_P(RADEON_P2PLL_CNTL,
871 | RADEON_P2PLL_ATOMIC_UPDATE_EN
872 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
874 | RADEON_P2PLL_ATOMIC_UPDATE_EN
875 | RADEON_P2PLL_PVG_MASK));
877 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
879 ~RADEON_P2PLL_REF_DIV_MASK);
881 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
883 ~RADEON_P2PLL_FB0_DIV_MASK);
885 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
887 ~RADEON_P2PLL_POST0_DIV_MASK);
889 radeon_pll2_write_update(dev);
890 radeon_pll2_wait_for_read_update_complete(dev);
892 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
894 WREG32_PLL_P(RADEON_P2PLL_CNTL,
898 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
900 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
901 (unsigned)pll_ref_div,
902 (unsigned)pll_fb_post_div,
903 (unsigned)htotal_cntl,
904 RREG32_PLL(RADEON_P2PLL_CNTL));
905 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
906 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
907 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
908 (unsigned)((pll_fb_post_div &
909 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
911 mdelay(50); /* Let the clock to lock */
913 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
914 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
915 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
917 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
919 uint32_t pixclks_cntl;
923 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
924 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
925 &pll_fb_post_div, &pixclks_cntl);
928 if (rdev->flags & RADEON_IS_MOBILITY) {
929 /* A temporal workaround for the occasional blanking on certain laptop panels.
930 This appears to related to the PLL divider registers (fail to lock?).
931 It occurs even when all dividers are the same with their old settings.
932 In this case we really don't need to fiddle with PLL registers.
933 By doing this we can avoid the blanking problem with some panels.
935 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
936 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
937 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
938 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
940 ~(RADEON_PLL_DIV_SEL));
941 r100_pll_errata_after_index(rdev);
946 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
947 RADEON_VCLK_SRC_SEL_CPUCLK,
948 ~(RADEON_VCLK_SRC_SEL_MASK));
949 WREG32_PLL_P(RADEON_PPLL_CNTL,
951 | RADEON_PPLL_ATOMIC_UPDATE_EN
952 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
953 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
955 | RADEON_PPLL_ATOMIC_UPDATE_EN
956 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
957 | RADEON_PPLL_PVG_MASK));
959 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
961 ~(RADEON_PLL_DIV_SEL));
962 r100_pll_errata_after_index(rdev);
964 if (ASIC_IS_R300(rdev) ||
965 (rdev->family == CHIP_RS300) ||
966 (rdev->family == CHIP_RS400) ||
967 (rdev->family == CHIP_RS480)) {
968 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
969 /* When restoring console mode, use saved PPLL_REF_DIV
972 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
976 /* R300 uses ref_div_acc field as real ref divider */
977 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
978 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
979 ~R300_PPLL_REF_DIV_ACC_MASK);
982 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
984 ~RADEON_PPLL_REF_DIV_MASK);
986 WREG32_PLL_P(RADEON_PPLL_DIV_3,
988 ~RADEON_PPLL_FB3_DIV_MASK);
990 WREG32_PLL_P(RADEON_PPLL_DIV_3,
992 ~RADEON_PPLL_POST3_DIV_MASK);
994 radeon_pll_write_update(dev);
995 radeon_pll_wait_for_read_update_complete(dev);
997 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
999 WREG32_PLL_P(RADEON_PPLL_CNTL,
1003 | RADEON_PPLL_ATOMIC_UPDATE_EN
1004 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1006 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1009 (unsigned)htotal_cntl,
1010 RREG32_PLL(RADEON_PPLL_CNTL));
1011 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1012 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1013 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1014 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1016 mdelay(50); /* Let the clock to lock */
1018 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1019 RADEON_VCLK_SRC_SEL_PPLLCLK,
1020 ~(RADEON_VCLK_SRC_SEL_MASK));
1023 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1027 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1028 const struct drm_display_mode *mode,
1029 struct drm_display_mode *adjusted_mode)
1031 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1036 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1037 struct drm_display_mode *mode,
1038 struct drm_display_mode *adjusted_mode,
1039 int x, int y, struct drm_framebuffer *old_fb)
1041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1044 radeon_crtc_set_base(crtc, x, y, old_fb);
1045 radeon_set_crtc_timing(crtc, adjusted_mode);
1046 radeon_set_pll(crtc, adjusted_mode);
1047 radeon_overscan_setup(crtc, adjusted_mode);
1048 if (radeon_crtc->crtc_id == 0) {
1049 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1051 if (radeon_crtc->rmx_type != RMX_OFF) {
1052 /* FIXME: only first crtc has rmx what should we
1055 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1058 radeon_cursor_reset(crtc);
1062 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1064 struct drm_device *dev = crtc->dev;
1065 struct drm_crtc *crtci;
1068 * The hardware wedges sometimes if you reconfigure one CRTC
1069 * whilst another is running (see fdo bug #24611).
1071 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1072 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1075 static void radeon_crtc_commit(struct drm_crtc *crtc)
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_crtc *crtci;
1081 * Reenable the CRTCs that should be running.
1083 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1085 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1089 static void radeon_crtc_disable(struct drm_crtc *crtc)
1091 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1092 if (crtc->primary->fb) {
1094 struct radeon_framebuffer *radeon_fb;
1095 struct radeon_bo *rbo;
1097 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1098 rbo = gem_to_radeon_bo(radeon_fb->obj);
1099 r = radeon_bo_reserve(rbo, false);
1101 DRM_ERROR("failed to reserve rbo before unpin\n");
1103 radeon_bo_unpin(rbo);
1104 radeon_bo_unreserve(rbo);
1109 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1110 .dpms = radeon_crtc_dpms,
1111 .mode_fixup = radeon_crtc_mode_fixup,
1112 .mode_set = radeon_crtc_mode_set,
1113 .mode_set_base = radeon_crtc_set_base,
1114 .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1115 .prepare = radeon_crtc_prepare,
1116 .commit = radeon_crtc_commit,
1117 .load_lut = radeon_crtc_load_lut,
1118 .disable = radeon_crtc_disable
1122 void radeon_legacy_init_crtc(struct drm_device *dev,
1123 struct radeon_crtc *radeon_crtc)
1125 if (radeon_crtc->crtc_id == 1)
1126 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1127 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);