2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/pci.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/vga_switcheroo.h>
35 #include <drm/drm_agpsupport.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_file.h>
38 #include <drm/drm_ioctl.h>
39 #include <drm/radeon_drm.h>
42 #include "radeon_asic.h"
43 #include "radeon_drv.h"
44 #include "radeon_kms.h"
46 #if defined(CONFIG_VGA_SWITCHEROO)
47 bool radeon_has_atpx(void);
49 static inline bool radeon_has_atpx(void) { return false; }
53 * radeon_driver_unload_kms - Main unload function for KMS.
55 * @dev: drm dev pointer
57 * This is the main unload function for KMS (all asics).
58 * It calls radeon_modeset_fini() to tear down the
59 * displays, and radeon_device_fini() to tear down
60 * the rest of the device (CP, writeback, etc.).
61 * Returns 0 on success.
63 void radeon_driver_unload_kms(struct drm_device *dev)
65 struct radeon_device *rdev = dev->dev_private;
70 if (rdev->rmmio == NULL)
73 if (radeon_is_px(dev)) {
74 pm_runtime_get_sync(dev->dev);
75 pm_runtime_forbid(dev->dev);
78 radeon_acpi_fini(rdev);
80 radeon_modeset_fini(rdev);
81 radeon_device_fini(rdev);
84 arch_phys_wc_del(dev->agp->agp_mtrr);
90 dev->dev_private = NULL;
94 * radeon_driver_load_kms - Main load function for KMS.
96 * @dev: drm dev pointer
97 * @flags: device flags
99 * This is the main load function for KMS (all asics).
100 * It calls radeon_device_init() to set up the non-display
101 * parts of the chip (asic init, CP, writeback, etc.), and
102 * radeon_modeset_init() to set up the display parts
103 * (crtcs, encoders, hotplug detect, etc.).
104 * Returns 0 on success, error on failure.
106 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
108 struct pci_dev *pdev = to_pci_dev(dev->dev);
109 struct radeon_device *rdev;
112 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
116 dev->dev_private = (void *)rdev;
119 rdev->hose = pdev->sysdata;
122 /* update BUS flag */
123 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
124 flags |= RADEON_IS_AGP;
125 } else if (pci_is_pcie(pdev)) {
126 flags |= RADEON_IS_PCIE;
128 flags |= RADEON_IS_PCI;
131 if ((radeon_runtime_pm != 0) &&
133 ((flags & RADEON_IS_IGP) == 0) &&
134 !pci_is_thunderbolt_attached(pdev))
135 flags |= RADEON_IS_PX;
137 /* radeon_device_init should report only fatal error
138 * like memory allocation failure or iomapping failure,
139 * or memory manager initialization failure, it must
140 * properly initialize the GPU MC controller and permit
143 r = radeon_device_init(rdev, dev, pdev, flags);
145 dev_err(dev->dev, "Fatal error during GPU init\n");
149 /* Again modeset_init should fail only on fatal error
150 * otherwise it should provide enough functionalities
151 * for shadowfb to run
153 r = radeon_modeset_init(rdev);
155 dev_err(dev->dev, "Fatal error during modeset init\n");
157 /* Call ACPI methods: require modeset init
158 * but failure is not fatal
161 acpi_status = radeon_acpi_init(rdev);
163 dev_dbg(dev->dev, "Error during ACPI methods call\n");
166 if (radeon_is_px(dev)) {
167 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
168 pm_runtime_use_autosuspend(dev->dev);
169 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
170 pm_runtime_set_active(dev->dev);
171 pm_runtime_allow(dev->dev);
172 pm_runtime_mark_last_busy(dev->dev);
173 pm_runtime_put_autosuspend(dev->dev);
178 radeon_driver_unload_kms(dev);
185 * radeon_set_filp_rights - Set filp right.
187 * @dev: drm dev pointer
192 * Sets the filp rights for the device (all asics).
194 static void radeon_set_filp_rights(struct drm_device *dev,
195 struct drm_file **owner,
196 struct drm_file *applier,
199 struct radeon_device *rdev = dev->dev_private;
201 mutex_lock(&rdev->gem.mutex);
206 } else if (*value == 0) {
208 if (*owner == applier)
211 *value = *owner == applier ? 1 : 0;
212 mutex_unlock(&rdev->gem.mutex);
216 * Userspace get information ioctl
219 * radeon_info_ioctl - answer a device specific request.
221 * @dev: drm device pointer
222 * @data: request object
225 * This function is used to pass device specific parameters to the userspace
226 * drivers. Examples include: pci device id, pipeline parms, tiling params,
228 * Returns 0 on success, -EINVAL on failure.
230 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
232 struct radeon_device *rdev = dev->dev_private;
233 struct drm_radeon_info *info = data;
234 struct radeon_mode_info *minfo = &rdev->mode_info;
235 uint32_t *value, value_tmp, *value_ptr, value_size;
237 struct drm_crtc *crtc;
240 value_ptr = (uint32_t *)((unsigned long)info->value);
242 value_size = sizeof(uint32_t);
244 switch (info->request) {
245 case RADEON_INFO_DEVICE_ID:
246 *value = to_pci_dev(dev->dev)->device;
248 case RADEON_INFO_NUM_GB_PIPES:
249 *value = rdev->num_gb_pipes;
251 case RADEON_INFO_NUM_Z_PIPES:
252 *value = rdev->num_z_pipes;
254 case RADEON_INFO_ACCEL_WORKING:
255 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
256 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
259 *value = rdev->accel_working;
261 case RADEON_INFO_CRTC_FROM_ID:
262 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
263 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
266 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
267 crtc = (struct drm_crtc *)minfo->crtcs[i];
268 if (crtc && crtc->base.id == *value) {
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
270 *value = radeon_crtc->crtc_id;
276 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
280 case RADEON_INFO_ACCEL_WORKING2:
281 if (rdev->family == CHIP_HAWAII) {
282 if (rdev->accel_working) {
291 *value = rdev->accel_working;
294 case RADEON_INFO_TILING_CONFIG:
295 if (rdev->family >= CHIP_BONAIRE)
296 *value = rdev->config.cik.tile_config;
297 else if (rdev->family >= CHIP_TAHITI)
298 *value = rdev->config.si.tile_config;
299 else if (rdev->family >= CHIP_CAYMAN)
300 *value = rdev->config.cayman.tile_config;
301 else if (rdev->family >= CHIP_CEDAR)
302 *value = rdev->config.evergreen.tile_config;
303 else if (rdev->family >= CHIP_RV770)
304 *value = rdev->config.rv770.tile_config;
305 else if (rdev->family >= CHIP_R600)
306 *value = rdev->config.r600.tile_config;
308 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
312 case RADEON_INFO_WANT_HYPERZ:
313 /* The "value" here is both an input and output parameter.
314 * If the input value is 1, filp requests hyper-z access.
315 * If the input value is 0, filp revokes its hyper-z access.
317 * When returning, the value is 1 if filp owns hyper-z access,
319 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
320 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
324 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
327 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
329 case RADEON_INFO_WANT_CMASK:
330 /* The same logic as Hyper-Z. */
331 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
332 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
336 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
339 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
341 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
342 /* return clock value in KHz */
343 if (rdev->asic->get_xclk)
344 *value = radeon_get_xclk(rdev) * 10;
346 *value = rdev->clock.spll.reference_freq * 10;
348 case RADEON_INFO_NUM_BACKENDS:
349 if (rdev->family >= CHIP_BONAIRE)
350 *value = rdev->config.cik.max_backends_per_se *
351 rdev->config.cik.max_shader_engines;
352 else if (rdev->family >= CHIP_TAHITI)
353 *value = rdev->config.si.max_backends_per_se *
354 rdev->config.si.max_shader_engines;
355 else if (rdev->family >= CHIP_CAYMAN)
356 *value = rdev->config.cayman.max_backends_per_se *
357 rdev->config.cayman.max_shader_engines;
358 else if (rdev->family >= CHIP_CEDAR)
359 *value = rdev->config.evergreen.max_backends;
360 else if (rdev->family >= CHIP_RV770)
361 *value = rdev->config.rv770.max_backends;
362 else if (rdev->family >= CHIP_R600)
363 *value = rdev->config.r600.max_backends;
368 case RADEON_INFO_NUM_TILE_PIPES:
369 if (rdev->family >= CHIP_BONAIRE)
370 *value = rdev->config.cik.max_tile_pipes;
371 else if (rdev->family >= CHIP_TAHITI)
372 *value = rdev->config.si.max_tile_pipes;
373 else if (rdev->family >= CHIP_CAYMAN)
374 *value = rdev->config.cayman.max_tile_pipes;
375 else if (rdev->family >= CHIP_CEDAR)
376 *value = rdev->config.evergreen.max_tile_pipes;
377 else if (rdev->family >= CHIP_RV770)
378 *value = rdev->config.rv770.max_tile_pipes;
379 else if (rdev->family >= CHIP_R600)
380 *value = rdev->config.r600.max_tile_pipes;
385 case RADEON_INFO_FUSION_GART_WORKING:
388 case RADEON_INFO_BACKEND_MAP:
389 if (rdev->family >= CHIP_BONAIRE)
390 *value = rdev->config.cik.backend_map;
391 else if (rdev->family >= CHIP_TAHITI)
392 *value = rdev->config.si.backend_map;
393 else if (rdev->family >= CHIP_CAYMAN)
394 *value = rdev->config.cayman.backend_map;
395 else if (rdev->family >= CHIP_CEDAR)
396 *value = rdev->config.evergreen.backend_map;
397 else if (rdev->family >= CHIP_RV770)
398 *value = rdev->config.rv770.backend_map;
399 else if (rdev->family >= CHIP_R600)
400 *value = rdev->config.r600.backend_map;
405 case RADEON_INFO_VA_START:
406 /* this is where we report if vm is supported or not */
407 if (rdev->family < CHIP_CAYMAN)
409 *value = RADEON_VA_RESERVED_SIZE;
411 case RADEON_INFO_IB_VM_MAX_SIZE:
412 /* this is where we report if vm is supported or not */
413 if (rdev->family < CHIP_CAYMAN)
415 *value = RADEON_IB_VM_MAX_SIZE;
417 case RADEON_INFO_MAX_PIPES:
418 if (rdev->family >= CHIP_BONAIRE)
419 *value = rdev->config.cik.max_cu_per_sh;
420 else if (rdev->family >= CHIP_TAHITI)
421 *value = rdev->config.si.max_cu_per_sh;
422 else if (rdev->family >= CHIP_CAYMAN)
423 *value = rdev->config.cayman.max_pipes_per_simd;
424 else if (rdev->family >= CHIP_CEDAR)
425 *value = rdev->config.evergreen.max_pipes;
426 else if (rdev->family >= CHIP_RV770)
427 *value = rdev->config.rv770.max_pipes;
428 else if (rdev->family >= CHIP_R600)
429 *value = rdev->config.r600.max_pipes;
434 case RADEON_INFO_TIMESTAMP:
435 if (rdev->family < CHIP_R600) {
436 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
439 value = (uint32_t*)&value64;
440 value_size = sizeof(uint64_t);
441 value64 = radeon_get_gpu_clock_counter(rdev);
443 case RADEON_INFO_MAX_SE:
444 if (rdev->family >= CHIP_BONAIRE)
445 *value = rdev->config.cik.max_shader_engines;
446 else if (rdev->family >= CHIP_TAHITI)
447 *value = rdev->config.si.max_shader_engines;
448 else if (rdev->family >= CHIP_CAYMAN)
449 *value = rdev->config.cayman.max_shader_engines;
450 else if (rdev->family >= CHIP_CEDAR)
451 *value = rdev->config.evergreen.num_ses;
455 case RADEON_INFO_MAX_SH_PER_SE:
456 if (rdev->family >= CHIP_BONAIRE)
457 *value = rdev->config.cik.max_sh_per_se;
458 else if (rdev->family >= CHIP_TAHITI)
459 *value = rdev->config.si.max_sh_per_se;
463 case RADEON_INFO_FASTFB_WORKING:
464 *value = rdev->fastfb_working;
466 case RADEON_INFO_RING_WORKING:
467 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
468 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
472 case RADEON_CS_RING_GFX:
473 case RADEON_CS_RING_COMPUTE:
474 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
476 case RADEON_CS_RING_DMA:
477 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
478 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
480 case RADEON_CS_RING_UVD:
481 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
483 case RADEON_CS_RING_VCE:
484 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
490 case RADEON_INFO_SI_TILE_MODE_ARRAY:
491 if (rdev->family >= CHIP_BONAIRE) {
492 value = rdev->config.cik.tile_mode_array;
493 value_size = sizeof(uint32_t)*32;
494 } else if (rdev->family >= CHIP_TAHITI) {
495 value = rdev->config.si.tile_mode_array;
496 value_size = sizeof(uint32_t)*32;
498 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
502 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
503 if (rdev->family >= CHIP_BONAIRE) {
504 value = rdev->config.cik.macrotile_mode_array;
505 value_size = sizeof(uint32_t)*16;
507 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
511 case RADEON_INFO_SI_CP_DMA_COMPUTE:
514 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
515 if (rdev->family >= CHIP_BONAIRE) {
516 *value = rdev->config.cik.backend_enable_mask;
517 } else if (rdev->family >= CHIP_TAHITI) {
518 *value = rdev->config.si.backend_enable_mask;
520 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
523 case RADEON_INFO_MAX_SCLK:
524 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
525 rdev->pm.dpm_enabled)
526 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
528 *value = rdev->pm.default_sclk * 10;
530 case RADEON_INFO_VCE_FW_VERSION:
531 *value = rdev->vce.fw_version;
533 case RADEON_INFO_VCE_FB_VERSION:
534 *value = rdev->vce.fb_version;
536 case RADEON_INFO_NUM_BYTES_MOVED:
537 value = (uint32_t*)&value64;
538 value_size = sizeof(uint64_t);
539 value64 = atomic64_read(&rdev->num_bytes_moved);
541 case RADEON_INFO_VRAM_USAGE:
542 value = (uint32_t*)&value64;
543 value_size = sizeof(uint64_t);
544 value64 = atomic64_read(&rdev->vram_usage);
546 case RADEON_INFO_GTT_USAGE:
547 value = (uint32_t*)&value64;
548 value_size = sizeof(uint64_t);
549 value64 = atomic64_read(&rdev->gtt_usage);
551 case RADEON_INFO_ACTIVE_CU_COUNT:
552 if (rdev->family >= CHIP_BONAIRE)
553 *value = rdev->config.cik.active_cus;
554 else if (rdev->family >= CHIP_TAHITI)
555 *value = rdev->config.si.active_cus;
556 else if (rdev->family >= CHIP_CAYMAN)
557 *value = rdev->config.cayman.active_simds;
558 else if (rdev->family >= CHIP_CEDAR)
559 *value = rdev->config.evergreen.active_simds;
560 else if (rdev->family >= CHIP_RV770)
561 *value = rdev->config.rv770.active_simds;
562 else if (rdev->family >= CHIP_R600)
563 *value = rdev->config.r600.active_simds;
567 case RADEON_INFO_CURRENT_GPU_TEMP:
568 /* get temperature in millidegrees C */
569 if (rdev->asic->pm.get_temperature)
570 *value = radeon_get_temperature(rdev);
574 case RADEON_INFO_CURRENT_GPU_SCLK:
575 /* get sclk in Mhz */
576 if (rdev->pm.dpm_enabled)
577 *value = radeon_dpm_get_current_sclk(rdev) / 100;
579 *value = rdev->pm.current_sclk / 100;
581 case RADEON_INFO_CURRENT_GPU_MCLK:
582 /* get mclk in Mhz */
583 if (rdev->pm.dpm_enabled)
584 *value = radeon_dpm_get_current_mclk(rdev) / 100;
586 *value = rdev->pm.current_mclk / 100;
588 case RADEON_INFO_READ_REG:
589 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
590 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
593 if (radeon_get_allowed_info_register(rdev, *value, value))
596 case RADEON_INFO_VA_UNMAP_WORKING:
599 case RADEON_INFO_GPU_RESET_COUNTER:
600 *value = atomic_read(&rdev->gpu_reset_counter);
603 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
606 if (copy_to_user(value_ptr, (char*)value, value_size)) {
607 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
615 * Outdated mess for old drm with Xorg being in charge (void function now).
618 * radeon_driver_lastclose_kms - drm callback for last close
620 * @dev: drm dev pointer
622 * Switch vga_switcheroo state after last close (all asics).
624 void radeon_driver_lastclose_kms(struct drm_device *dev)
626 drm_fb_helper_lastclose(dev);
627 vga_switcheroo_process_delayed_switch();
631 * radeon_driver_open_kms - drm callback for open
633 * @dev: drm dev pointer
634 * @file_priv: drm file
636 * On device open, init vm on cayman+ (all asics).
637 * Returns 0 on success, error on failure.
639 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
641 struct radeon_device *rdev = dev->dev_private;
644 file_priv->driver_priv = NULL;
646 r = pm_runtime_get_sync(dev->dev);
648 pm_runtime_put_autosuspend(dev->dev);
652 /* new gpu have virtual address space support */
653 if (rdev->family >= CHIP_CAYMAN) {
654 struct radeon_fpriv *fpriv;
655 struct radeon_vm *vm;
657 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
658 if (unlikely(!fpriv)) {
663 if (rdev->accel_working) {
665 r = radeon_vm_init(rdev, vm);
671 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
673 radeon_vm_fini(rdev, vm);
678 /* map the ib pool buffer read only into
679 * virtual address space */
680 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
681 rdev->ring_tmp_bo.bo);
682 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
684 RADEON_VM_PAGE_READABLE |
685 RADEON_VM_PAGE_SNOOPED);
687 radeon_vm_fini(rdev, vm);
692 file_priv->driver_priv = fpriv;
696 pm_runtime_mark_last_busy(dev->dev);
697 pm_runtime_put_autosuspend(dev->dev);
702 * radeon_driver_postclose_kms - drm callback for post close
704 * @dev: drm dev pointer
705 * @file_priv: drm file
707 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
708 * (all asics). And tear down vm on cayman+ (all asics).
710 void radeon_driver_postclose_kms(struct drm_device *dev,
711 struct drm_file *file_priv)
713 struct radeon_device *rdev = dev->dev_private;
715 pm_runtime_get_sync(dev->dev);
717 mutex_lock(&rdev->gem.mutex);
718 if (rdev->hyperz_filp == file_priv)
719 rdev->hyperz_filp = NULL;
720 if (rdev->cmask_filp == file_priv)
721 rdev->cmask_filp = NULL;
722 mutex_unlock(&rdev->gem.mutex);
724 radeon_uvd_free_handles(rdev, file_priv);
725 radeon_vce_free_handles(rdev, file_priv);
727 /* new gpu have virtual address space support */
728 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
729 struct radeon_fpriv *fpriv = file_priv->driver_priv;
730 struct radeon_vm *vm = &fpriv->vm;
733 if (rdev->accel_working) {
734 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
737 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
738 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
740 radeon_vm_fini(rdev, vm);
744 file_priv->driver_priv = NULL;
746 pm_runtime_mark_last_busy(dev->dev);
747 pm_runtime_put_autosuspend(dev->dev);
751 * VBlank related functions.
754 * radeon_get_vblank_counter_kms - get frame count
756 * @crtc: crtc to get the frame count from
758 * Gets the frame count on the requested crtc (all asics).
759 * Returns frame count on success, -EINVAL on failure.
761 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
763 struct drm_device *dev = crtc->dev;
764 unsigned int pipe = crtc->index;
765 int vpos, hpos, stat;
767 struct radeon_device *rdev = dev->dev_private;
769 if (pipe >= rdev->num_crtc) {
770 DRM_ERROR("Invalid crtc %u\n", pipe);
774 /* The hw increments its frame counter at start of vsync, not at start
775 * of vblank, as is required by DRM core vblank counter handling.
776 * Cook the hw count here to make it appear to the caller as if it
777 * incremented at start of vblank. We measure distance to start of
778 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
779 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
780 * result by 1 to give the proper appearance to caller.
782 if (rdev->mode_info.crtcs[pipe]) {
783 /* Repeat readout if needed to provide stable result if
784 * we cross start of vsync during the queries.
787 count = radeon_get_vblank_counter(rdev, pipe);
788 /* Ask radeon_get_crtc_scanoutpos to return vpos as
789 * distance to start of vblank, instead of regular
790 * vertical scanout pos.
792 stat = radeon_get_crtc_scanoutpos(
793 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
794 &vpos, &hpos, NULL, NULL,
795 &rdev->mode_info.crtcs[pipe]->base.hwmode);
796 } while (count != radeon_get_vblank_counter(rdev, pipe));
798 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
799 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
800 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
803 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
806 /* Bump counter if we are at >= leading edge of vblank,
807 * but before vsync where vpos would turn negative and
808 * the hw counter really increments.
815 /* Fallback to use value as is. */
816 count = radeon_get_vblank_counter(rdev, pipe);
817 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
824 * radeon_enable_vblank_kms - enable vblank interrupt
826 * @crtc: crtc to enable vblank interrupt for
828 * Enable the interrupt on the requested crtc (all asics).
829 * Returns 0 on success, -EINVAL on failure.
831 int radeon_enable_vblank_kms(struct drm_crtc *crtc)
833 struct drm_device *dev = crtc->dev;
834 unsigned int pipe = crtc->index;
835 struct radeon_device *rdev = dev->dev_private;
836 unsigned long irqflags;
839 if (pipe >= rdev->num_crtc) {
840 DRM_ERROR("Invalid crtc %d\n", pipe);
844 spin_lock_irqsave(&rdev->irq.lock, irqflags);
845 rdev->irq.crtc_vblank_int[pipe] = true;
846 r = radeon_irq_set(rdev);
847 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
852 * radeon_disable_vblank_kms - disable vblank interrupt
854 * @crtc: crtc to disable vblank interrupt for
856 * Disable the interrupt on the requested crtc (all asics).
858 void radeon_disable_vblank_kms(struct drm_crtc *crtc)
860 struct drm_device *dev = crtc->dev;
861 unsigned int pipe = crtc->index;
862 struct radeon_device *rdev = dev->dev_private;
863 unsigned long irqflags;
865 if (pipe >= rdev->num_crtc) {
866 DRM_ERROR("Invalid crtc %d\n", pipe);
870 spin_lock_irqsave(&rdev->irq.lock, irqflags);
871 rdev->irq.crtc_vblank_int[pipe] = false;
872 radeon_irq_set(rdev);
873 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);