2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/fdtable.h>
25 #include <linux/uaccess.h>
30 #include "radeon_kfd.h"
31 #include "radeon_ucode.h"
32 #include <linux/firmware.h>
34 #define CIK_PIPE_PER_MEC (4)
37 struct radeon_sa_bo *sa_bo;
42 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size);
43 static void fini_sa_manager(struct kgd_dev *kgd);
45 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
46 enum kgd_memory_pool pool, struct kgd_mem **mem);
48 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem);
50 static uint64_t get_vmem_size(struct kgd_dev *kgd);
51 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
53 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
54 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
57 * Register access functions
60 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
61 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
62 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
64 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
67 static int kgd_init_memory(struct kgd_dev *kgd);
69 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
70 uint32_t hpd_size, uint64_t hpd_gpu_addr);
72 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
73 uint32_t queue_id, uint32_t __user *wptr);
75 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
76 uint32_t pipe_id, uint32_t queue_id);
78 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
79 unsigned int timeout, uint32_t pipe_id,
82 static const struct kfd2kgd_calls kfd2kgd = {
83 .init_sa_manager = init_sa_manager,
84 .fini_sa_manager = fini_sa_manager,
85 .allocate_mem = allocate_mem,
87 .get_vmem_size = get_vmem_size,
88 .get_gpu_clock_counter = get_gpu_clock_counter,
89 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
90 .program_sh_mem_settings = kgd_program_sh_mem_settings,
91 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
92 .init_memory = kgd_init_memory,
93 .init_pipeline = kgd_init_pipeline,
94 .hqd_load = kgd_hqd_load,
95 .hqd_is_occupies = kgd_hqd_is_occupies,
96 .hqd_destroy = kgd_hqd_destroy,
97 .get_fw_version = get_fw_version
100 static const struct kgd2kfd_calls *kgd2kfd;
102 bool radeon_kfd_init(void)
104 #if defined(CONFIG_HSA_AMD_MODULE)
105 bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
106 const struct kgd2kfd_calls**);
108 kgd2kfd_init_p = symbol_request(kgd2kfd_init);
110 if (kgd2kfd_init_p == NULL)
113 if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
114 symbol_put(kgd2kfd_init);
121 #elif defined(CONFIG_HSA_AMD)
122 if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
134 void radeon_kfd_fini(void)
138 symbol_put(kgd2kfd_init);
142 void radeon_kfd_device_probe(struct radeon_device *rdev)
145 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
148 void radeon_kfd_device_init(struct radeon_device *rdev)
151 struct kgd2kfd_shared_resources gpu_resources = {
152 .compute_vmid_bitmap = 0xFF00,
154 .first_compute_pipe = 1,
155 .compute_pipe_count = 8 - 1,
158 radeon_doorbell_get_kfd_info(rdev,
159 &gpu_resources.doorbell_physical_address,
160 &gpu_resources.doorbell_aperture_size,
161 &gpu_resources.doorbell_start_offset);
163 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
167 void radeon_kfd_device_fini(struct radeon_device *rdev)
170 kgd2kfd->device_exit(rdev->kfd);
175 void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
178 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
181 void radeon_kfd_suspend(struct radeon_device *rdev)
184 kgd2kfd->suspend(rdev->kfd);
187 int radeon_kfd_resume(struct radeon_device *rdev)
192 r = kgd2kfd->resume(rdev->kfd);
197 static u32 pool_to_domain(enum kgd_memory_pool p)
200 case KGD_POOL_FRAMEBUFFER: return RADEON_GEM_DOMAIN_VRAM;
201 default: return RADEON_GEM_DOMAIN_GTT;
205 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size)
207 struct radeon_device *rdev = (struct radeon_device *)kgd;
212 r = radeon_sa_bo_manager_init(rdev, &rdev->kfd_bo,
214 RADEON_GPU_PAGE_SIZE,
215 RADEON_GEM_DOMAIN_GTT,
221 r = radeon_sa_bo_manager_start(rdev, &rdev->kfd_bo);
223 radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
228 static void fini_sa_manager(struct kgd_dev *kgd)
230 struct radeon_device *rdev = (struct radeon_device *)kgd;
234 radeon_sa_bo_manager_suspend(rdev, &rdev->kfd_bo);
235 radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
238 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
239 enum kgd_memory_pool pool, struct kgd_mem **mem)
241 struct radeon_device *rdev = (struct radeon_device *)kgd;
247 domain = pool_to_domain(pool);
248 if (domain != RADEON_GEM_DOMAIN_GTT) {
250 "Only allowed to allocate gart memory for kfd\n");
254 *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
258 r = radeon_sa_bo_new(rdev, &rdev->kfd_bo, &(*mem)->sa_bo, size,
261 dev_err(rdev->dev, "failed to get memory for kfd (%d)\n", r);
265 (*mem)->ptr = radeon_sa_bo_cpu_addr((*mem)->sa_bo);
266 (*mem)->gpu_addr = radeon_sa_bo_gpu_addr((*mem)->sa_bo);
271 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem)
273 struct radeon_device *rdev = (struct radeon_device *)kgd;
277 radeon_sa_bo_free(rdev, &mem->sa_bo, NULL);
281 static uint64_t get_vmem_size(struct kgd_dev *kgd)
283 struct radeon_device *rdev = (struct radeon_device *)kgd;
287 return rdev->mc.real_vram_size;
290 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
292 struct radeon_device *rdev = (struct radeon_device *)kgd;
294 return rdev->asic->get_gpu_clock_counter(rdev);
297 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
299 struct radeon_device *rdev = (struct radeon_device *)kgd;
301 /* The sclk is in quantas of 10kHz */
302 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
305 static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
307 return (struct radeon_device *)kgd;
310 static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
312 struct radeon_device *rdev = get_radeon_device(kgd);
314 writel(value, (void __iomem *)(rdev->rmmio + offset));
317 static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
319 struct radeon_device *rdev = get_radeon_device(kgd);
321 return readl((void __iomem *)(rdev->rmmio + offset));
324 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
325 uint32_t queue, uint32_t vmid)
327 struct radeon_device *rdev = get_radeon_device(kgd);
328 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
330 mutex_lock(&rdev->srbm_mutex);
331 write_register(kgd, SRBM_GFX_CNTL, value);
334 static void unlock_srbm(struct kgd_dev *kgd)
336 struct radeon_device *rdev = get_radeon_device(kgd);
338 write_register(kgd, SRBM_GFX_CNTL, 0);
339 mutex_unlock(&rdev->srbm_mutex);
342 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
345 uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
346 uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
348 lock_srbm(kgd, mec, pipe, queue_id, 0);
351 static void release_queue(struct kgd_dev *kgd)
356 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
357 uint32_t sh_mem_config,
358 uint32_t sh_mem_ape1_base,
359 uint32_t sh_mem_ape1_limit,
360 uint32_t sh_mem_bases)
362 lock_srbm(kgd, 0, 0, 0, vmid);
364 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
365 write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
366 write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
367 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
372 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
376 * We have to assume that there is no outstanding mapping.
377 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
378 * because a mapping is in progress or because a mapping finished and
380 * So the protocol is to always wait & clear.
382 uint32_t pasid_mapping = (pasid == 0) ? 0 :
383 (uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;
385 write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
388 while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
391 write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
396 static int kgd_init_memory(struct kgd_dev *kgd)
399 * Configure apertures:
400 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
401 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
402 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
405 uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);
407 for (i = 8; i < 16; i++) {
408 uint32_t sh_mem_config;
410 lock_srbm(kgd, 0, 0, 0, i);
412 sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
413 sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
415 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
417 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
419 /* Scratch aperture is not supported for now. */
420 write_register(kgd, SH_STATIC_MEM_CONFIG, 0);
422 /* APE1 disabled for now. */
423 write_register(kgd, SH_MEM_APE1_BASE, 1);
424 write_register(kgd, SH_MEM_APE1_LIMIT, 0);
432 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
433 uint32_t hpd_size, uint64_t hpd_gpu_addr)
435 uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
436 uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
438 lock_srbm(kgd, mec, pipe, 0, 0);
439 write_register(kgd, CP_HPD_EOP_BASE_ADDR,
440 lower_32_bits(hpd_gpu_addr >> 8));
441 write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
442 upper_32_bits(hpd_gpu_addr >> 8));
443 write_register(kgd, CP_HPD_EOP_VMID, 0);
444 write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
450 static inline struct cik_mqd *get_mqd(void *mqd)
452 return (struct cik_mqd *)mqd;
455 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
456 uint32_t queue_id, uint32_t __user *wptr)
458 uint32_t wptr_shadow, is_wptr_shadow_valid;
463 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
465 acquire_queue(kgd, pipe_id, queue_id);
466 write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
467 write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
468 write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
470 write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
471 write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
472 write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
474 write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
475 write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
476 write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
478 write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
480 write_register(kgd, CP_HQD_PERSISTENT_STATE,
481 m->cp_hqd_persistent_state);
482 write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
483 write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
485 write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
486 m->cp_hqd_atomic0_preop_lo);
488 write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
489 m->cp_hqd_atomic0_preop_hi);
491 write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
492 m->cp_hqd_atomic1_preop_lo);
494 write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
495 m->cp_hqd_atomic1_preop_hi);
497 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
498 m->cp_hqd_pq_rptr_report_addr_lo);
500 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
501 m->cp_hqd_pq_rptr_report_addr_hi);
503 write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
505 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
506 m->cp_hqd_pq_wptr_poll_addr_lo);
508 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
509 m->cp_hqd_pq_wptr_poll_addr_hi);
511 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
512 m->cp_hqd_pq_doorbell_control);
514 write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
516 write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
518 write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
519 write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
521 write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
523 if (is_wptr_shadow_valid)
524 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
526 write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
532 static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
533 uint32_t pipe_id, uint32_t queue_id)
539 acquire_queue(kgd, pipe_id, queue_id);
540 act = read_register(kgd, CP_HQD_ACTIVE);
542 low = lower_32_bits(queue_address >> 8);
543 high = upper_32_bits(queue_address >> 8);
545 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
546 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
553 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
554 unsigned int timeout, uint32_t pipe_id,
559 acquire_queue(kgd, pipe_id, queue_id);
560 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
562 write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
565 temp = read_register(kgd, CP_HQD_ACTIVE);
569 pr_err("kfd: cp queue preemption time out (%dms)\n",
581 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
583 struct radeon_device *rdev = (struct radeon_device *) kgd;
584 const union radeon_firmware_header *hdr;
586 BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
590 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
594 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
598 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
601 case KGD_ENGINE_MEC1:
602 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
605 case KGD_ENGINE_MEC2:
606 hdr = (const union radeon_firmware_header *)
611 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
614 case KGD_ENGINE_SDMA:
615 hdr = (const union radeon_firmware_header *)
626 /* Only 12 bit in use*/
627 return hdr->common.ucode_version;