2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <linux/export.h>
29 #include <drm/drm_device.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_pci.h>
32 #include <drm/radeon_drm.h>
37 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
38 struct i2c_msg *msgs, int num);
39 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
50 struct i2c_msg msgs[] = {
65 /* on hw with routers, select right port */
66 if (radeon_connector->router.ddc_valid)
67 radeon_router_select_ddc_port(radeon_connector);
70 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
72 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
76 /* Couldn't find an accessible DDC on this connector */
78 /* Probe also for valid EDID header
79 * EDID header starts with:
80 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
81 * Only the first 6 bytes must be valid as
82 * drm_edid_block_valid() can fix the last 2 bytes */
83 if (drm_edid_header_is_valid(buf) < 6) {
84 /* Couldn't find an accessible EDID on this
93 static int pre_xfer(struct i2c_adapter *i2c_adap)
95 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
96 struct radeon_device *rdev = i2c->dev->dev_private;
97 struct radeon_i2c_bus_rec *rec = &i2c->rec;
100 mutex_lock(&i2c->mutex);
102 /* RV410 appears to have a bug where the hw i2c in reset
103 * holds the i2c port in a bad state - switch hw i2c away before
104 * doing DDC - do this for all r200s/r300s/r400s for safety sake
106 if (rec->hw_capable) {
107 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
110 if (rdev->family >= CHIP_RV350)
111 reg = RADEON_GPIO_MONID;
112 else if ((rdev->family == CHIP_R300) ||
113 (rdev->family == CHIP_R350))
114 reg = RADEON_GPIO_DVI_DDC;
116 reg = RADEON_GPIO_CRT2_DDC;
118 mutex_lock(&rdev->dc_hw_i2c_mutex);
119 if (rec->a_clk_reg == reg) {
120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
121 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
126 mutex_unlock(&rdev->dc_hw_i2c_mutex);
130 /* switch the pads to ddc mode */
131 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
132 temp = RREG32(rec->mask_clk_reg);
134 WREG32(rec->mask_clk_reg, temp);
137 /* clear the output pin values */
138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
139 WREG32(rec->a_clk_reg, temp);
141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
142 WREG32(rec->a_data_reg, temp);
144 /* set the pins to input */
145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
146 WREG32(rec->en_clk_reg, temp);
148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
149 WREG32(rec->en_data_reg, temp);
151 /* mask the gpio pins for software use */
152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
153 WREG32(rec->mask_clk_reg, temp);
154 temp = RREG32(rec->mask_clk_reg);
156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
157 WREG32(rec->mask_data_reg, temp);
158 temp = RREG32(rec->mask_data_reg);
163 static void post_xfer(struct i2c_adapter *i2c_adap)
165 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
166 struct radeon_device *rdev = i2c->dev->dev_private;
167 struct radeon_i2c_bus_rec *rec = &i2c->rec;
170 /* unmask the gpio pins for software use */
171 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
172 WREG32(rec->mask_clk_reg, temp);
173 temp = RREG32(rec->mask_clk_reg);
175 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
176 WREG32(rec->mask_data_reg, temp);
177 temp = RREG32(rec->mask_data_reg);
179 mutex_unlock(&i2c->mutex);
182 static int get_clock(void *i2c_priv)
184 struct radeon_i2c_chan *i2c = i2c_priv;
185 struct radeon_device *rdev = i2c->dev->dev_private;
186 struct radeon_i2c_bus_rec *rec = &i2c->rec;
189 /* read the value off the pin */
190 val = RREG32(rec->y_clk_reg);
191 val &= rec->y_clk_mask;
197 static int get_data(void *i2c_priv)
199 struct radeon_i2c_chan *i2c = i2c_priv;
200 struct radeon_device *rdev = i2c->dev->dev_private;
201 struct radeon_i2c_bus_rec *rec = &i2c->rec;
204 /* read the value off the pin */
205 val = RREG32(rec->y_data_reg);
206 val &= rec->y_data_mask;
211 static void set_clock(void *i2c_priv, int clock)
213 struct radeon_i2c_chan *i2c = i2c_priv;
214 struct radeon_device *rdev = i2c->dev->dev_private;
215 struct radeon_i2c_bus_rec *rec = &i2c->rec;
218 /* set pin direction */
219 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
220 val |= clock ? 0 : rec->en_clk_mask;
221 WREG32(rec->en_clk_reg, val);
224 static void set_data(void *i2c_priv, int data)
226 struct radeon_i2c_chan *i2c = i2c_priv;
227 struct radeon_device *rdev = i2c->dev->dev_private;
228 struct radeon_i2c_bus_rec *rec = &i2c->rec;
231 /* set pin direction */
232 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
233 val |= data ? 0 : rec->en_data_mask;
234 WREG32(rec->en_data_reg, val);
239 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
241 u32 sclk = rdev->pm.current_sclk;
247 switch (rdev->family) {
261 nm = (sclk * 10) / (i2c_clock * 4);
262 for (loop = 1; loop < 255; loop++) {
263 if ((nm / loop) < loop)
268 prescale = m | (n << 8);
276 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
290 if (rdev->family == CHIP_R520)
291 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
293 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
319 DRM_ERROR("i2c: unhandled radeon chip\n");
326 /* hw i2c engine for r1xx-4xx hardware
327 * hw can buffer up to 15 bytes
329 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
330 struct i2c_msg *msgs, int num)
332 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
333 struct radeon_device *rdev = i2c->dev->dev_private;
334 struct radeon_i2c_bus_rec *rec = &i2c->rec;
336 int i, j, k, ret = num;
338 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
341 mutex_lock(&rdev->dc_hw_i2c_mutex);
342 /* take the pm lock since we need a constant sclk */
343 mutex_lock(&rdev->pm.mutex);
345 prescale = radeon_get_i2c_prescale(rdev);
347 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
348 RADEON_I2C_DRIVE_EN |
353 if (rdev->is_atom_bios) {
354 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
355 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
359 i2c_cntl_0 = RADEON_I2C_CNTL_0;
360 i2c_cntl_1 = RADEON_I2C_CNTL_1;
361 i2c_data = RADEON_I2C_DATA;
363 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
364 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
365 i2c_data = RADEON_DVI_I2C_DATA;
367 switch (rdev->family) {
374 switch (rec->mask_clk_reg) {
375 case RADEON_GPIO_DVI_DDC:
376 /* no gpio select bit */
379 DRM_ERROR("gpio not supported with hw i2c\n");
385 /* only bit 4 on r200 */
386 switch (rec->mask_clk_reg) {
387 case RADEON_GPIO_DVI_DDC:
388 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
390 case RADEON_GPIO_MONID:
391 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
394 DRM_ERROR("gpio not supported with hw i2c\n");
402 switch (rec->mask_clk_reg) {
403 case RADEON_GPIO_DVI_DDC:
404 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
406 case RADEON_GPIO_VGA_DDC:
407 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
409 case RADEON_GPIO_CRT2_DDC:
410 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
413 DRM_ERROR("gpio not supported with hw i2c\n");
420 /* only bit 4 on r300/r350 */
421 switch (rec->mask_clk_reg) {
422 case RADEON_GPIO_VGA_DDC:
423 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
425 case RADEON_GPIO_DVI_DDC:
426 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
429 DRM_ERROR("gpio not supported with hw i2c\n");
442 switch (rec->mask_clk_reg) {
443 case RADEON_GPIO_VGA_DDC:
444 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
446 case RADEON_GPIO_DVI_DDC:
447 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
449 case RADEON_GPIO_MONID:
450 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
453 DRM_ERROR("gpio not supported with hw i2c\n");
459 DRM_ERROR("unsupported asic\n");
466 /* check for bus probe */
468 if ((num == 1) && (p->len == 0)) {
469 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
472 RADEON_I2C_SOFT_RST));
473 WREG32(i2c_data, (p->addr << 1) & 0xff);
475 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
476 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
478 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
479 WREG32(i2c_cntl_0, reg);
480 for (k = 0; k < 32; k++) {
482 tmp = RREG32(i2c_cntl_0);
483 if (tmp & RADEON_I2C_GO)
485 tmp = RREG32(i2c_cntl_0);
486 if (tmp & RADEON_I2C_DONE)
489 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
490 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
498 for (i = 0; i < num; i++) {
500 for (j = 0; j < p->len; j++) {
501 if (p->flags & I2C_M_RD) {
502 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
505 RADEON_I2C_SOFT_RST));
506 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
507 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
508 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
510 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
511 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
512 for (k = 0; k < 32; k++) {
514 tmp = RREG32(i2c_cntl_0);
515 if (tmp & RADEON_I2C_GO)
517 tmp = RREG32(i2c_cntl_0);
518 if (tmp & RADEON_I2C_DONE)
521 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
522 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
527 p->buf[j] = RREG32(i2c_data) & 0xff;
529 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
532 RADEON_I2C_SOFT_RST));
533 WREG32(i2c_data, (p->addr << 1) & 0xff);
534 WREG32(i2c_data, p->buf[j]);
535 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
536 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
538 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
539 WREG32(i2c_cntl_0, reg);
540 for (k = 0; k < 32; k++) {
542 tmp = RREG32(i2c_cntl_0);
543 if (tmp & RADEON_I2C_GO)
545 tmp = RREG32(i2c_cntl_0);
546 if (tmp & RADEON_I2C_DONE)
549 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
550 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
560 WREG32(i2c_cntl_0, 0);
561 WREG32(i2c_cntl_1, 0);
562 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
565 RADEON_I2C_SOFT_RST));
567 if (rdev->is_atom_bios) {
568 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
569 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
570 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
573 mutex_unlock(&rdev->pm.mutex);
574 mutex_unlock(&rdev->dc_hw_i2c_mutex);
579 /* hw i2c engine for r5xx hardware
580 * hw can buffer up to 15 bytes
582 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
583 struct i2c_msg *msgs, int num)
585 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
586 struct radeon_device *rdev = i2c->dev->dev_private;
587 struct radeon_i2c_bus_rec *rec = &i2c->rec;
589 int i, j, remaining, current_count, buffer_offset, ret = num;
594 mutex_lock(&rdev->dc_hw_i2c_mutex);
595 /* take the pm lock since we need a constant sclk */
596 mutex_lock(&rdev->pm.mutex);
598 prescale = radeon_get_i2c_prescale(rdev);
600 /* clear gpio mask bits */
601 tmp = RREG32(rec->mask_clk_reg);
602 tmp &= ~rec->mask_clk_mask;
603 WREG32(rec->mask_clk_reg, tmp);
604 tmp = RREG32(rec->mask_clk_reg);
606 tmp = RREG32(rec->mask_data_reg);
607 tmp &= ~rec->mask_data_mask;
608 WREG32(rec->mask_data_reg, tmp);
609 tmp = RREG32(rec->mask_data_reg);
611 /* clear pin values */
612 tmp = RREG32(rec->a_clk_reg);
613 tmp &= ~rec->a_clk_mask;
614 WREG32(rec->a_clk_reg, tmp);
615 tmp = RREG32(rec->a_clk_reg);
617 tmp = RREG32(rec->a_data_reg);
618 tmp &= ~rec->a_data_mask;
619 WREG32(rec->a_data_reg, tmp);
620 tmp = RREG32(rec->a_data_reg);
622 /* set the pins to input */
623 tmp = RREG32(rec->en_clk_reg);
624 tmp &= ~rec->en_clk_mask;
625 WREG32(rec->en_clk_reg, tmp);
626 tmp = RREG32(rec->en_clk_reg);
628 tmp = RREG32(rec->en_data_reg);
629 tmp &= ~rec->en_data_mask;
630 WREG32(rec->en_data_reg, tmp);
631 tmp = RREG32(rec->en_data_reg);
634 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
635 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
636 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
637 saved2 = RREG32(0x494);
638 WREG32(0x494, saved2 | 0x1);
640 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
641 for (i = 0; i < 50; i++) {
643 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
647 DRM_ERROR("failed to get i2c bus\n");
652 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
653 switch (rec->mask_clk_reg) {
654 case AVIVO_DC_GPIO_DDC1_MASK:
655 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
657 case AVIVO_DC_GPIO_DDC2_MASK:
658 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
660 case AVIVO_DC_GPIO_DDC3_MASK:
661 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
664 DRM_ERROR("gpio not supported with hw i2c\n");
669 /* check for bus probe */
671 if ((num == 1) && (p->len == 0)) {
672 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
675 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
677 WREG32(AVIVO_DC_I2C_RESET, 0);
679 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
680 WREG32(AVIVO_DC_I2C_DATA, 0);
682 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
683 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
684 AVIVO_DC_I2C_DATA_COUNT(1) |
686 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
687 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
688 for (j = 0; j < 200; j++) {
690 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
691 if (tmp & AVIVO_DC_I2C_GO)
693 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
694 if (tmp & AVIVO_DC_I2C_DONE)
697 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
698 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
706 for (i = 0; i < num; i++) {
710 if (p->flags & I2C_M_RD) {
715 current_count = remaining;
716 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
719 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
721 WREG32(AVIVO_DC_I2C_RESET, 0);
723 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
724 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
725 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
726 AVIVO_DC_I2C_DATA_COUNT(current_count) |
728 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
729 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
730 for (j = 0; j < 200; j++) {
732 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
733 if (tmp & AVIVO_DC_I2C_GO)
735 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
736 if (tmp & AVIVO_DC_I2C_DONE)
739 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
740 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
745 for (j = 0; j < current_count; j++)
746 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
747 remaining -= current_count;
748 buffer_offset += current_count;
755 current_count = remaining;
756 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
759 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
761 WREG32(AVIVO_DC_I2C_RESET, 0);
763 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
764 for (j = 0; j < current_count; j++)
765 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
767 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
768 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
769 AVIVO_DC_I2C_DATA_COUNT(current_count) |
771 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
772 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
773 for (j = 0; j < 200; j++) {
775 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
776 if (tmp & AVIVO_DC_I2C_GO)
778 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
779 if (tmp & AVIVO_DC_I2C_DONE)
782 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
783 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
788 remaining -= current_count;
789 buffer_offset += current_count;
795 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
798 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
800 WREG32(AVIVO_DC_I2C_RESET, 0);
802 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
803 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
804 WREG32(0x494, saved2);
805 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
806 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
807 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
809 mutex_unlock(&rdev->pm.mutex);
810 mutex_unlock(&rdev->dc_hw_i2c_mutex);
815 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
816 struct i2c_msg *msgs, int num)
818 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
819 struct radeon_device *rdev = i2c->dev->dev_private;
820 struct radeon_i2c_bus_rec *rec = &i2c->rec;
823 mutex_lock(&i2c->mutex);
825 switch (rdev->family) {
844 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
849 /* XXX fill in hw i2c implementation */
858 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
860 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
866 /* XXX fill in hw i2c implementation */
876 /* XXX fill in hw i2c implementation */
883 /* XXX fill in hw i2c implementation */
886 DRM_ERROR("i2c: unhandled radeon chip\n");
891 mutex_unlock(&i2c->mutex);
896 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
898 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
901 static const struct i2c_algorithm radeon_i2c_algo = {
902 .master_xfer = radeon_hw_i2c_xfer,
903 .functionality = radeon_hw_i2c_func,
906 static const struct i2c_algorithm radeon_atom_i2c_algo = {
907 .master_xfer = radeon_atom_hw_i2c_xfer,
908 .functionality = radeon_atom_hw_i2c_func,
911 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
912 struct radeon_i2c_bus_rec *rec,
915 struct radeon_device *rdev = dev->dev_private;
916 struct radeon_i2c_chan *i2c;
919 /* don't add the mm_i2c bus unless hw_i2c is enabled */
920 if (rec->mm_i2c && (radeon_hw_i2c == 0))
923 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
928 i2c->adapter.owner = THIS_MODULE;
929 i2c->adapter.class = I2C_CLASS_DDC;
930 i2c->adapter.dev.parent = &dev->pdev->dev;
932 i2c_set_adapdata(&i2c->adapter, i2c);
933 mutex_init(&i2c->mutex);
937 ((rdev->family <= CHIP_RS480) ||
938 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
939 /* set the radeon hw i2c adapter */
940 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
941 "Radeon i2c hw bus %s", name);
942 i2c->adapter.algo = &radeon_i2c_algo;
943 ret = i2c_add_adapter(&i2c->adapter);
946 } else if (rec->hw_capable &&
948 ASIC_IS_DCE3(rdev)) {
949 /* hw i2c using atom */
950 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
951 "Radeon i2c hw bus %s", name);
952 i2c->adapter.algo = &radeon_atom_i2c_algo;
953 ret = i2c_add_adapter(&i2c->adapter);
957 /* set the radeon bit adapter */
958 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
959 "Radeon i2c bit bus %s", name);
960 i2c->adapter.algo_data = &i2c->bit;
961 i2c->bit.pre_xfer = pre_xfer;
962 i2c->bit.post_xfer = post_xfer;
963 i2c->bit.setsda = set_data;
964 i2c->bit.setscl = set_clock;
965 i2c->bit.getsda = get_data;
966 i2c->bit.getscl = get_clock;
967 i2c->bit.udelay = 10;
968 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
970 ret = i2c_bit_add_bus(&i2c->adapter);
972 DRM_ERROR("Failed to register bit i2c %s\n", name);
984 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
988 WARN_ON(i2c->has_aux);
989 i2c_del_adapter(&i2c->adapter);
993 /* Add the default buses */
994 void radeon_i2c_init(struct radeon_device *rdev)
997 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
999 if (rdev->is_atom_bios)
1000 radeon_atombios_i2c_init(rdev);
1002 radeon_combios_i2c_init(rdev);
1005 /* remove all the buses */
1006 void radeon_i2c_fini(struct radeon_device *rdev)
1010 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1011 if (rdev->i2c_bus[i]) {
1012 radeon_i2c_destroy(rdev->i2c_bus[i]);
1013 rdev->i2c_bus[i] = NULL;
1018 /* Add additional buses */
1019 void radeon_i2c_add(struct radeon_device *rdev,
1020 struct radeon_i2c_bus_rec *rec,
1023 struct drm_device *dev = rdev->ddev;
1026 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1027 if (!rdev->i2c_bus[i]) {
1028 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1034 /* looks up bus based on id */
1035 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1036 struct radeon_i2c_bus_rec *i2c_bus)
1040 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1041 if (rdev->i2c_bus[i] &&
1042 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1043 return rdev->i2c_bus[i];
1049 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1056 struct i2c_msg msgs[] = {
1074 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1076 DRM_DEBUG("val = 0x%02x\n", *val);
1078 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1083 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1089 struct i2c_msg msg = {
1099 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1100 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1104 /* ddc router switching */
1105 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1109 if (!radeon_connector->router.ddc_valid)
1112 if (!radeon_connector->router_bus)
1115 radeon_i2c_get_byte(radeon_connector->router_bus,
1116 radeon_connector->router.i2c_addr,
1118 val &= ~radeon_connector->router.ddc_mux_control_pin;
1119 radeon_i2c_put_byte(radeon_connector->router_bus,
1120 radeon_connector->router.i2c_addr,
1122 radeon_i2c_get_byte(radeon_connector->router_bus,
1123 radeon_connector->router.i2c_addr,
1125 val &= ~radeon_connector->router.ddc_mux_control_pin;
1126 val |= radeon_connector->router.ddc_mux_state;
1127 radeon_i2c_put_byte(radeon_connector->router_bus,
1128 radeon_connector->router.i2c_addr,
1132 /* clock/data router switching */
1133 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1137 if (!radeon_connector->router.cd_valid)
1140 if (!radeon_connector->router_bus)
1143 radeon_i2c_get_byte(radeon_connector->router_bus,
1144 radeon_connector->router.i2c_addr,
1146 val &= ~radeon_connector->router.cd_mux_control_pin;
1147 radeon_i2c_put_byte(radeon_connector->router_bus,
1148 radeon_connector->router.i2c_addr,
1150 radeon_i2c_get_byte(radeon_connector->router_bus,
1151 radeon_connector->router.i2c_addr,
1153 val &= ~radeon_connector->router.cd_mux_control_pin;
1154 val |= radeon_connector->router.cd_mux_state;
1155 radeon_i2c_put_byte(radeon_connector->router_bus,
1156 radeon_connector->router.i2c_addr,