2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_drm.h"
31 #include "radeon_reg.h"
35 * The GART (Graphics Aperture Remapping Table) is an aperture
36 * in the GPU's address space. System pages can be mapped into
37 * the aperture and look like contiguous pages from the GPU's
38 * perspective. A page table maps the pages in the aperture
39 * to the actual backing pages in system memory.
41 * Radeon GPUs support both an internal GART, as described above,
42 * and AGP. AGP works similarly, but the GART table is configured
43 * and maintained by the northbridge rather than the driver.
44 * Radeon hw has a separate AGP aperture that is programmed to
45 * point to the AGP aperture provided by the northbridge and the
46 * requests are passed through to the northbridge aperture.
47 * Both AGP and internal GART can be used at the same time, however
48 * that is not currently supported by the driver.
50 * This file handles the common internal GART management.
54 * Common GART table functions.
57 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
59 * @rdev: radeon_device pointer
61 * Allocate system memory for GART page table
62 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
63 * gart table to be in system memory.
64 * Returns 0 for success, -ENOMEM for failure.
66 int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
70 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
71 &rdev->gart.table_addr);
76 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
77 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
78 set_memory_uc((unsigned long)ptr,
79 rdev->gart.table_size >> PAGE_SHIFT);
83 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
88 * radeon_gart_table_ram_free - free system ram for gart page table
90 * @rdev: radeon_device pointer
92 * Free system memory for GART page table
93 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
94 * gart table to be in system memory.
96 void radeon_gart_table_ram_free(struct radeon_device *rdev)
98 if (rdev->gart.ptr == NULL) {
102 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
103 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
104 set_memory_wb((unsigned long)rdev->gart.ptr,
105 rdev->gart.table_size >> PAGE_SHIFT);
108 pci_free_consistent(rdev->pdev, rdev->gart.table_size,
109 (void *)rdev->gart.ptr,
110 rdev->gart.table_addr);
111 rdev->gart.ptr = NULL;
112 rdev->gart.table_addr = 0;
116 * radeon_gart_table_vram_alloc - allocate vram for gart page table
118 * @rdev: radeon_device pointer
120 * Allocate video memory for GART page table
121 * (pcie r4xx, r5xx+). These asics require the
122 * gart table to be in video memory.
123 * Returns 0 for success, error for failure.
125 int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
129 if (rdev->gart.robj == NULL) {
130 r = radeon_bo_create(rdev, rdev->gart.table_size,
131 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
132 NULL, &rdev->gart.robj);
141 * radeon_gart_table_vram_pin - pin gart page table in vram
143 * @rdev: radeon_device pointer
145 * Pin the GART page table in vram so it will not be moved
146 * by the memory manager (pcie r4xx, r5xx+). These asics require the
147 * gart table to be in video memory.
148 * Returns 0 for success, error for failure.
150 int radeon_gart_table_vram_pin(struct radeon_device *rdev)
155 r = radeon_bo_reserve(rdev->gart.robj, false);
156 if (unlikely(r != 0))
158 r = radeon_bo_pin(rdev->gart.robj,
159 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
161 radeon_bo_unreserve(rdev->gart.robj);
164 r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
166 radeon_bo_unpin(rdev->gart.robj);
167 radeon_bo_unreserve(rdev->gart.robj);
168 rdev->gart.table_addr = gpu_addr;
173 * radeon_gart_table_vram_unpin - unpin gart page table in vram
175 * @rdev: radeon_device pointer
177 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
178 * These asics require the gart table to be in video memory.
180 void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
184 if (rdev->gart.robj == NULL) {
187 r = radeon_bo_reserve(rdev->gart.robj, false);
188 if (likely(r == 0)) {
189 radeon_bo_kunmap(rdev->gart.robj);
190 radeon_bo_unpin(rdev->gart.robj);
191 radeon_bo_unreserve(rdev->gart.robj);
192 rdev->gart.ptr = NULL;
197 * radeon_gart_table_vram_free - free gart page table vram
199 * @rdev: radeon_device pointer
201 * Free the video memory used for the GART page table
202 * (pcie r4xx, r5xx+). These asics require the gart table to
203 * be in video memory.
205 void radeon_gart_table_vram_free(struct radeon_device *rdev)
207 if (rdev->gart.robj == NULL) {
210 radeon_gart_table_vram_unpin(rdev);
211 radeon_bo_unref(&rdev->gart.robj);
215 * Common gart functions.
218 * radeon_gart_unbind - unbind pages from the gart page table
220 * @rdev: radeon_device pointer
221 * @offset: offset into the GPU's gart aperture
222 * @pages: number of pages to unbind
224 * Unbinds the requested pages from the gart page table and
225 * replaces them with the dummy page (all asics).
227 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
235 if (!rdev->gart.ready) {
236 WARN(1, "trying to unbind memory from uninitialized GART !\n");
239 t = offset / RADEON_GPU_PAGE_SIZE;
240 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
241 for (i = 0; i < pages; i++, p++) {
242 if (rdev->gart.pages[p]) {
243 rdev->gart.pages[p] = NULL;
244 rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
245 page_base = rdev->gart.pages_addr[p];
246 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
247 if (rdev->gart.ptr) {
248 radeon_gart_set_page(rdev, t, page_base);
250 page_base += RADEON_GPU_PAGE_SIZE;
255 radeon_gart_tlb_flush(rdev);
259 * radeon_gart_bind - bind pages into the gart page table
261 * @rdev: radeon_device pointer
262 * @offset: offset into the GPU's gart aperture
263 * @pages: number of pages to bind
264 * @pagelist: pages to bind
265 * @dma_addr: DMA addresses of pages
267 * Binds the requested pages to the gart page table
269 * Returns 0 for success, -EINVAL for failure.
271 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
272 int pages, struct page **pagelist, dma_addr_t *dma_addr)
279 if (!rdev->gart.ready) {
280 WARN(1, "trying to bind memory to uninitialized GART !\n");
283 t = offset / RADEON_GPU_PAGE_SIZE;
284 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
286 for (i = 0; i < pages; i++, p++) {
287 rdev->gart.pages_addr[p] = dma_addr[i];
288 rdev->gart.pages[p] = pagelist[i];
289 if (rdev->gart.ptr) {
290 page_base = rdev->gart.pages_addr[p];
291 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
292 radeon_gart_set_page(rdev, t, page_base);
293 page_base += RADEON_GPU_PAGE_SIZE;
298 radeon_gart_tlb_flush(rdev);
303 * radeon_gart_restore - bind all pages in the gart page table
305 * @rdev: radeon_device pointer
307 * Binds all pages in the gart page table (all asics).
308 * Used to rebuild the gart table on device startup or resume.
310 void radeon_gart_restore(struct radeon_device *rdev)
315 if (!rdev->gart.ptr) {
318 for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
319 page_base = rdev->gart.pages_addr[i];
320 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
321 radeon_gart_set_page(rdev, t, page_base);
322 page_base += RADEON_GPU_PAGE_SIZE;
326 radeon_gart_tlb_flush(rdev);
330 * radeon_gart_init - init the driver info for managing the gart
332 * @rdev: radeon_device pointer
334 * Allocate the dummy page and init the gart driver info (all asics).
335 * Returns 0 for success, error for failure.
337 int radeon_gart_init(struct radeon_device *rdev)
341 if (rdev->gart.pages) {
344 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
345 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
346 DRM_ERROR("Page size is smaller than GPU page size!\n");
349 r = radeon_dummy_page_init(rdev);
352 /* Compute table size */
353 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
354 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
355 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
356 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
357 /* Allocate pages table */
358 rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
360 if (rdev->gart.pages == NULL) {
361 radeon_gart_fini(rdev);
364 rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
365 rdev->gart.num_cpu_pages, GFP_KERNEL);
366 if (rdev->gart.pages_addr == NULL) {
367 radeon_gart_fini(rdev);
370 /* set GART entry to point to the dummy page by default */
371 for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
372 rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
378 * radeon_gart_fini - tear down the driver info for managing the gart
380 * @rdev: radeon_device pointer
382 * Tear down the gart driver info and free the dummy page (all asics).
384 void radeon_gart_fini(struct radeon_device *rdev)
386 if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
388 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
390 rdev->gart.ready = false;
391 kfree(rdev->gart.pages);
392 kfree(rdev->gart.pages_addr);
393 rdev->gart.pages = NULL;
394 rdev->gart.pages_addr = NULL;
396 radeon_dummy_page_fini(rdev);
401 * GPUVM is similar to the legacy gart on older asics, however
402 * rather than there being a single global gart table
403 * for the entire GPU, there are multiple VM page tables active
404 * at any given time. The VM page tables can contain a mix
405 * vram pages and system memory pages and system memory pages
406 * can be mapped as snooped (cached system pages) or unsnooped
407 * (uncached system pages).
408 * Each VM has an ID associated with it and there is a page table
409 * associated with each VMID. When execting a command buffer,
410 * the kernel tells the the ring what VMID to use for that command
411 * buffer. VMIDs are allocated dynamically as commands are submitted.
412 * The userspace drivers maintain their own address space and the kernel
413 * sets up their pages tables accordingly when they submit their
414 * command buffers and a VMID is assigned.
415 * Cayman/Trinity support up to 8 active VMs at any given time;
422 * TODO bind a default page at vm initialization for default address
426 * radeon_vm_manager_init - init the vm manager
428 * @rdev: radeon_device pointer
430 * Init the vm manager (cayman+).
431 * Returns 0 for success, error for failure.
433 int radeon_vm_manager_init(struct radeon_device *rdev)
435 struct radeon_vm *vm;
436 struct radeon_bo_va *bo_va;
439 if (!rdev->vm_manager.enabled) {
440 /* mark first vm as always in use, it's the system one */
441 /* allocate enough for 2 full VM pts */
442 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
443 rdev->vm_manager.max_pfn * 8 * 2,
444 RADEON_GEM_DOMAIN_VRAM);
446 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n",
447 (rdev->vm_manager.max_pfn * 8) >> 10);
451 r = radeon_asic_vm_init(rdev);
455 rdev->vm_manager.enabled = true;
457 r = radeon_sa_bo_manager_start(rdev, &rdev->vm_manager.sa_manager);
462 /* restore page table */
463 list_for_each_entry(vm, &rdev->vm_manager.lru_vm, list) {
467 list_for_each_entry(bo_va, &vm->va, vm_list) {
468 struct ttm_mem_reg *mem = NULL;
470 mem = &bo_va->bo->tbo.mem;
472 bo_va->valid = false;
473 r = radeon_vm_bo_update_pte(rdev, vm, bo_va->bo, mem);
475 DRM_ERROR("Failed to update pte for vm %d!\n", vm->id);
479 r = radeon_asic_vm_bind(rdev, vm, vm->id);
481 DRM_ERROR("Failed to bind vm %d!\n", vm->id);
487 /* global mutex must be lock */
489 * radeon_vm_unbind_locked - unbind a specific vm
491 * @rdev: radeon_device pointer
494 * Unbind the requested vm (cayman+).
495 * Wait for use of the VM to finish, then unbind the page table,
496 * and free the page table memory.
498 static void radeon_vm_unbind_locked(struct radeon_device *rdev,
499 struct radeon_vm *vm)
501 struct radeon_bo_va *bo_va;
507 /* wait for vm use to end */
510 r = radeon_fence_wait(vm->fence, false);
512 DRM_ERROR("error while waiting for fence: %d\n", r);
514 mutex_unlock(&rdev->vm_manager.lock);
515 r = radeon_gpu_reset(rdev);
516 mutex_lock(&rdev->vm_manager.lock);
522 radeon_fence_unref(&vm->fence);
523 radeon_fence_unref(&vm->last_flush);
526 rdev->vm_manager.use_bitmap &= ~(1 << vm->id);
527 list_del_init(&vm->list);
529 radeon_sa_bo_free(rdev, &vm->sa_bo, NULL);
532 list_for_each_entry(bo_va, &vm->va, vm_list) {
533 bo_va->valid = false;
538 * radeon_vm_manager_fini - tear down the vm manager
540 * @rdev: radeon_device pointer
542 * Tear down the VM manager (cayman+).
544 void radeon_vm_manager_fini(struct radeon_device *rdev)
546 struct radeon_vm *vm, *tmp;
548 if (!rdev->vm_manager.enabled)
551 mutex_lock(&rdev->vm_manager.lock);
552 /* unbind all active vm */
553 list_for_each_entry_safe(vm, tmp, &rdev->vm_manager.lru_vm, list) {
554 radeon_vm_unbind_locked(rdev, vm);
556 radeon_asic_vm_fini(rdev);
557 mutex_unlock(&rdev->vm_manager.lock);
559 radeon_sa_bo_manager_suspend(rdev, &rdev->vm_manager.sa_manager);
560 radeon_sa_bo_manager_fini(rdev, &rdev->vm_manager.sa_manager);
561 rdev->vm_manager.enabled = false;
564 /* global mutex must be locked */
566 * radeon_vm_unbind - locked version of unbind
568 * @rdev: radeon_device pointer
571 * Locked version that wraps radeon_vm_unbind_locked (cayman+).
573 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
575 mutex_lock(&vm->mutex);
576 radeon_vm_unbind_locked(rdev, vm);
577 mutex_unlock(&vm->mutex);
580 /* global and local mutex must be locked */
582 * radeon_vm_bind - bind a page table to a VMID
584 * @rdev: radeon_device pointer
587 * Bind the requested vm (cayman+).
588 * Suballocate memory for the page table, allocate a VMID
589 * and bind the page table to it, and finally start to populate
591 * Returns 0 for success, error for failure.
593 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm)
595 struct radeon_vm *vm_evict;
605 list_del_init(&vm->list);
606 list_add_tail(&vm->list, &rdev->vm_manager.lru_vm);
611 r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager, &vm->sa_bo,
612 RADEON_GPU_PAGE_ALIGN(vm->last_pfn * 8),
613 RADEON_GPU_PAGE_SIZE, false);
615 if (list_empty(&rdev->vm_manager.lru_vm)) {
618 vm_evict = list_first_entry(&rdev->vm_manager.lru_vm, struct radeon_vm, list);
619 radeon_vm_unbind(rdev, vm_evict);
622 vm->pt = radeon_sa_bo_cpu_addr(vm->sa_bo);
623 vm->pt_gpu_addr = radeon_sa_bo_gpu_addr(vm->sa_bo);
624 memset(vm->pt, 0, RADEON_GPU_PAGE_ALIGN(vm->last_pfn * 8));
627 /* search for free vm */
628 for (i = 0; i < rdev->vm_manager.nvm; i++) {
629 if (!(rdev->vm_manager.use_bitmap & (1 << i))) {
634 /* evict vm if necessary */
636 vm_evict = list_first_entry(&rdev->vm_manager.lru_vm, struct radeon_vm, list);
637 radeon_vm_unbind(rdev, vm_evict);
642 r = radeon_asic_vm_bind(rdev, vm, id);
643 radeon_fence_unref(&vm->last_flush);
645 radeon_sa_bo_free(rdev, &vm->sa_bo, NULL);
648 rdev->vm_manager.use_bitmap |= 1 << id;
650 list_add_tail(&vm->list, &rdev->vm_manager.lru_vm);
651 return radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo,
652 &rdev->ring_tmp_bo.bo->tbo.mem);
655 /* object have to be reserved */
657 * radeon_vm_bo_add - add a bo to a specific vm
659 * @rdev: radeon_device pointer
661 * @bo: radeon buffer object
662 * @offset: requested offset of the buffer in the VM address space
663 * @flags: attributes of pages (read/write/valid/etc.)
665 * Add @bo into the requested vm (cayman+).
666 * Add @bo to the list of bos associated with the vm and validate
667 * the offset requested within the vm address space.
668 * Returns 0 for success, error for failure.
670 int radeon_vm_bo_add(struct radeon_device *rdev,
671 struct radeon_vm *vm,
672 struct radeon_bo *bo,
676 struct radeon_bo_va *bo_va, *tmp;
677 struct list_head *head;
678 uint64_t size = radeon_bo_size(bo), last_offset = 0;
681 bo_va = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
687 bo_va->soffset = offset;
688 bo_va->eoffset = offset + size;
689 bo_va->flags = flags;
690 bo_va->valid = false;
691 INIT_LIST_HEAD(&bo_va->bo_list);
692 INIT_LIST_HEAD(&bo_va->vm_list);
693 /* make sure object fit at this offset */
694 if (bo_va->soffset >= bo_va->eoffset) {
699 last_pfn = bo_va->eoffset / RADEON_GPU_PAGE_SIZE;
700 if (last_pfn > rdev->vm_manager.max_pfn) {
702 dev_err(rdev->dev, "va above limit (0x%08X > 0x%08X)\n",
703 last_pfn, rdev->vm_manager.max_pfn);
707 mutex_lock(&vm->mutex);
708 if (last_pfn > vm->last_pfn) {
709 /* release mutex and lock in right order */
710 mutex_unlock(&vm->mutex);
711 mutex_lock(&rdev->vm_manager.lock);
712 mutex_lock(&vm->mutex);
713 /* and check again */
714 if (last_pfn > vm->last_pfn) {
715 /* grow va space 32M by 32M */
716 unsigned align = ((32 << 20) >> 12) - 1;
717 radeon_vm_unbind_locked(rdev, vm);
718 vm->last_pfn = (last_pfn + align) & ~align;
720 mutex_unlock(&rdev->vm_manager.lock);
724 list_for_each_entry(tmp, &vm->va, vm_list) {
725 if (bo_va->soffset >= last_offset && bo_va->eoffset < tmp->soffset) {
726 /* bo can be added before this one */
729 if (bo_va->soffset >= tmp->soffset && bo_va->soffset < tmp->eoffset) {
730 /* bo and tmp overlap, invalid offset */
731 dev_err(rdev->dev, "bo %p va 0x%08X conflict with (bo %p 0x%08X 0x%08X)\n",
732 bo, (unsigned)bo_va->soffset, tmp->bo,
733 (unsigned)tmp->soffset, (unsigned)tmp->eoffset);
735 mutex_unlock(&vm->mutex);
738 last_offset = tmp->eoffset;
739 head = &tmp->vm_list;
741 list_add(&bo_va->vm_list, head);
742 list_add_tail(&bo_va->bo_list, &bo->va);
743 mutex_unlock(&vm->mutex);
748 * radeon_vm_get_addr - get the physical address of the page
750 * @rdev: radeon_device pointer
754 * Look up the physical address of the page that the pte resolves
756 * Returns the physical address of the page.
758 static u64 radeon_vm_get_addr(struct radeon_device *rdev,
759 struct ttm_mem_reg *mem,
764 switch (mem->mem_type) {
766 addr = (mem->start << PAGE_SHIFT);
767 addr += pfn * RADEON_GPU_PAGE_SIZE;
768 addr += rdev->vm_manager.vram_base_offset;
771 /* offset inside page table */
772 addr = mem->start << PAGE_SHIFT;
773 addr += pfn * RADEON_GPU_PAGE_SIZE;
774 addr = addr >> PAGE_SHIFT;
775 /* page table offset */
776 addr = rdev->gart.pages_addr[addr];
777 /* in case cpu page size != gpu page size*/
778 addr += (pfn * RADEON_GPU_PAGE_SIZE) & (~PAGE_MASK);
786 /* object have to be reserved & global and local mutex must be locked */
788 * radeon_vm_bo_update_pte - map a bo into the vm page table
790 * @rdev: radeon_device pointer
792 * @bo: radeon buffer object
795 * Fill in the page table entries for @bo (cayman+).
796 * Returns 0 for success, -EINVAL for failure.
798 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
799 struct radeon_vm *vm,
800 struct radeon_bo *bo,
801 struct ttm_mem_reg *mem)
803 struct radeon_bo_va *bo_va;
804 unsigned ngpu_pages, i;
805 uint64_t addr = 0, pfn;
808 /* nothing to do if vm isn't bound */
812 bo_va = radeon_bo_va(bo, vm);
814 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
818 if (bo_va->valid && mem)
821 ngpu_pages = radeon_bo_ngpu_pages(bo);
822 bo_va->flags &= ~RADEON_VM_PAGE_VALID;
823 bo_va->flags &= ~RADEON_VM_PAGE_SYSTEM;
825 if (mem->mem_type != TTM_PL_SYSTEM) {
826 bo_va->flags |= RADEON_VM_PAGE_VALID;
829 if (mem->mem_type == TTM_PL_TT) {
830 bo_va->flags |= RADEON_VM_PAGE_SYSTEM;
833 pfn = bo_va->soffset / RADEON_GPU_PAGE_SIZE;
834 flags = radeon_asic_vm_page_flags(rdev, bo_va->vm, bo_va->flags);
835 for (i = 0, addr = 0; i < ngpu_pages; i++) {
836 if (mem && bo_va->valid) {
837 addr = radeon_vm_get_addr(rdev, mem, i);
839 radeon_asic_vm_set_page(rdev, bo_va->vm, i + pfn, addr, flags);
841 radeon_fence_unref(&vm->last_flush);
845 /* object have to be reserved */
847 * radeon_vm_bo_rmv - remove a bo to a specific vm
849 * @rdev: radeon_device pointer
851 * @bo: radeon buffer object
853 * Remove @bo from the requested vm (cayman+).
854 * Remove @bo from the list of bos associated with the vm and
855 * remove the ptes for @bo in the page table.
856 * Returns 0 for success.
858 int radeon_vm_bo_rmv(struct radeon_device *rdev,
859 struct radeon_vm *vm,
860 struct radeon_bo *bo)
862 struct radeon_bo_va *bo_va;
865 bo_va = radeon_bo_va(bo, vm);
869 /* wait for va use to end */
870 while (bo_va->fence) {
871 r = radeon_fence_wait(bo_va->fence, false);
873 DRM_ERROR("error while waiting for fence: %d\n", r);
876 r = radeon_gpu_reset(rdev);
882 radeon_fence_unref(&bo_va->fence);
884 mutex_lock(&rdev->vm_manager.lock);
885 mutex_lock(&vm->mutex);
886 radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
887 mutex_unlock(&rdev->vm_manager.lock);
888 list_del(&bo_va->vm_list);
889 mutex_unlock(&vm->mutex);
890 list_del(&bo_va->bo_list);
897 * radeon_vm_bo_invalidate - mark the bo as invalid
899 * @rdev: radeon_device pointer
901 * @bo: radeon buffer object
903 * Mark @bo as invalid (cayman+).
905 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
906 struct radeon_bo *bo)
908 struct radeon_bo_va *bo_va;
910 BUG_ON(!atomic_read(&bo->tbo.reserved));
911 list_for_each_entry(bo_va, &bo->va, bo_list) {
912 bo_va->valid = false;
917 * radeon_vm_init - initialize a vm instance
919 * @rdev: radeon_device pointer
922 * Init @vm (cayman+).
923 * Map the IB pool and any other shared objects into the VM
924 * by default as it's used by all VMs.
925 * Returns 0 for success, error for failure.
927 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
933 mutex_init(&vm->mutex);
934 INIT_LIST_HEAD(&vm->list);
935 INIT_LIST_HEAD(&vm->va);
936 /* SI requires equal sized PTs for all VMs, so always set
937 * last_pfn to max_pfn. cayman allows variable sized
938 * pts so we can grow then as needed. Once we switch
939 * to two level pts we can unify this again.
941 if (rdev->family >= CHIP_TAHITI)
942 vm->last_pfn = rdev->vm_manager.max_pfn;
945 /* map the ib pool buffer at 0 in virtual address space, set
948 r = radeon_vm_bo_add(rdev, vm, rdev->ring_tmp_bo.bo, 0,
949 RADEON_VM_PAGE_READABLE | RADEON_VM_PAGE_SNOOPED);
954 * radeon_vm_fini - tear down a vm instance
956 * @rdev: radeon_device pointer
959 * Tear down @vm (cayman+).
960 * Unbind the VM and remove all bos from the vm bo list
962 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
964 struct radeon_bo_va *bo_va, *tmp;
967 mutex_lock(&rdev->vm_manager.lock);
968 mutex_lock(&vm->mutex);
969 radeon_vm_unbind_locked(rdev, vm);
970 mutex_unlock(&rdev->vm_manager.lock);
972 /* remove all bo at this point non are busy any more because unbind
973 * waited for the last vm fence to signal
975 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
977 bo_va = radeon_bo_va(rdev->ring_tmp_bo.bo, vm);
978 list_del_init(&bo_va->bo_list);
979 list_del_init(&bo_va->vm_list);
980 radeon_fence_unref(&bo_va->fence);
981 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
984 if (!list_empty(&vm->va)) {
985 dev_err(rdev->dev, "still active bo inside vm\n");
987 list_for_each_entry_safe(bo_va, tmp, &vm->va, vm_list) {
988 list_del_init(&bo_va->vm_list);
989 r = radeon_bo_reserve(bo_va->bo, false);
991 list_del_init(&bo_va->bo_list);
992 radeon_fence_unref(&bo_va->fence);
993 radeon_bo_unreserve(bo_va->bo);
997 mutex_unlock(&vm->mutex);