2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/list.h>
35 #include <linux/kref.h>
36 #include <linux/slab.h>
39 #include "radeon_reg.h"
41 #include "radeon_trace.h"
43 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
45 if (rdev->wb.enabled) {
46 *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
48 WREG32(rdev->fence_drv[ring].scratch_reg, seq);
52 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
56 if (rdev->wb.enabled) {
57 seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
59 seq = RREG32(rdev->fence_drv[ring].scratch_reg);
64 int radeon_fence_emit(struct radeon_device *rdev,
65 struct radeon_fence **fence,
68 /* we are protected by the ring emission mutex */
69 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
70 if ((*fence) == NULL) {
73 kref_init(&((*fence)->kref));
74 (*fence)->rdev = rdev;
75 (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
76 (*fence)->ring = ring;
77 radeon_fence_ring_emit(rdev, ring, *fence);
78 trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
82 void radeon_fence_process(struct radeon_device *rdev, int ring)
84 uint64_t seq, last_seq;
85 unsigned count_loop = 0;
88 /* Note there is a scenario here for an infinite loop but it's
89 * very unlikely to happen. For it to happen, the current polling
90 * process need to be interrupted by another process and another
91 * process needs to update the last_seq btw the atomic read and
92 * xchg of the current process.
94 * More over for this to go in infinite loop there need to be
95 * continuously new fence signaled ie radeon_fence_read needs
96 * to return a different value each time for both the currently
97 * polling process and the other process that xchg the last_seq
98 * btw atomic read and xchg of the current process. And the
99 * value the other process set as last seq must be higher than
100 * the seq value we just read. Which means that current process
101 * need to be interrupted after radeon_fence_read and before
104 * To be even more safe we count the number of time we loop and
105 * we bail after 10 loop just accepting the fact that we might
106 * have temporarly set the last_seq not to the true real last
107 * seq but to an older one.
109 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
111 seq = radeon_fence_read(rdev, ring);
112 seq |= last_seq & 0xffffffff00000000LL;
113 if (seq < last_seq) {
114 seq += 0x100000000LL;
117 if (seq == last_seq) {
120 /* If we loop over we don't want to return without
121 * checking if a fence is signaled as it means that the
122 * seq we just read is different from the previous on.
126 if ((count_loop++) > 10) {
127 /* We looped over too many time leave with the
128 * fact that we might have set an older fence
129 * seq then the current real last seq as signaled
134 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
137 rdev->fence_drv[ring].last_activity = jiffies;
138 wake_up_all(&rdev->fence_queue);
142 static void radeon_fence_destroy(struct kref *kref)
144 struct radeon_fence *fence;
146 fence = container_of(kref, struct radeon_fence, kref);
150 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
151 u64 seq, unsigned ring)
153 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
156 /* poll new last sequence at least once */
157 radeon_fence_process(rdev, ring);
158 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
164 bool radeon_fence_signaled(struct radeon_fence *fence)
169 if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
172 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
173 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
179 static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
180 unsigned ring, bool intr, bool lock_ring)
182 unsigned long timeout, last_activity;
188 while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
189 if (!rdev->ring[ring].ready) {
193 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
194 if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
195 /* the normal case, timeout is somewhere before last_activity */
196 timeout = rdev->fence_drv[ring].last_activity - timeout;
198 /* either jiffies wrapped around, or no fence was signaled in the last 500ms
199 * anyway we will just wait for the minimum amount and then check for a lockup
203 seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
204 /* Save current last activity valuee, used to check for GPU lockups */
205 last_activity = rdev->fence_drv[ring].last_activity;
207 trace_radeon_fence_wait_begin(rdev->ddev, seq);
208 radeon_irq_kms_sw_irq_get(rdev, ring);
210 r = wait_event_interruptible_timeout(rdev->fence_queue,
211 (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
214 r = wait_event_timeout(rdev->fence_queue,
215 (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
218 radeon_irq_kms_sw_irq_put(rdev, ring);
219 if (unlikely(r < 0)) {
222 trace_radeon_fence_wait_end(rdev->ddev, seq);
224 if (unlikely(!signaled)) {
225 /* we were interrupted for some reason and fence
226 * isn't signaled yet, resume waiting */
231 /* check if sequence value has changed since last_activity */
232 if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
237 mutex_lock(&rdev->ring_lock);
240 /* test if somebody else has already decided that this is a lockup */
241 if (last_activity != rdev->fence_drv[ring].last_activity) {
243 mutex_unlock(&rdev->ring_lock);
248 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
249 /* good news we believe it's a lockup */
250 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
253 /* change last activity so nobody else think there is a lockup */
254 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
255 rdev->fence_drv[i].last_activity = jiffies;
258 /* mark the ring as not ready any more */
259 rdev->ring[ring].ready = false;
261 mutex_unlock(&rdev->ring_lock);
267 mutex_unlock(&rdev->ring_lock);
274 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
279 WARN(1, "Querying an invalid fence : %p !\n", fence);
283 r = radeon_fence_wait_seq(fence->rdev, fence->seq,
284 fence->ring, intr, true);
288 fence->seq = RADEON_FENCE_SIGNALED_SEQ;
292 bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
296 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
297 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
304 static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
305 u64 *target_seq, bool intr)
307 unsigned long timeout, last_activity, tmp;
308 unsigned i, ring = RADEON_NUM_RINGS;
312 for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
313 if (!target_seq[i]) {
317 /* use the most recent one as indicator */
318 if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
319 last_activity = rdev->fence_drv[i].last_activity;
322 /* For lockup detection just pick the lowest ring we are
323 * actively waiting for
330 /* nothing to wait for ? */
331 if (ring == RADEON_NUM_RINGS) {
335 while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
336 timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
337 if (time_after(last_activity, timeout)) {
338 /* the normal case, timeout is somewhere before last_activity */
339 timeout = last_activity - timeout;
341 /* either jiffies wrapped around, or no fence was signaled in the last 500ms
342 * anyway we will just wait for the minimum amount and then check for a lockup
347 trace_radeon_fence_wait_begin(rdev->ddev, target_seq[ring]);
348 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
350 radeon_irq_kms_sw_irq_get(rdev, i);
354 r = wait_event_interruptible_timeout(rdev->fence_queue,
355 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
358 r = wait_event_timeout(rdev->fence_queue,
359 (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
362 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
364 radeon_irq_kms_sw_irq_put(rdev, i);
367 if (unlikely(r < 0)) {
370 trace_radeon_fence_wait_end(rdev->ddev, target_seq[ring]);
372 if (unlikely(!signaled)) {
373 /* we were interrupted for some reason and fence
374 * isn't signaled yet, resume waiting */
379 mutex_lock(&rdev->ring_lock);
380 for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
381 if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
382 tmp = rdev->fence_drv[i].last_activity;
385 /* test if somebody else has already decided that this is a lockup */
386 if (last_activity != tmp) {
388 mutex_unlock(&rdev->ring_lock);
392 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
393 /* good news we believe it's a lockup */
394 dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx)\n",
397 /* change last activity so nobody else think there is a lockup */
398 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
399 rdev->fence_drv[i].last_activity = jiffies;
402 /* mark the ring as not ready any more */
403 rdev->ring[ring].ready = false;
404 mutex_unlock(&rdev->ring_lock);
407 mutex_unlock(&rdev->ring_lock);
413 int radeon_fence_wait_any(struct radeon_device *rdev,
414 struct radeon_fence **fences,
417 uint64_t seq[RADEON_NUM_RINGS];
421 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
428 if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
429 /* something was allready signaled */
433 seq[i] = fences[i]->seq;
436 r = radeon_fence_wait_any_seq(rdev, seq, intr);
443 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
447 /* We are not protected by ring lock when reading current seq but
448 * it's ok as worst case is we return to early while we could have
451 seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
452 if (seq >= rdev->fence_drv[ring].sync_seq[ring]) {
453 /* nothing to wait for, last_seq is
454 already the last emited fence */
457 return radeon_fence_wait_seq(rdev, seq, ring, false, false);
460 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
462 /* We are not protected by ring lock when reading current seq
463 * but it's ok as wait empty is call from place where no more
464 * activity can be scheduled so there won't be concurrent access
467 return radeon_fence_wait_seq(rdev, rdev->fence_drv[ring].sync_seq[ring],
471 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
473 kref_get(&fence->kref);
477 void radeon_fence_unref(struct radeon_fence **fence)
479 struct radeon_fence *tmp = *fence;
483 kref_put(&tmp->kref, radeon_fence_destroy);
487 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
491 /* We are not protected by ring lock when reading the last sequence
492 * but it's ok to report slightly wrong fence count here.
494 radeon_fence_process(rdev, ring);
495 emitted = rdev->fence_drv[ring].sync_seq[ring]
496 - atomic64_read(&rdev->fence_drv[ring].last_seq);
497 /* to avoid 32bits warp around */
498 if (emitted > 0x10000000) {
499 emitted = 0x10000000;
501 return (unsigned)emitted;
504 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
506 struct radeon_fence_driver *fdrv;
512 if (fence->ring == dst_ring) {
516 /* we are protected by the ring mutex */
517 fdrv = &fence->rdev->fence_drv[dst_ring];
518 if (fence->seq <= fdrv->sync_seq[fence->ring]) {
525 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
527 struct radeon_fence_driver *dst, *src;
534 if (fence->ring == dst_ring) {
538 /* we are protected by the ring mutex */
539 src = &fence->rdev->fence_drv[fence->ring];
540 dst = &fence->rdev->fence_drv[dst_ring];
541 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
545 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
549 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
554 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
555 if (rdev->wb.use_event) {
556 rdev->fence_drv[ring].scratch_reg = 0;
557 index = R600_WB_EVENT_OFFSET + ring * 4;
559 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
561 dev_err(rdev->dev, "fence failed to get scratch register\n");
564 index = RADEON_WB_SCRATCH_OFFSET +
565 rdev->fence_drv[ring].scratch_reg -
566 rdev->scratch.reg_base;
568 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
569 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
570 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
571 rdev->fence_drv[ring].initialized = true;
572 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
573 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
577 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
581 rdev->fence_drv[ring].scratch_reg = -1;
582 rdev->fence_drv[ring].cpu_addr = NULL;
583 rdev->fence_drv[ring].gpu_addr = 0;
584 for (i = 0; i < RADEON_NUM_RINGS; ++i)
585 rdev->fence_drv[ring].sync_seq[i] = 0;
586 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
587 rdev->fence_drv[ring].last_activity = jiffies;
588 rdev->fence_drv[ring].initialized = false;
591 int radeon_fence_driver_init(struct radeon_device *rdev)
595 init_waitqueue_head(&rdev->fence_queue);
596 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
597 radeon_fence_driver_init_ring(rdev, ring);
599 if (radeon_debugfs_fence_init(rdev)) {
600 dev_err(rdev->dev, "fence debugfs file creation failed\n");
605 void radeon_fence_driver_fini(struct radeon_device *rdev)
609 mutex_lock(&rdev->ring_lock);
610 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
611 if (!rdev->fence_drv[ring].initialized)
613 radeon_fence_wait_empty_locked(rdev, ring);
614 wake_up_all(&rdev->fence_queue);
615 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
616 rdev->fence_drv[ring].initialized = false;
618 mutex_unlock(&rdev->ring_lock);
625 #if defined(CONFIG_DEBUG_FS)
626 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
628 struct drm_info_node *node = (struct drm_info_node *)m->private;
629 struct drm_device *dev = node->minor->dev;
630 struct radeon_device *rdev = dev->dev_private;
633 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
634 if (!rdev->fence_drv[i].initialized)
637 seq_printf(m, "--- ring %d ---\n", i);
638 seq_printf(m, "Last signaled fence 0x%016llx\n",
639 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
640 seq_printf(m, "Last emitted 0x%016llx\n",
641 rdev->fence_drv[i].sync_seq[i]);
643 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
644 if (i != j && rdev->fence_drv[j].initialized)
645 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
646 j, rdev->fence_drv[i].sync_seq[j]);
652 static struct drm_info_list radeon_debugfs_fence_list[] = {
653 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
657 int radeon_debugfs_fence_init(struct radeon_device *rdev)
659 #if defined(CONFIG_DEBUG_FS)
660 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);