2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
62 if (clone_encoder == encoder)
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
69 index_mask |= (1 << count);
74 void radeon_setup_encoder_clones(struct drm_device *dev)
76 struct drm_encoder *encoder;
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
86 struct radeon_device *rdev = dev->dev_private;
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
104 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
113 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
120 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
128 ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
138 ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
149 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
160 radeon_link_encoder_connector(struct drm_device *dev)
162 struct drm_connector *connector;
163 struct radeon_connector *radeon_connector;
164 struct drm_encoder *encoder;
165 struct radeon_encoder *radeon_encoder;
167 /* walk the list and link encoders to connectors */
168 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
169 radeon_connector = to_radeon_connector(connector);
170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
171 radeon_encoder = to_radeon_encoder(encoder);
172 if (radeon_encoder->devices & radeon_connector->devices)
173 drm_mode_connector_attach_encoder(connector, encoder);
178 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
180 struct drm_device *dev = encoder->dev;
181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
182 struct drm_connector *connector;
184 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
185 if (connector->encoder == encoder) {
186 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
187 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
188 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
189 radeon_encoder->active_device, radeon_encoder->devices,
190 radeon_connector->devices, encoder->encoder_type);
195 static struct drm_connector *
196 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
198 struct drm_device *dev = encoder->dev;
199 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
200 struct drm_connector *connector;
201 struct radeon_connector *radeon_connector;
203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
204 radeon_connector = to_radeon_connector(connector);
205 if (radeon_encoder->devices & radeon_connector->devices)
211 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
212 struct drm_display_mode *mode,
213 struct drm_display_mode *adjusted_mode)
215 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
216 struct drm_device *dev = encoder->dev;
217 struct radeon_device *rdev = dev->dev_private;
219 /* set the active encoder to connector routing */
220 radeon_encoder_set_active_device(encoder);
221 drm_mode_set_crtcinfo(adjusted_mode, 0);
224 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
225 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
226 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
228 /* get the native mode for LVDS */
229 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
230 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
231 int mode_id = adjusted_mode->base.id;
232 *adjusted_mode = *native_mode;
233 if (!ASIC_IS_AVIVO(rdev)) {
234 adjusted_mode->hdisplay = mode->hdisplay;
235 adjusted_mode->vdisplay = mode->vdisplay;
237 adjusted_mode->base.id = mode_id;
240 /* get the native mode for TV */
241 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
242 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
244 if (tv_dac->tv_std == TV_STD_NTSC ||
245 tv_dac->tv_std == TV_STD_NTSC_J ||
246 tv_dac->tv_std == TV_STD_PAL_M)
247 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
249 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
253 if (ASIC_IS_DCE3(rdev) &&
254 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
255 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
256 radeon_dp_set_link_config(connector, mode);
263 atombios_dac_setup(struct drm_encoder *encoder, int action)
265 struct drm_device *dev = encoder->dev;
266 struct radeon_device *rdev = dev->dev_private;
267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
268 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
269 int index = 0, num = 0;
270 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
271 enum radeon_tv_std tv_std = TV_STD_NTSC;
273 if (dac_info->tv_std)
274 tv_std = dac_info->tv_std;
276 memset(&args, 0, sizeof(args));
278 switch (radeon_encoder->encoder_id) {
279 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
281 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
284 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
286 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
291 args.ucAction = action;
293 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
294 args.ucDacStandard = ATOM_DAC1_PS2;
295 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
296 args.ucDacStandard = ATOM_DAC1_CV;
301 case TV_STD_SCART_PAL:
304 args.ucDacStandard = ATOM_DAC1_PAL;
310 args.ucDacStandard = ATOM_DAC1_NTSC;
314 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
321 atombios_tv_setup(struct drm_encoder *encoder, int action)
323 struct drm_device *dev = encoder->dev;
324 struct radeon_device *rdev = dev->dev_private;
325 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
326 TV_ENCODER_CONTROL_PS_ALLOCATION args;
328 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
329 enum radeon_tv_std tv_std = TV_STD_NTSC;
331 if (dac_info->tv_std)
332 tv_std = dac_info->tv_std;
334 memset(&args, 0, sizeof(args));
336 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
338 args.sTVEncoder.ucAction = action;
340 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
341 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
345 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
348 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
351 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
354 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
357 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
359 case TV_STD_SCART_PAL:
360 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
363 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
366 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
369 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
374 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
376 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
381 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
383 struct drm_device *dev = encoder->dev;
384 struct radeon_device *rdev = dev->dev_private;
385 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
386 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
389 memset(&args, 0, sizeof(args));
391 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
393 args.sXTmdsEncoder.ucEnable = action;
395 if (radeon_encoder->pixel_clock > 165000)
396 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
398 /*if (pScrn->rgbBits == 8)*/
399 args.sXTmdsEncoder.ucMisc |= (1 << 1);
401 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406 atombios_ddia_setup(struct drm_encoder *encoder, int action)
408 struct drm_device *dev = encoder->dev;
409 struct radeon_device *rdev = dev->dev_private;
410 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
411 DVO_ENCODER_CONTROL_PS_ALLOCATION args;
414 memset(&args, 0, sizeof(args));
416 index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
418 args.sDVOEncoder.ucAction = action;
419 args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
421 if (radeon_encoder->pixel_clock > 165000)
422 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
424 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428 union lvds_encoder_control {
429 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
430 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
434 atombios_digital_setup(struct drm_encoder *encoder, int action)
436 struct drm_device *dev = encoder->dev;
437 struct radeon_device *rdev = dev->dev_private;
438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
439 union lvds_encoder_control args;
441 int hdmi_detected = 0;
443 struct radeon_encoder_atom_dig *dig;
444 struct drm_connector *connector;
445 struct radeon_connector *radeon_connector;
446 struct radeon_connector_atom_dig *dig_connector;
448 connector = radeon_get_connector_for_encoder(encoder);
452 radeon_connector = to_radeon_connector(connector);
454 if (!radeon_encoder->enc_priv)
457 dig = radeon_encoder->enc_priv;
459 if (!radeon_connector->con_priv)
462 if (drm_detect_hdmi_monitor(radeon_connector->edid))
465 dig_connector = radeon_connector->con_priv;
467 memset(&args, 0, sizeof(args));
469 switch (radeon_encoder->encoder_id) {
470 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
471 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
473 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
474 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
475 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
477 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
478 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
479 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
481 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
485 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
493 args.v1.ucAction = action;
495 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
496 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
498 if (dig->lvds_misc & (1 << 0))
499 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
500 if (dig->lvds_misc & (1 << 1))
501 args.v1.ucMisc |= (1 << 1);
503 if (dig_connector->linkb)
504 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
505 if (radeon_encoder->pixel_clock > 165000)
506 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
507 /*if (pScrn->rgbBits == 8) */
508 args.v1.ucMisc |= (1 << 1);
514 args.v2.ucAction = action;
516 if (dig->coherent_mode)
517 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
520 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
521 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
522 args.v2.ucTruncate = 0;
523 args.v2.ucSpatial = 0;
524 args.v2.ucTemporal = 0;
526 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
527 if (dig->lvds_misc & (1 << 0))
528 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
529 if (dig->lvds_misc & (1 << 5)) {
530 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
531 if (dig->lvds_misc & (1 << 1))
532 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
534 if (dig->lvds_misc & (1 << 6)) {
535 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
536 if (dig->lvds_misc & (1 << 1))
537 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
538 if (((dig->lvds_misc >> 2) & 0x3) == 2)
539 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
542 if (dig_connector->linkb)
543 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
544 if (radeon_encoder->pixel_clock > 165000)
545 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
549 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
554 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
559 r600_hdmi_enable(encoder, hdmi_detected);
563 atombios_get_encoder_mode(struct drm_encoder *encoder)
565 struct drm_connector *connector;
566 struct radeon_connector *radeon_connector;
567 struct radeon_connector_atom_dig *radeon_dig_connector;
569 connector = radeon_get_connector_for_encoder(encoder);
573 radeon_connector = to_radeon_connector(connector);
575 switch (connector->connector_type) {
576 case DRM_MODE_CONNECTOR_DVII:
577 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
578 if (drm_detect_hdmi_monitor(radeon_connector->edid))
579 return ATOM_ENCODER_MODE_HDMI;
580 else if (radeon_connector->use_digital)
581 return ATOM_ENCODER_MODE_DVI;
583 return ATOM_ENCODER_MODE_CRT;
585 case DRM_MODE_CONNECTOR_DVID:
586 case DRM_MODE_CONNECTOR_HDMIA:
588 if (drm_detect_hdmi_monitor(radeon_connector->edid))
589 return ATOM_ENCODER_MODE_HDMI;
591 return ATOM_ENCODER_MODE_DVI;
593 case DRM_MODE_CONNECTOR_LVDS:
594 return ATOM_ENCODER_MODE_LVDS;
596 case DRM_MODE_CONNECTOR_DisplayPort:
597 radeon_dig_connector = radeon_connector->con_priv;
598 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
599 return ATOM_ENCODER_MODE_DP;
600 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
601 return ATOM_ENCODER_MODE_HDMI;
603 return ATOM_ENCODER_MODE_DVI;
605 case CONNECTOR_DVI_A:
607 return ATOM_ENCODER_MODE_CRT;
613 return ATOM_ENCODER_MODE_TV;
614 /*return ATOM_ENCODER_MODE_CV;*/
620 * DIG Encoder/Transmitter Setup
623 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
624 * Supports up to 3 digital outputs
625 * - 2 DIG encoder blocks.
626 * DIG1 can drive UNIPHY link A or link B
627 * DIG2 can drive UNIPHY link B or LVTMA
630 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
631 * Supports up to 5 digital outputs
632 * - 2 DIG encoder blocks.
633 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
636 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
638 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
639 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
640 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
641 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
644 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
646 struct drm_device *dev = encoder->dev;
647 struct radeon_device *rdev = dev->dev_private;
648 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
649 DIG_ENCODER_CONTROL_PS_ALLOCATION args;
650 int index = 0, num = 0;
652 struct radeon_encoder_atom_dig *dig;
653 struct drm_connector *connector;
654 struct radeon_connector *radeon_connector;
655 struct radeon_connector_atom_dig *dig_connector;
657 connector = radeon_get_connector_for_encoder(encoder);
661 radeon_connector = to_radeon_connector(connector);
663 if (!radeon_connector->con_priv)
666 dig_connector = radeon_connector->con_priv;
668 if (!radeon_encoder->enc_priv)
671 dig = radeon_encoder->enc_priv;
673 memset(&args, 0, sizeof(args));
675 if (ASIC_IS_DCE32(rdev)) {
677 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
679 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
680 num = dig->dig_block + 1;
682 switch (radeon_encoder->encoder_id) {
683 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
684 /* XXX doesn't really matter which dig encoder we pick as long as it's
687 if (dig_connector->linkb)
688 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
690 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
693 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
694 /* Only dig2 encoder can drive LVTMA */
695 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
701 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
703 args.ucAction = action;
704 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
706 if (ASIC_IS_DCE32(rdev)) {
707 switch (radeon_encoder->encoder_id) {
708 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
709 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
711 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
712 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
714 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
715 args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
719 switch (radeon_encoder->encoder_id) {
720 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
721 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
723 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
724 args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
729 args.ucEncoderMode = atombios_get_encoder_mode(encoder);
731 if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
732 if (dig_connector->dp_clock == 270000)
733 args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
734 args.ucLaneNum = dig_connector->dp_lane_count;
735 } else if (radeon_encoder->pixel_clock > 165000)
740 if (dig_connector->linkb)
741 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
743 args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
745 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
749 union dig_transmitter_control {
750 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
751 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
755 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
757 struct drm_device *dev = encoder->dev;
758 struct radeon_device *rdev = dev->dev_private;
759 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
760 union dig_transmitter_control args;
761 int index = 0, num = 0;
763 struct radeon_encoder_atom_dig *dig;
764 struct drm_connector *connector;
765 struct radeon_connector *radeon_connector;
766 struct radeon_connector_atom_dig *dig_connector;
769 connector = radeon_get_connector_for_encoder(encoder);
773 radeon_connector = to_radeon_connector(connector);
775 if (!radeon_encoder->enc_priv)
778 dig = radeon_encoder->enc_priv;
780 if (!radeon_connector->con_priv)
783 dig_connector = radeon_connector->con_priv;
785 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
788 memset(&args, 0, sizeof(args));
790 if (ASIC_IS_DCE32(rdev))
791 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
793 switch (radeon_encoder->encoder_id) {
794 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
795 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
798 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
803 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
805 args.v1.ucAction = action;
806 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
807 args.v1.usInitInfo = radeon_connector->connector_object_id;
808 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
809 args.v1.asMode.ucLaneSel = lane_num;
810 args.v1.asMode.ucLaneSet = lane_set;
813 args.v1.usPixelClock =
814 cpu_to_le16(dig_connector->dp_clock / 10);
815 else if (radeon_encoder->pixel_clock > 165000)
816 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
818 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
820 if (ASIC_IS_DCE32(rdev)) {
822 args.v2.acConfig.ucEncoderSel = 1;
823 if (dig_connector->linkb)
824 args.v2.acConfig.ucLinkSel = 1;
826 switch (radeon_encoder->encoder_id) {
827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
828 args.v2.acConfig.ucTransmitterSel = 0;
831 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
832 args.v2.acConfig.ucTransmitterSel = 1;
835 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
836 args.v2.acConfig.ucTransmitterSel = 2;
842 args.v2.acConfig.fCoherentMode = 1;
843 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
844 if (dig->coherent_mode)
845 args.v2.acConfig.fCoherentMode = 1;
848 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
850 switch (radeon_encoder->encoder_id) {
851 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
852 /* XXX doesn't really matter which dig encoder we pick as long as it's
855 if (dig_connector->linkb)
856 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
859 if (rdev->flags & RADEON_IS_IGP) {
860 if (radeon_encoder->pixel_clock > 165000) {
861 if (dig_connector->igp_lane_info & 0x3)
862 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
863 else if (dig_connector->igp_lane_info & 0xc)
864 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
866 if (dig_connector->igp_lane_info & 0x1)
867 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
868 else if (dig_connector->igp_lane_info & 0x2)
869 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
870 else if (dig_connector->igp_lane_info & 0x4)
871 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
872 else if (dig_connector->igp_lane_info & 0x8)
873 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
877 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
878 /* Only dig2 encoder can drive LVTMA */
879 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
883 if (radeon_encoder->pixel_clock > 165000)
884 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
886 if (dig_connector->linkb)
887 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
889 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
892 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
893 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
894 if (dig->coherent_mode)
895 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
899 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
903 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
905 struct drm_device *dev = encoder->dev;
906 struct radeon_device *rdev = dev->dev_private;
907 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
908 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
909 ENABLE_YUV_PS_ALLOCATION args;
910 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
913 memset(&args, 0, sizeof(args));
915 if (rdev->family >= CHIP_R600)
916 reg = R600_BIOS_3_SCRATCH;
918 reg = RADEON_BIOS_3_SCRATCH;
920 /* XXX: fix up scratch reg handling */
922 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
923 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
924 (radeon_crtc->crtc_id << 18)));
925 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
926 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
931 args.ucEnable = ATOM_ENABLE;
932 args.ucCRTC = radeon_crtc->crtc_id;
934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
940 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
942 struct drm_device *dev = encoder->dev;
943 struct radeon_device *rdev = dev->dev_private;
944 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
945 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
949 memset(&args, 0, sizeof(args));
951 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
952 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
953 radeon_encoder->active_device);
954 switch (radeon_encoder->encoder_id) {
955 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
956 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
957 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
959 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
960 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
962 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
965 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
966 case ENCODER_OBJECT_ID_INTERNAL_DDI:
967 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
968 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
970 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
971 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
973 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
974 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
975 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
977 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
979 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
980 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
981 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
982 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
983 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
984 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
986 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
988 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
989 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
990 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
991 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
992 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
993 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
995 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1001 case DRM_MODE_DPMS_ON:
1002 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1004 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1005 dp_link_train(encoder, connector);
1008 case DRM_MODE_DPMS_STANDBY:
1009 case DRM_MODE_DPMS_SUSPEND:
1010 case DRM_MODE_DPMS_OFF:
1011 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1016 case DRM_MODE_DPMS_ON:
1017 args.ucAction = ATOM_ENABLE;
1019 case DRM_MODE_DPMS_STANDBY:
1020 case DRM_MODE_DPMS_SUSPEND:
1021 case DRM_MODE_DPMS_OFF:
1022 args.ucAction = ATOM_DISABLE;
1025 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1027 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1030 union crtc_sourc_param {
1031 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1032 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1036 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1038 struct drm_device *dev = encoder->dev;
1039 struct radeon_device *rdev = dev->dev_private;
1040 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1042 union crtc_sourc_param args;
1043 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1046 memset(&args, 0, sizeof(args));
1048 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1055 if (ASIC_IS_AVIVO(rdev))
1056 args.v1.ucCRTC = radeon_crtc->crtc_id;
1058 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1059 args.v1.ucCRTC = radeon_crtc->crtc_id;
1061 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1064 switch (radeon_encoder->encoder_id) {
1065 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1067 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1069 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1070 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1071 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1072 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1074 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1076 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1077 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1078 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1079 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1081 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1082 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1083 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1084 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1085 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1086 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1088 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1090 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1091 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1092 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1093 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1094 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1095 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1097 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1102 args.v2.ucCRTC = radeon_crtc->crtc_id;
1103 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1104 switch (radeon_encoder->encoder_id) {
1105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1108 if (ASIC_IS_DCE32(rdev)) {
1109 if (radeon_crtc->crtc_id)
1110 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1112 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1114 struct drm_connector *connector;
1115 struct radeon_connector *radeon_connector;
1116 struct radeon_connector_atom_dig *dig_connector;
1118 connector = radeon_get_connector_for_encoder(encoder);
1121 radeon_connector = to_radeon_connector(connector);
1122 if (!radeon_connector->con_priv)
1124 dig_connector = radeon_connector->con_priv;
1126 /* XXX doesn't really matter which dig encoder we pick as long as it's
1127 * not already in use
1129 if (dig_connector->linkb)
1130 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1132 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1136 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1139 /* Only dig2 encoder can drive LVTMA */
1140 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1143 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1144 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1145 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1146 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1148 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1150 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1151 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1152 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1153 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1154 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1156 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1163 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1167 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1171 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1172 struct drm_display_mode *mode)
1174 struct drm_device *dev = encoder->dev;
1175 struct radeon_device *rdev = dev->dev_private;
1176 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1179 /* Funky macbooks */
1180 if ((dev->pdev->device == 0x71C5) &&
1181 (dev->pdev->subsystem_vendor == 0x106b) &&
1182 (dev->pdev->subsystem_device == 0x0080)) {
1183 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1184 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1186 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1187 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1189 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1193 /* set scaler clears this on some chips */
1194 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1195 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1196 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1197 AVIVO_D1MODE_INTERLEAVE_EN);
1202 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1203 struct drm_display_mode *mode,
1204 struct drm_display_mode *adjusted_mode)
1206 struct drm_device *dev = encoder->dev;
1207 struct radeon_device *rdev = dev->dev_private;
1208 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1209 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1211 if (radeon_encoder->active_device &
1212 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1213 if (radeon_encoder->enc_priv) {
1214 struct radeon_encoder_atom_dig *dig;
1216 dig = radeon_encoder->enc_priv;
1217 dig->dig_block = radeon_crtc->crtc_id;
1220 radeon_encoder->pixel_clock = adjusted_mode->clock;
1222 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1223 atombios_set_encoder_crtc_source(encoder);
1225 if (ASIC_IS_AVIVO(rdev)) {
1226 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1227 atombios_yuv_setup(encoder, true);
1229 atombios_yuv_setup(encoder, false);
1232 switch (radeon_encoder->encoder_id) {
1233 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1234 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1235 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1236 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1237 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1240 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1241 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1242 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1243 /* disable the encoder and transmitter */
1244 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1245 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1247 /* setup and enable the encoder and transmitter */
1248 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1249 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1250 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1251 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1253 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1254 atombios_ddia_setup(encoder, ATOM_ENABLE);
1256 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1257 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1258 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1260 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1261 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1262 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1263 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1264 atombios_dac_setup(encoder, ATOM_ENABLE);
1265 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1266 atombios_tv_setup(encoder, ATOM_ENABLE);
1269 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1271 r600_hdmi_setmode(encoder, adjusted_mode);
1275 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1277 struct drm_device *dev = encoder->dev;
1278 struct radeon_device *rdev = dev->dev_private;
1279 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1280 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1282 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1283 ATOM_DEVICE_CV_SUPPORT |
1284 ATOM_DEVICE_CRT_SUPPORT)) {
1285 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1286 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1289 memset(&args, 0, sizeof(args));
1291 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
1293 args.sDacload.ucMisc = 0;
1295 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1296 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1297 args.sDacload.ucDacType = ATOM_DAC_A;
1299 args.sDacload.ucDacType = ATOM_DAC_B;
1301 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1302 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1303 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1304 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1305 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1306 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1308 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1309 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1310 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1312 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1322 static enum drm_connector_status
1323 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1325 struct drm_device *dev = encoder->dev;
1326 struct radeon_device *rdev = dev->dev_private;
1327 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1328 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1329 uint32_t bios_0_scratch;
1331 if (!atombios_dac_load_detect(encoder, connector)) {
1332 DRM_DEBUG("detect returned false \n");
1333 return connector_status_unknown;
1336 if (rdev->family >= CHIP_R600)
1337 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1339 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1341 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1342 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1343 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1344 return connector_status_connected;
1346 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1347 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1348 return connector_status_connected;
1350 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1351 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1352 return connector_status_connected;
1354 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1355 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1356 return connector_status_connected; /* CTV */
1357 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1358 return connector_status_connected; /* STV */
1360 return connector_status_disconnected;
1363 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1365 radeon_atom_output_lock(encoder, true);
1366 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1369 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1371 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1372 radeon_atom_output_lock(encoder, false);
1375 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1378 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1379 radeon_encoder->active_device = 0;
1382 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1383 .dpms = radeon_atom_encoder_dpms,
1384 .mode_fixup = radeon_atom_mode_fixup,
1385 .prepare = radeon_atom_encoder_prepare,
1386 .mode_set = radeon_atom_encoder_mode_set,
1387 .commit = radeon_atom_encoder_commit,
1388 .disable = radeon_atom_encoder_disable,
1389 /* no detect for TMDS/LVDS yet */
1392 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1393 .dpms = radeon_atom_encoder_dpms,
1394 .mode_fixup = radeon_atom_mode_fixup,
1395 .prepare = radeon_atom_encoder_prepare,
1396 .mode_set = radeon_atom_encoder_mode_set,
1397 .commit = radeon_atom_encoder_commit,
1398 .detect = radeon_atom_dac_detect,
1401 void radeon_enc_destroy(struct drm_encoder *encoder)
1403 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1404 kfree(radeon_encoder->enc_priv);
1405 drm_encoder_cleanup(encoder);
1406 kfree(radeon_encoder);
1409 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1410 .destroy = radeon_enc_destroy,
1413 struct radeon_encoder_atom_dac *
1414 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1416 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1421 dac->tv_std = TV_STD_NTSC;
1425 struct radeon_encoder_atom_dig *
1426 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1428 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1433 /* coherent mode by default */
1434 dig->coherent_mode = true;
1440 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1442 struct radeon_device *rdev = dev->dev_private;
1443 struct drm_encoder *encoder;
1444 struct radeon_encoder *radeon_encoder;
1446 /* see if we already added it */
1447 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1448 radeon_encoder = to_radeon_encoder(encoder);
1449 if (radeon_encoder->encoder_id == encoder_id) {
1450 radeon_encoder->devices |= supported_device;
1457 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1458 if (!radeon_encoder)
1461 encoder = &radeon_encoder->base;
1462 if (rdev->flags & RADEON_SINGLE_CRTC)
1463 encoder->possible_crtcs = 0x1;
1465 encoder->possible_crtcs = 0x3;
1467 radeon_encoder->enc_priv = NULL;
1469 radeon_encoder->encoder_id = encoder_id;
1470 radeon_encoder->devices = supported_device;
1471 radeon_encoder->rmx_type = RMX_OFF;
1473 switch (radeon_encoder->encoder_id) {
1474 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1475 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1477 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1478 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1479 radeon_encoder->rmx_type = RMX_FULL;
1480 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1481 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1483 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1484 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1486 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1488 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1489 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1490 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1492 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1493 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1495 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1496 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1497 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1499 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1500 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1501 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1502 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1503 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1504 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1505 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1506 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1507 radeon_encoder->rmx_type = RMX_FULL;
1508 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1509 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1511 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1512 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1514 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1518 r600_hdmi_init(encoder);