3 #include <drm/drm_dp_mst_helper.h>
4 #include <drm/drm_fb_helper.h>
10 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
12 static int radeon_atom_set_enc_offset(int id)
14 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
15 EVERGREEN_CRTC1_REGISTER_OFFSET,
16 EVERGREEN_CRTC2_REGISTER_OFFSET,
17 EVERGREEN_CRTC3_REGISTER_OFFSET,
18 EVERGREEN_CRTC4_REGISTER_OFFSET,
19 EVERGREEN_CRTC5_REGISTER_OFFSET,
25 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
26 struct radeon_encoder_mst *mst_enc,
27 enum radeon_hpd_id hpd, bool enable)
29 struct drm_device *dev = primary->base.dev;
30 struct radeon_device *rdev = dev->dev_private;
35 reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
38 reg &= ~NI_DIG_FE_DIG_MODE(7);
39 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
42 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
44 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
46 reg |= NI_DIG_HPD_SELECT(hpd);
47 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
48 WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
51 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
54 temp = RREG32(NI_DIG_FE_CNTL + offset);
55 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
57 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
62 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
67 struct drm_device *dev = primary->base.dev;
68 struct radeon_device *rdev = dev->dev_private;
73 satreg = stream_number >> 1;
74 satidx = stream_number & 1;
76 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
78 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
80 val <<= (16 * satidx);
82 temp &= ~(0xffff << (16 * satidx));
86 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
87 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
89 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
92 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
93 } while ((temp & 0x1) && retries++ < 10000);
96 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
102 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
103 struct radeon_encoder *primary)
105 struct drm_device *dev = mst_conn->base.dev;
106 struct stream_attribs new_attribs[6];
109 struct radeon_connector *radeon_connector;
110 struct drm_connector *connector;
112 memset(new_attribs, 0, sizeof(new_attribs));
113 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
114 struct radeon_encoder *subenc;
115 struct radeon_encoder_mst *mst_enc;
117 radeon_connector = to_radeon_connector(connector);
118 if (!radeon_connector->is_mst_connector)
121 if (radeon_connector->mst_port != mst_conn)
124 subenc = radeon_connector->mst_encoder;
125 mst_enc = subenc->enc_priv;
127 if (!mst_enc->enc_active)
130 new_attribs[idx].fe = mst_enc->fe;
131 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
135 for (i = 0; i < idx; i++) {
136 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
137 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
138 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
139 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
140 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
144 for (i = idx; i < mst_conn->enabled_attribs; i++) {
145 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
146 mst_conn->cur_stream_attribs[i].fe = 0;
147 mst_conn->cur_stream_attribs[i].slots = 0;
149 mst_conn->enabled_attribs = idx;
153 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
155 struct drm_device *dev = mst->base.dev;
156 struct radeon_device *rdev = dev->dev_private;
157 struct radeon_encoder_mst *mst_enc = mst->enc_priv;
159 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
162 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
164 WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
167 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
168 } while ((temp & 0x1) && (retries++ < 10000));
170 if (retries >= 10000)
171 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
175 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
177 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
178 struct radeon_connector *master = radeon_connector->mst_port;
182 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
183 radeon_connector->edid = edid;
184 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
185 if (radeon_connector->edid) {
186 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
187 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
188 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
191 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
196 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
198 return radeon_dp_mst_get_ddc_modes(connector);
201 static enum drm_mode_status
202 radeon_dp_mst_mode_valid(struct drm_connector *connector,
203 struct drm_display_mode *mode)
205 /* TODO - validate mode against available PBN for link */
206 if (mode->clock < 10000)
207 return MODE_CLOCK_LOW;
209 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
210 return MODE_H_ILLEGAL;
215 struct drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
217 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
219 return &radeon_connector->mst_encoder->base;
222 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
223 .get_modes = radeon_dp_mst_get_modes,
224 .mode_valid = radeon_dp_mst_mode_valid,
225 .best_encoder = radeon_mst_best_encoder,
228 static enum drm_connector_status
229 radeon_dp_mst_detect(struct drm_connector *connector, bool force)
231 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
232 struct radeon_connector *master = radeon_connector->mst_port;
234 return drm_dp_mst_detect_port(connector, &master->mst_mgr, radeon_connector->port);
238 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
240 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
241 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
243 drm_encoder_cleanup(&radeon_encoder->base);
244 kfree(radeon_encoder);
245 drm_connector_cleanup(connector);
246 kfree(radeon_connector);
249 static int radeon_connector_dpms(struct drm_connector *connector, int mode)
255 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
256 .dpms = radeon_connector_dpms,
257 .detect = radeon_dp_mst_detect,
258 .fill_modes = drm_helper_probe_single_connector_modes,
259 .destroy = radeon_dp_mst_connector_destroy,
262 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
263 struct drm_dp_mst_port *port,
264 const char *pathprop)
266 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
267 struct drm_device *dev = master->base.dev;
268 struct radeon_connector *radeon_connector;
269 struct drm_connector *connector;
271 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
272 if (!radeon_connector)
275 radeon_connector->is_mst_connector = true;
276 connector = &radeon_connector->base;
277 radeon_connector->port = port;
278 radeon_connector->mst_port = master;
281 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
282 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
283 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
285 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
286 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
287 drm_mode_connector_set_path_property(connector, pathprop);
292 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
294 struct drm_device *dev = connector->dev;
295 struct radeon_device *rdev = dev->dev_private;
297 drm_modeset_lock_all(dev);
298 radeon_fb_add_connector(rdev, connector);
299 drm_modeset_unlock_all(dev);
301 drm_connector_register(connector);
304 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
305 struct drm_connector *connector)
307 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
308 struct drm_device *dev = master->base.dev;
309 struct radeon_device *rdev = dev->dev_private;
311 drm_connector_unregister(connector);
312 /* need to nuke the connector */
313 drm_modeset_lock_all(dev);
315 radeon_fb_remove_connector(rdev, connector);
317 drm_connector_cleanup(connector);
318 drm_modeset_unlock_all(dev);
324 static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
326 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
327 struct drm_device *dev = master->base.dev;
329 drm_kms_helper_hotplug_event(dev);
332 const struct drm_dp_mst_topology_cbs mst_cbs = {
333 .add_connector = radeon_dp_add_mst_connector,
334 .register_connector = radeon_dp_register_mst_connector,
335 .destroy_connector = radeon_dp_destroy_mst_connector,
336 .hotplug = radeon_dp_mst_hotplug,
339 struct radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
341 struct drm_device *dev = encoder->dev;
342 struct drm_connector *connector;
344 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
345 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
346 if (!connector->encoder)
348 if (!radeon_connector->is_mst_connector)
351 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
352 if (connector->encoder == encoder)
353 return radeon_connector;
358 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
364 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
365 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
367 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
369 if (radeon_connector) {
370 radeon_connector->pixelclock_for_modeset = mode->clock;
371 if (radeon_connector->base.display_info.bpc)
372 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
374 radeon_crtc->bpc = 8;
377 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
378 dp_clock = dig_connector->dp_clock;
379 radeon_crtc->ss_enabled =
380 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
381 ASIC_INTERNAL_SS_ON_DP,
386 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
388 struct drm_device *dev = encoder->dev;
389 struct radeon_device *rdev = dev->dev_private;
390 struct radeon_encoder *radeon_encoder, *primary;
391 struct radeon_encoder_mst *mst_enc;
392 struct radeon_encoder_atom_dig *dig_enc;
393 struct radeon_connector *radeon_connector;
394 struct drm_crtc *crtc;
395 struct radeon_crtc *radeon_crtc;
398 if (!ASIC_IS_DCE5(rdev)) {
399 DRM_ERROR("got mst dpms on non-DCE5\n");
403 radeon_connector = radeon_mst_find_connector(encoder);
404 if (!radeon_connector)
407 radeon_encoder = to_radeon_encoder(encoder);
409 mst_enc = radeon_encoder->enc_priv;
411 primary = mst_enc->primary;
413 dig_enc = primary->enc_priv;
415 crtc = encoder->crtc;
416 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
419 case DRM_MODE_DPMS_ON:
420 dig_enc->active_mst_links++;
422 radeon_crtc = to_radeon_crtc(crtc);
424 if (dig_enc->active_mst_links == 1) {
425 mst_enc->fe = dig_enc->dig_encoder;
426 mst_enc->fe_from_be = true;
427 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
429 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
430 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
431 0, 0, dig_enc->dig_encoder);
433 if (radeon_dp_needs_link_train(mst_enc->connector) ||
434 dig_enc->active_mst_links == 1) {
435 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
439 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
440 if (mst_enc->fe == -1)
441 DRM_ERROR("failed to get frontend for dig encoder\n");
442 mst_enc->fe_from_be = false;
443 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
446 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
447 dig_enc->linkb, radeon_crtc->crtc_id);
449 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
450 radeon_connector->port,
451 mst_enc->pbn, &slots);
452 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
454 radeon_dp_mst_set_be_cntl(primary, mst_enc,
455 radeon_connector->mst_port->hpd.hpd, true);
457 mst_enc->enc_active = true;
458 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
459 radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
461 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
463 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
465 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
468 case DRM_MODE_DPMS_STANDBY:
469 case DRM_MODE_DPMS_SUSPEND:
470 case DRM_MODE_DPMS_OFF:
471 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
473 if (!mst_enc->enc_active)
476 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
477 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
479 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
480 /* and this can also fail */
481 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
483 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
485 mst_enc->enc_active = false;
486 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
488 radeon_dp_mst_set_be_cntl(primary, mst_enc,
489 radeon_connector->mst_port->hpd.hpd, false);
490 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
493 if (!mst_enc->fe_from_be)
494 radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
496 mst_enc->fe_from_be = false;
497 dig_enc->active_mst_links--;
498 if (dig_enc->active_mst_links == 0) {
507 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
508 const struct drm_display_mode *mode,
509 struct drm_display_mode *adjusted_mode)
511 struct radeon_encoder_mst *mst_enc;
512 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
513 struct radeon_connector_atom_dig *dig_connector;
516 mst_enc = radeon_encoder->enc_priv;
518 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
520 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
521 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
522 mst_enc->primary->active_device, mst_enc->primary->devices,
523 mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
526 drm_mode_set_crtcinfo(adjusted_mode, 0);
527 dig_connector = mst_enc->connector->con_priv;
528 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
529 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
530 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
531 dig_connector->dp_lane_count, dig_connector->dp_clock);
535 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
537 struct radeon_connector *radeon_connector;
538 struct radeon_encoder *radeon_encoder, *primary;
539 struct radeon_encoder_mst *mst_enc;
540 struct radeon_encoder_atom_dig *dig_enc;
542 radeon_connector = radeon_mst_find_connector(encoder);
543 if (!radeon_connector) {
544 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
547 radeon_encoder = to_radeon_encoder(encoder);
549 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
551 mst_enc = radeon_encoder->enc_priv;
553 primary = mst_enc->primary;
555 dig_enc = primary->enc_priv;
557 mst_enc->port = radeon_connector->port;
559 if (dig_enc->dig_encoder == -1) {
560 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
561 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
562 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
566 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
570 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
571 struct drm_display_mode *mode,
572 struct drm_display_mode *adjusted_mode)
577 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
579 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
583 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
584 .dpms = radeon_mst_encoder_dpms,
585 .mode_fixup = radeon_mst_mode_fixup,
586 .prepare = radeon_mst_encoder_prepare,
587 .mode_set = radeon_mst_encoder_mode_set,
588 .commit = radeon_mst_encoder_commit,
591 void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
593 drm_encoder_cleanup(encoder);
597 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
598 .destroy = radeon_dp_mst_encoder_destroy,
601 static struct radeon_encoder *
602 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
604 struct drm_device *dev = connector->base.dev;
605 struct radeon_device *rdev = dev->dev_private;
606 struct radeon_encoder *radeon_encoder;
607 struct radeon_encoder_mst *mst_enc;
608 struct drm_encoder *encoder;
609 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
610 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
612 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
613 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
617 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
618 if (!radeon_encoder->enc_priv) {
619 kfree(radeon_encoder);
622 encoder = &radeon_encoder->base;
623 switch (rdev->num_crtc) {
625 encoder->possible_crtcs = 0x1;
629 encoder->possible_crtcs = 0x3;
632 encoder->possible_crtcs = 0xf;
635 encoder->possible_crtcs = 0x3f;
639 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
640 DRM_MODE_ENCODER_DPMST, NULL);
641 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
643 mst_enc = radeon_encoder->enc_priv;
644 mst_enc->connector = connector;
645 mst_enc->primary = to_radeon_encoder(enc_master);
646 radeon_encoder->is_mst_encoder = true;
647 return radeon_encoder;
651 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
653 struct drm_device *dev = radeon_connector->base.dev;
655 if (!radeon_connector->ddc_bus->has_aux)
658 radeon_connector->mst_mgr.cbs = &mst_cbs;
659 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev,
660 &radeon_connector->ddc_bus->aux, 16, 6,
661 radeon_connector->base.base.id);
665 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
667 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
668 struct drm_device *dev = radeon_connector->base.dev;
669 struct radeon_device *rdev = dev->dev_private;
676 if (!ASIC_IS_DCE5(rdev))
679 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
682 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
685 if (msg[0] & DP_MST_CAP) {
686 DRM_DEBUG_KMS("Sink is MST capable\n");
687 dig_connector->is_mst = true;
689 DRM_DEBUG_KMS("Sink is not MST capable\n");
690 dig_connector->is_mst = false;
694 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
695 dig_connector->is_mst);
696 return dig_connector->is_mst;
700 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
702 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
705 if (dig_connector->is_mst) {
711 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
712 DP_SINK_COUNT_ESI, esi, 8);
715 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
716 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
719 for (retry = 0; retry < 3; retry++) {
721 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
722 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
727 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
728 DP_SINK_COUNT_ESI, esi, 8);
730 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
738 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
739 dig_connector->is_mst = false;
740 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
741 dig_connector->is_mst);
742 /* send a hotplug event */
748 #if defined(CONFIG_DEBUG_FS)
750 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
752 struct drm_info_node *node = (struct drm_info_node *)m->private;
753 struct drm_device *dev = node->minor->dev;
754 struct drm_connector *connector;
755 struct radeon_connector *radeon_connector;
756 struct radeon_connector_atom_dig *dig_connector;
759 drm_modeset_lock_all(dev);
760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
761 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
764 radeon_connector = to_radeon_connector(connector);
765 dig_connector = radeon_connector->con_priv;
766 if (radeon_connector->is_mst_connector)
768 if (!dig_connector->is_mst)
770 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
772 for (i = 0; i < radeon_connector->enabled_attribs; i++)
773 seq_printf(m, "attrib %d: %d %d\n", i,
774 radeon_connector->cur_stream_attribs[i].fe,
775 radeon_connector->cur_stream_attribs[i].slots);
777 drm_modeset_unlock_all(dev);
781 static struct drm_info_list radeon_debugfs_mst_list[] = {
782 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
786 int radeon_mst_debugfs_init(struct radeon_device *rdev)
788 #if defined(CONFIG_DEBUG_FS)
789 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);