2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
38 #include <linux/gcd.h>
40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
63 for (i = 0; i < 256; i++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR,
65 (radeon_crtc->lut_r[i] << 20) |
66 (radeon_crtc->lut_g[i] << 10) |
67 (radeon_crtc->lut_b[i] << 0));
70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
77 struct drm_device *dev = crtc->dev;
78 struct radeon_device *rdev = dev->dev_private;
81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
96 for (i = 0; i < 256; i++) {
97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
98 (radeon_crtc->lut_r[i] << 20) |
99 (radeon_crtc->lut_g[i] << 10) |
100 (radeon_crtc->lut_b[i] << 0));
104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
107 struct drm_device *dev = crtc->dev;
108 struct radeon_device *rdev = dev->dev_private;
111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
114 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
115 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
117 NI_GRPH_PRESCALE_BYPASS);
118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
119 NI_OVL_PRESCALE_BYPASS);
120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
121 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
122 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
138 for (i = 0; i < 256; i++) {
139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
140 (radeon_crtc->lut_r[i] << 20) |
141 (radeon_crtc->lut_g[i] << 10) |
142 (radeon_crtc->lut_b[i] << 0));
145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
148 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
149 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
152 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
154 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
155 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
158 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
159 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
161 if (ASIC_IS_DCE8(rdev)) {
162 /* XXX this only needs to be programmed once per crtc at startup,
163 * not sure where the best place for it is
165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
166 CIK_CURSOR_ALPHA_BLND_ENA);
170 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
173 struct drm_device *dev = crtc->dev;
174 struct radeon_device *rdev = dev->dev_private;
178 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
179 if (radeon_crtc->crtc_id == 0)
180 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
182 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
183 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
185 WREG8(RADEON_PALETTE_INDEX, 0);
186 for (i = 0; i < 256; i++) {
187 WREG32(RADEON_PALETTE_30_DATA,
188 (radeon_crtc->lut_r[i] << 20) |
189 (radeon_crtc->lut_g[i] << 10) |
190 (radeon_crtc->lut_b[i] << 0));
194 void radeon_crtc_load_lut(struct drm_crtc *crtc)
196 struct drm_device *dev = crtc->dev;
197 struct radeon_device *rdev = dev->dev_private;
202 if (ASIC_IS_DCE5(rdev))
203 dce5_crtc_load_lut(crtc);
204 else if (ASIC_IS_DCE4(rdev))
205 dce4_crtc_load_lut(crtc);
206 else if (ASIC_IS_AVIVO(rdev))
207 avivo_crtc_load_lut(crtc);
209 legacy_crtc_load_lut(crtc);
212 /** Sets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
218 radeon_crtc->lut_r[regno] = red >> 6;
219 radeon_crtc->lut_g[regno] = green >> 6;
220 radeon_crtc->lut_b[regno] = blue >> 6;
223 /** Gets the color ramps on behalf of fbcon */
224 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
225 u16 *blue, int regno)
227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 *red = radeon_crtc->lut_r[regno] << 6;
230 *green = radeon_crtc->lut_g[regno] << 6;
231 *blue = radeon_crtc->lut_b[regno] << 6;
234 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
235 u16 *blue, uint32_t start, uint32_t size)
237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
238 int end = (start + size > 256) ? 256 : start + size, i;
240 /* userspace palettes are always correct as is */
241 for (i = start; i < end; i++) {
242 radeon_crtc->lut_r[i] = red[i] >> 6;
243 radeon_crtc->lut_g[i] = green[i] >> 6;
244 radeon_crtc->lut_b[i] = blue[i] >> 6;
246 radeon_crtc_load_lut(crtc);
249 static void radeon_crtc_destroy(struct drm_crtc *crtc)
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
253 drm_crtc_cleanup(crtc);
254 destroy_workqueue(radeon_crtc->flip_queue);
259 * radeon_unpin_work_func - unpin old buffer object
261 * @__work - kernel work item
263 * Unpin the old frame buffer object outside of the interrupt handler
265 static void radeon_unpin_work_func(struct work_struct *__work)
267 struct radeon_flip_work *work =
268 container_of(__work, struct radeon_flip_work, unpin_work);
271 /* unpin of the old buffer */
272 r = radeon_bo_reserve(work->old_rbo, false);
273 if (likely(r == 0)) {
274 r = radeon_bo_unpin(work->old_rbo);
275 if (unlikely(r != 0)) {
276 DRM_ERROR("failed to unpin buffer after flip\n");
278 radeon_bo_unreserve(work->old_rbo);
280 DRM_ERROR("failed to reserve buffer after flip\n");
282 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
286 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
288 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
293 /* can happen during initialization */
294 if (radeon_crtc == NULL)
297 /* Skip the pageflip completion check below (based on polling) on
298 * asics which reliably support hw pageflip completion irqs. pflip
299 * irqs are a reliable and race-free method of handling pageflip
300 * completion detection. A use_pflipirq module parameter < 2 allows
301 * to override this in case of asics with faulty pflip irqs.
302 * A module parameter of 0 would only use this polling based path,
303 * a parameter of 1 would use pflip irq only as a backup to this
304 * path, as in Linux 3.16.
306 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
309 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
310 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
311 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
312 "RADEON_FLIP_SUBMITTED(%d)\n",
313 radeon_crtc->flip_status,
314 RADEON_FLIP_SUBMITTED);
315 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
319 update_pending = radeon_page_flip_pending(rdev, crtc_id);
321 /* Has the pageflip already completed in crtc, or is it certain
322 * to complete in this vblank?
324 if (update_pending &&
325 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
326 &vpos, &hpos, NULL, NULL,
327 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
328 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
329 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
330 /* crtc didn't flip in this target vblank interval,
331 * but flip is pending in crtc. Based on the current
332 * scanout position we know that the current frame is
333 * (nearly) complete and the flip will (likely)
334 * complete before the start of the next frame.
338 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
340 radeon_crtc_handle_flip(rdev, crtc_id);
344 * radeon_crtc_handle_flip - page flip completed
346 * @rdev: radeon device pointer
347 * @crtc_id: crtc number this event is for
349 * Called when we are sure that a page flip for this crtc is completed.
351 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
353 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
354 struct radeon_flip_work *work;
357 /* this can happen at init */
358 if (radeon_crtc == NULL)
361 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
362 work = radeon_crtc->flip_work;
363 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
364 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
365 "RADEON_FLIP_SUBMITTED(%d)\n",
366 radeon_crtc->flip_status,
367 RADEON_FLIP_SUBMITTED);
368 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
372 /* Pageflip completed. Clean up. */
373 radeon_crtc->flip_status = RADEON_FLIP_NONE;
374 radeon_crtc->flip_work = NULL;
376 /* wakeup userspace */
378 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
380 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
382 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
383 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
384 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
388 * radeon_flip_work_func - page flip framebuffer
390 * @work - kernel work item
392 * Wait for the buffer object to become idle and do the actual page flip
394 static void radeon_flip_work_func(struct work_struct *__work)
396 struct radeon_flip_work *work =
397 container_of(__work, struct radeon_flip_work, flip_work);
398 struct radeon_device *rdev = work->rdev;
399 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
401 struct drm_crtc *crtc = &radeon_crtc->base;
405 down_read(&rdev->exclusive_lock);
407 struct radeon_fence *fence;
409 fence = to_radeon_fence(work->fence);
410 if (fence && fence->rdev == rdev) {
411 r = radeon_fence_wait(fence, false);
413 up_read(&rdev->exclusive_lock);
415 r = radeon_gpu_reset(rdev);
416 } while (r == -EAGAIN);
417 down_read(&rdev->exclusive_lock);
420 r = fence_wait(work->fence, false);
423 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
425 /* We continue with the page flip even if we failed to wait on
426 * the fence, otherwise the DRM core and userspace will be
427 * confused about which BO the CRTC is scanning out
430 fence_put(work->fence);
434 /* We borrow the event spin lock for protecting flip_status */
435 spin_lock_irqsave(&crtc->dev->event_lock, flags);
437 /* set the proper interrupt */
438 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
440 /* do the flip (mmio) */
441 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
443 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
444 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
445 up_read(&rdev->exclusive_lock);
448 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
449 struct drm_framebuffer *fb,
450 struct drm_pending_vblank_event *event,
451 uint32_t page_flip_flags)
453 struct drm_device *dev = crtc->dev;
454 struct radeon_device *rdev = dev->dev_private;
455 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
456 struct radeon_framebuffer *old_radeon_fb;
457 struct radeon_framebuffer *new_radeon_fb;
458 struct drm_gem_object *obj;
459 struct radeon_flip_work *work;
460 struct radeon_bo *new_rbo;
461 uint32_t tiling_flags, pitch_pixels;
466 work = kzalloc(sizeof *work, GFP_KERNEL);
470 INIT_WORK(&work->flip_work, radeon_flip_work_func);
471 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
474 work->crtc_id = radeon_crtc->crtc_id;
477 /* schedule unpin of the old buffer */
478 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
479 obj = old_radeon_fb->obj;
481 /* take a reference to the old object */
482 drm_gem_object_reference(obj);
483 work->old_rbo = gem_to_radeon_bo(obj);
485 new_radeon_fb = to_radeon_framebuffer(fb);
486 obj = new_radeon_fb->obj;
487 new_rbo = gem_to_radeon_bo(obj);
489 /* pin the new buffer */
490 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
491 work->old_rbo, new_rbo);
493 r = radeon_bo_reserve(new_rbo, false);
494 if (unlikely(r != 0)) {
495 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
498 /* Only 27 bit offset for legacy CRTC */
499 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
500 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
501 if (unlikely(r != 0)) {
502 radeon_bo_unreserve(new_rbo);
504 DRM_ERROR("failed to pin new rbo buffer before flip\n");
507 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
508 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
509 radeon_bo_unreserve(new_rbo);
511 if (!ASIC_IS_AVIVO(rdev)) {
512 /* crtc offset is from display base addr not FB location */
513 base -= radeon_crtc->legacy_display_base_addr;
514 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
516 if (tiling_flags & RADEON_TILING_MACRO) {
517 if (ASIC_IS_R300(rdev)) {
520 int byteshift = fb->bits_per_pixel >> 4;
521 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
522 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
525 int offset = crtc->y * pitch_pixels + crtc->x;
526 switch (fb->bits_per_pixel) {
548 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
550 DRM_ERROR("failed to get vblank before flip\n");
554 /* We borrow the event spin lock for protecting flip_work */
555 spin_lock_irqsave(&crtc->dev->event_lock, flags);
557 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
558 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
559 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
563 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
564 radeon_crtc->flip_work = work;
567 crtc->primary->fb = fb;
569 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
571 queue_work(radeon_crtc->flip_queue, &work->flip_work);
575 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
578 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
579 DRM_ERROR("failed to reserve new rbo in error path\n");
582 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
583 DRM_ERROR("failed to unpin new rbo in error path\n");
585 radeon_bo_unreserve(new_rbo);
588 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
589 fence_put(work->fence);
595 radeon_crtc_set_config(struct drm_mode_set *set)
597 struct drm_device *dev;
598 struct radeon_device *rdev;
599 struct drm_crtc *crtc;
603 if (!set || !set->crtc)
606 dev = set->crtc->dev;
608 ret = pm_runtime_get_sync(dev->dev);
612 ret = drm_crtc_helper_set_config(set);
614 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
618 pm_runtime_mark_last_busy(dev->dev);
620 rdev = dev->dev_private;
621 /* if we have active crtcs and we don't have a power ref,
622 take the current one */
623 if (active && !rdev->have_disp_power_ref) {
624 rdev->have_disp_power_ref = true;
627 /* if we have no active crtcs, then drop the power ref
629 if (!active && rdev->have_disp_power_ref) {
630 pm_runtime_put_autosuspend(dev->dev);
631 rdev->have_disp_power_ref = false;
634 /* drop the power reference we got coming in here */
635 pm_runtime_put_autosuspend(dev->dev);
638 static const struct drm_crtc_funcs radeon_crtc_funcs = {
639 .cursor_set2 = radeon_crtc_cursor_set2,
640 .cursor_move = radeon_crtc_cursor_move,
641 .gamma_set = radeon_crtc_gamma_set,
642 .set_config = radeon_crtc_set_config,
643 .destroy = radeon_crtc_destroy,
644 .page_flip = radeon_crtc_page_flip,
647 static void radeon_crtc_init(struct drm_device *dev, int index)
649 struct radeon_device *rdev = dev->dev_private;
650 struct radeon_crtc *radeon_crtc;
653 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
654 if (radeon_crtc == NULL)
657 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
659 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
660 radeon_crtc->crtc_id = index;
661 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
662 rdev->mode_info.crtcs[index] = radeon_crtc;
664 if (rdev->family >= CHIP_BONAIRE) {
665 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
666 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
668 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
669 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
671 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
672 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
675 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
676 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
677 radeon_crtc->mode_set.num_connectors = 0;
680 for (i = 0; i < 256; i++) {
681 radeon_crtc->lut_r[i] = i << 2;
682 radeon_crtc->lut_g[i] = i << 2;
683 radeon_crtc->lut_b[i] = i << 2;
686 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
687 radeon_atombios_init_crtc(dev, radeon_crtc);
689 radeon_legacy_init_crtc(dev, radeon_crtc);
692 static const char *encoder_names[38] = {
712 "INTERNAL_KLDSCP_TMDS1",
713 "INTERNAL_KLDSCP_DVO1",
714 "INTERNAL_KLDSCP_DAC1",
715 "INTERNAL_KLDSCP_DAC2",
724 "INTERNAL_KLDSCP_LVTMA",
733 static const char *hpd_names[6] = {
742 static void radeon_print_display_setup(struct drm_device *dev)
744 struct drm_connector *connector;
745 struct radeon_connector *radeon_connector;
746 struct drm_encoder *encoder;
747 struct radeon_encoder *radeon_encoder;
751 DRM_INFO("Radeon Display Connectors\n");
752 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
753 radeon_connector = to_radeon_connector(connector);
754 DRM_INFO("Connector %d:\n", i);
755 DRM_INFO(" %s\n", connector->name);
756 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
757 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
758 if (radeon_connector->ddc_bus) {
759 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
760 radeon_connector->ddc_bus->rec.mask_clk_reg,
761 radeon_connector->ddc_bus->rec.mask_data_reg,
762 radeon_connector->ddc_bus->rec.a_clk_reg,
763 radeon_connector->ddc_bus->rec.a_data_reg,
764 radeon_connector->ddc_bus->rec.en_clk_reg,
765 radeon_connector->ddc_bus->rec.en_data_reg,
766 radeon_connector->ddc_bus->rec.y_clk_reg,
767 radeon_connector->ddc_bus->rec.y_data_reg);
768 if (radeon_connector->router.ddc_valid)
769 DRM_INFO(" DDC Router 0x%x/0x%x\n",
770 radeon_connector->router.ddc_mux_control_pin,
771 radeon_connector->router.ddc_mux_state);
772 if (radeon_connector->router.cd_valid)
773 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
774 radeon_connector->router.cd_mux_control_pin,
775 radeon_connector->router.cd_mux_state);
777 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
778 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
779 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
780 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
781 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
782 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
783 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
785 DRM_INFO(" Encoders:\n");
786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
787 radeon_encoder = to_radeon_encoder(encoder);
788 devices = radeon_encoder->devices & radeon_connector->devices;
790 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
791 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
792 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
793 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
794 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
795 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
796 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
797 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
798 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
799 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
800 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
801 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
802 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
803 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
804 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
805 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
806 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
807 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
808 if (devices & ATOM_DEVICE_TV1_SUPPORT)
809 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
810 if (devices & ATOM_DEVICE_CV_SUPPORT)
811 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
818 static bool radeon_setup_enc_conn(struct drm_device *dev)
820 struct radeon_device *rdev = dev->dev_private;
824 if (rdev->is_atom_bios) {
825 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
827 ret = radeon_get_atom_connector_info_from_object_table(dev);
829 ret = radeon_get_legacy_connector_info_from_bios(dev);
831 ret = radeon_get_legacy_connector_info_from_table(dev);
834 if (!ASIC_IS_AVIVO(rdev))
835 ret = radeon_get_legacy_connector_info_from_table(dev);
838 radeon_setup_encoder_clones(dev);
839 radeon_print_display_setup(dev);
848 * avivo_reduce_ratio - fractional number reduction
852 * @nom_min: minimum value for nominator
853 * @den_min: minimum value for denominator
855 * Find the greatest common divisor and apply it on both nominator and
856 * denominator, but make nominator and denominator are at least as large
857 * as their minimum values.
859 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
860 unsigned nom_min, unsigned den_min)
864 /* reduce the numbers to a simpler ratio */
865 tmp = gcd(*nom, *den);
869 /* make sure nominator is large enough */
870 if (*nom < nom_min) {
871 tmp = DIV_ROUND_UP(nom_min, *nom);
876 /* make sure the denominator is large enough */
877 if (*den < den_min) {
878 tmp = DIV_ROUND_UP(den_min, *den);
885 * avivo_get_fb_ref_div - feedback and ref divider calculation
889 * @post_div: post divider
890 * @fb_div_max: feedback divider maximum
891 * @ref_div_max: reference divider maximum
892 * @fb_div: resulting feedback divider
893 * @ref_div: resulting reference divider
895 * Calculate feedback and reference divider for a given post divider. Makes
896 * sure we stay within the limits.
898 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
899 unsigned fb_div_max, unsigned ref_div_max,
900 unsigned *fb_div, unsigned *ref_div)
902 /* limit reference * post divider to a maximum */
903 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
905 /* get matching reference and feedback divider */
906 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
907 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
909 /* limit fb divider to its maximum */
910 if (*fb_div > fb_div_max) {
911 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
912 *fb_div = fb_div_max;
917 * radeon_compute_pll_avivo - compute PLL paramaters
919 * @pll: information about the PLL
920 * @dot_clock_p: resulting pixel clock
921 * fb_div_p: resulting feedback divider
922 * frac_fb_div_p: fractional part of the feedback divider
923 * ref_div_p: resulting reference divider
924 * post_div_p: resulting reference divider
926 * Try to calculate the PLL parameters to generate the given frequency:
927 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
929 void radeon_compute_pll_avivo(struct radeon_pll *pll,
937 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
940 unsigned fb_div_min, fb_div_max, fb_div;
941 unsigned post_div_min, post_div_max, post_div;
942 unsigned ref_div_min, ref_div_max, ref_div;
943 unsigned post_div_best, diff_best;
946 /* determine allowed feedback divider range */
947 fb_div_min = pll->min_feedback_div;
948 fb_div_max = pll->max_feedback_div;
950 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
955 /* determine allowed ref divider range */
956 if (pll->flags & RADEON_PLL_USE_REF_DIV)
957 ref_div_min = pll->reference_div;
959 ref_div_min = pll->min_ref_div;
961 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
962 pll->flags & RADEON_PLL_USE_REF_DIV)
963 ref_div_max = pll->reference_div;
964 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
965 /* fix for problems on RS880 */
966 ref_div_max = min(pll->max_ref_div, 7u);
968 ref_div_max = pll->max_ref_div;
970 /* determine allowed post divider range */
971 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
972 post_div_min = pll->post_div;
973 post_div_max = pll->post_div;
975 unsigned vco_min, vco_max;
977 if (pll->flags & RADEON_PLL_IS_LCD) {
978 vco_min = pll->lcd_pll_out_min;
979 vco_max = pll->lcd_pll_out_max;
981 vco_min = pll->pll_out_min;
982 vco_max = pll->pll_out_max;
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
990 post_div_min = vco_min / target_clock;
991 if ((target_clock * post_div_min) < vco_min)
993 if (post_div_min < pll->min_post_div)
994 post_div_min = pll->min_post_div;
996 post_div_max = vco_max / target_clock;
997 if ((target_clock * post_div_max) > vco_max)
999 if (post_div_max > pll->max_post_div)
1000 post_div_max = pll->max_post_div;
1003 /* represent the searched ratio as fractional number */
1005 den = pll->reference_freq;
1007 /* reduce the numbers to a simpler ratio */
1008 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1010 /* now search for a post divider */
1011 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1012 post_div_best = post_div_min;
1014 post_div_best = post_div_max;
1017 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1019 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1020 ref_div_max, &fb_div, &ref_div);
1021 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1022 (ref_div * post_div));
1024 if (diff < diff_best || (diff == diff_best &&
1025 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1027 post_div_best = post_div;
1031 post_div = post_div_best;
1033 /* get the feedback and reference divider for the optimal value */
1034 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1037 /* reduce the numbers to a simpler ratio once more */
1038 /* this also makes sure that the reference divider is large enough */
1039 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1041 /* avoid high jitter with small fractional dividers */
1042 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1043 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1044 if (fb_div < fb_div_min) {
1045 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1051 /* and finally save the result */
1052 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1053 *fb_div_p = fb_div / 10;
1054 *frac_fb_div_p = fb_div % 10;
1060 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1061 (pll->reference_freq * *frac_fb_div_p)) /
1062 (ref_div * post_div * 10);
1063 *ref_div_p = ref_div;
1064 *post_div_p = post_div;
1066 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1067 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1072 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1082 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1084 uint32_t *dot_clock_p,
1086 uint32_t *frac_fb_div_p,
1087 uint32_t *ref_div_p,
1088 uint32_t *post_div_p)
1090 uint32_t min_ref_div = pll->min_ref_div;
1091 uint32_t max_ref_div = pll->max_ref_div;
1092 uint32_t min_post_div = pll->min_post_div;
1093 uint32_t max_post_div = pll->max_post_div;
1094 uint32_t min_fractional_feed_div = 0;
1095 uint32_t max_fractional_feed_div = 0;
1096 uint32_t best_vco = pll->best_vco;
1097 uint32_t best_post_div = 1;
1098 uint32_t best_ref_div = 1;
1099 uint32_t best_feedback_div = 1;
1100 uint32_t best_frac_feedback_div = 0;
1101 uint32_t best_freq = -1;
1102 uint32_t best_error = 0xffffffff;
1103 uint32_t best_vco_diff = 1;
1105 u32 pll_out_min, pll_out_max;
1107 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1110 if (pll->flags & RADEON_PLL_IS_LCD) {
1111 pll_out_min = pll->lcd_pll_out_min;
1112 pll_out_max = pll->lcd_pll_out_max;
1114 pll_out_min = pll->pll_out_min;
1115 pll_out_max = pll->pll_out_max;
1118 if (pll_out_min > 64800)
1119 pll_out_min = 64800;
1121 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1122 min_ref_div = max_ref_div = pll->reference_div;
1124 while (min_ref_div < max_ref_div-1) {
1125 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1126 uint32_t pll_in = pll->reference_freq / mid;
1127 if (pll_in < pll->pll_in_min)
1129 else if (pll_in > pll->pll_in_max)
1136 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1137 min_post_div = max_post_div = pll->post_div;
1139 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1140 min_fractional_feed_div = pll->min_frac_feedback_div;
1141 max_fractional_feed_div = pll->max_frac_feedback_div;
1144 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1147 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1150 /* legacy radeons only have a few post_divs */
1151 if (pll->flags & RADEON_PLL_LEGACY) {
1152 if ((post_div == 5) ||
1163 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1164 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1165 uint32_t pll_in = pll->reference_freq / ref_div;
1166 uint32_t min_feed_div = pll->min_feedback_div;
1167 uint32_t max_feed_div = pll->max_feedback_div + 1;
1169 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1172 while (min_feed_div < max_feed_div) {
1174 uint32_t min_frac_feed_div = min_fractional_feed_div;
1175 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1176 uint32_t frac_feedback_div;
1179 feedback_div = (min_feed_div + max_feed_div) / 2;
1181 tmp = (uint64_t)pll->reference_freq * feedback_div;
1182 vco = radeon_div(tmp, ref_div);
1184 if (vco < pll_out_min) {
1185 min_feed_div = feedback_div + 1;
1187 } else if (vco > pll_out_max) {
1188 max_feed_div = feedback_div;
1192 while (min_frac_feed_div < max_frac_feed_div) {
1193 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1194 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1195 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1196 current_freq = radeon_div(tmp, ref_div * post_div);
1198 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1199 if (freq < current_freq)
1202 error = freq - current_freq;
1204 error = abs(current_freq - freq);
1205 vco_diff = abs(vco - best_vco);
1207 if ((best_vco == 0 && error < best_error) ||
1209 ((best_error > 100 && error < best_error - 100) ||
1210 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1211 best_post_div = post_div;
1212 best_ref_div = ref_div;
1213 best_feedback_div = feedback_div;
1214 best_frac_feedback_div = frac_feedback_div;
1215 best_freq = current_freq;
1217 best_vco_diff = vco_diff;
1218 } else if (current_freq == freq) {
1219 if (best_freq == -1) {
1220 best_post_div = post_div;
1221 best_ref_div = ref_div;
1222 best_feedback_div = feedback_div;
1223 best_frac_feedback_div = frac_feedback_div;
1224 best_freq = current_freq;
1226 best_vco_diff = vco_diff;
1227 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1228 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1229 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1230 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1231 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1232 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1233 best_post_div = post_div;
1234 best_ref_div = ref_div;
1235 best_feedback_div = feedback_div;
1236 best_frac_feedback_div = frac_feedback_div;
1237 best_freq = current_freq;
1239 best_vco_diff = vco_diff;
1242 if (current_freq < freq)
1243 min_frac_feed_div = frac_feedback_div + 1;
1245 max_frac_feed_div = frac_feedback_div;
1247 if (current_freq < freq)
1248 min_feed_div = feedback_div + 1;
1250 max_feed_div = feedback_div;
1255 *dot_clock_p = best_freq / 10000;
1256 *fb_div_p = best_feedback_div;
1257 *frac_fb_div_p = best_frac_feedback_div;
1258 *ref_div_p = best_ref_div;
1259 *post_div_p = best_post_div;
1260 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1262 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1263 best_ref_div, best_post_div);
1267 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1269 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1271 if (radeon_fb->obj) {
1272 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1274 drm_framebuffer_cleanup(fb);
1278 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1279 struct drm_file *file_priv,
1280 unsigned int *handle)
1282 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1284 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1287 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1288 .destroy = radeon_user_framebuffer_destroy,
1289 .create_handle = radeon_user_framebuffer_create_handle,
1293 radeon_framebuffer_init(struct drm_device *dev,
1294 struct radeon_framebuffer *rfb,
1295 struct drm_mode_fb_cmd2 *mode_cmd,
1296 struct drm_gem_object *obj)
1300 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1301 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1309 static struct drm_framebuffer *
1310 radeon_user_framebuffer_create(struct drm_device *dev,
1311 struct drm_file *file_priv,
1312 struct drm_mode_fb_cmd2 *mode_cmd)
1314 struct drm_gem_object *obj;
1315 struct radeon_framebuffer *radeon_fb;
1318 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1320 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1321 "can't create framebuffer\n", mode_cmd->handles[0]);
1322 return ERR_PTR(-ENOENT);
1325 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1326 if (radeon_fb == NULL) {
1327 drm_gem_object_unreference_unlocked(obj);
1328 return ERR_PTR(-ENOMEM);
1331 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1334 drm_gem_object_unreference_unlocked(obj);
1335 return ERR_PTR(ret);
1338 return &radeon_fb->base;
1341 static void radeon_output_poll_changed(struct drm_device *dev)
1343 struct radeon_device *rdev = dev->dev_private;
1344 radeon_fb_output_poll_changed(rdev);
1347 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1348 .fb_create = radeon_user_framebuffer_create,
1349 .output_poll_changed = radeon_output_poll_changed
1352 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1357 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1358 { { TV_STD_NTSC, "ntsc" },
1359 { TV_STD_PAL, "pal" },
1360 { TV_STD_PAL_M, "pal-m" },
1361 { TV_STD_PAL_60, "pal-60" },
1362 { TV_STD_NTSC_J, "ntsc-j" },
1363 { TV_STD_SCART_PAL, "scart-pal" },
1364 { TV_STD_PAL_CN, "pal-cn" },
1365 { TV_STD_SECAM, "secam" },
1368 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1369 { { UNDERSCAN_OFF, "off" },
1370 { UNDERSCAN_ON, "on" },
1371 { UNDERSCAN_AUTO, "auto" },
1374 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1375 { { RADEON_AUDIO_DISABLE, "off" },
1376 { RADEON_AUDIO_ENABLE, "on" },
1377 { RADEON_AUDIO_AUTO, "auto" },
1380 /* XXX support different dither options? spatial, temporal, both, etc. */
1381 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1382 { { RADEON_FMT_DITHER_DISABLE, "off" },
1383 { RADEON_FMT_DITHER_ENABLE, "on" },
1386 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1387 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1388 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1389 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1390 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1393 static int radeon_modeset_create_props(struct radeon_device *rdev)
1397 if (rdev->is_atom_bios) {
1398 rdev->mode_info.coherent_mode_property =
1399 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1400 if (!rdev->mode_info.coherent_mode_property)
1404 if (!ASIC_IS_AVIVO(rdev)) {
1405 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1406 rdev->mode_info.tmds_pll_property =
1407 drm_property_create_enum(rdev->ddev, 0,
1409 radeon_tmds_pll_enum_list, sz);
1412 rdev->mode_info.load_detect_property =
1413 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1414 if (!rdev->mode_info.load_detect_property)
1417 drm_mode_create_scaling_mode_property(rdev->ddev);
1419 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1420 rdev->mode_info.tv_std_property =
1421 drm_property_create_enum(rdev->ddev, 0,
1423 radeon_tv_std_enum_list, sz);
1425 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1426 rdev->mode_info.underscan_property =
1427 drm_property_create_enum(rdev->ddev, 0,
1429 radeon_underscan_enum_list, sz);
1431 rdev->mode_info.underscan_hborder_property =
1432 drm_property_create_range(rdev->ddev, 0,
1433 "underscan hborder", 0, 128);
1434 if (!rdev->mode_info.underscan_hborder_property)
1437 rdev->mode_info.underscan_vborder_property =
1438 drm_property_create_range(rdev->ddev, 0,
1439 "underscan vborder", 0, 128);
1440 if (!rdev->mode_info.underscan_vborder_property)
1443 sz = ARRAY_SIZE(radeon_audio_enum_list);
1444 rdev->mode_info.audio_property =
1445 drm_property_create_enum(rdev->ddev, 0,
1447 radeon_audio_enum_list, sz);
1449 sz = ARRAY_SIZE(radeon_dither_enum_list);
1450 rdev->mode_info.dither_property =
1451 drm_property_create_enum(rdev->ddev, 0,
1453 radeon_dither_enum_list, sz);
1455 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1456 rdev->mode_info.output_csc_property =
1457 drm_property_create_enum(rdev->ddev, 0,
1459 radeon_output_csc_enum_list, sz);
1464 void radeon_update_display_priority(struct radeon_device *rdev)
1466 /* adjustment options for the display watermarks */
1467 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1468 /* set display priority to high for r3xx, rv515 chips
1469 * this avoids flickering due to underflow to the
1470 * display controllers during heavy acceleration.
1471 * Don't force high on rs4xx igp chips as it seems to
1472 * affect the sound card. See kernel bug 15982.
1474 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1475 !(rdev->flags & RADEON_IS_IGP))
1476 rdev->disp_priority = 2;
1478 rdev->disp_priority = 0;
1480 rdev->disp_priority = radeon_disp_priority;
1485 * Allocate hdmi structs and determine register offsets
1487 static void radeon_afmt_init(struct radeon_device *rdev)
1491 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1492 rdev->mode_info.afmt[i] = NULL;
1494 if (ASIC_IS_NODCE(rdev)) {
1496 } else if (ASIC_IS_DCE4(rdev)) {
1497 static uint32_t eg_offsets[] = {
1498 EVERGREEN_CRTC0_REGISTER_OFFSET,
1499 EVERGREEN_CRTC1_REGISTER_OFFSET,
1500 EVERGREEN_CRTC2_REGISTER_OFFSET,
1501 EVERGREEN_CRTC3_REGISTER_OFFSET,
1502 EVERGREEN_CRTC4_REGISTER_OFFSET,
1503 EVERGREEN_CRTC5_REGISTER_OFFSET,
1508 /* DCE8 has 7 audio blocks tied to DIG encoders */
1509 /* DCE6 has 6 audio blocks tied to DIG encoders */
1510 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1511 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1512 if (ASIC_IS_DCE8(rdev))
1514 else if (ASIC_IS_DCE6(rdev))
1516 else if (ASIC_IS_DCE5(rdev))
1518 else if (ASIC_IS_DCE41(rdev))
1523 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1524 for (i = 0; i < num_afmt; i++) {
1525 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1526 if (rdev->mode_info.afmt[i]) {
1527 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1528 rdev->mode_info.afmt[i]->id = i;
1531 } else if (ASIC_IS_DCE3(rdev)) {
1532 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1533 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1534 if (rdev->mode_info.afmt[0]) {
1535 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1536 rdev->mode_info.afmt[0]->id = 0;
1538 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1539 if (rdev->mode_info.afmt[1]) {
1540 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1541 rdev->mode_info.afmt[1]->id = 1;
1543 } else if (ASIC_IS_DCE2(rdev)) {
1544 /* DCE2 has at least 1 routable audio block */
1545 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1546 if (rdev->mode_info.afmt[0]) {
1547 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1548 rdev->mode_info.afmt[0]->id = 0;
1550 /* r6xx has 2 routable audio blocks */
1551 if (rdev->family >= CHIP_R600) {
1552 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1553 if (rdev->mode_info.afmt[1]) {
1554 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1555 rdev->mode_info.afmt[1]->id = 1;
1561 static void radeon_afmt_fini(struct radeon_device *rdev)
1565 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1566 kfree(rdev->mode_info.afmt[i]);
1567 rdev->mode_info.afmt[i] = NULL;
1571 int radeon_modeset_init(struct radeon_device *rdev)
1576 drm_mode_config_init(rdev->ddev);
1577 rdev->mode_info.mode_config_initialized = true;
1579 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1581 if (ASIC_IS_DCE5(rdev)) {
1582 rdev->ddev->mode_config.max_width = 16384;
1583 rdev->ddev->mode_config.max_height = 16384;
1584 } else if (ASIC_IS_AVIVO(rdev)) {
1585 rdev->ddev->mode_config.max_width = 8192;
1586 rdev->ddev->mode_config.max_height = 8192;
1588 rdev->ddev->mode_config.max_width = 4096;
1589 rdev->ddev->mode_config.max_height = 4096;
1592 rdev->ddev->mode_config.preferred_depth = 24;
1593 rdev->ddev->mode_config.prefer_shadow = 1;
1595 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1597 ret = radeon_modeset_create_props(rdev);
1602 /* init i2c buses */
1603 radeon_i2c_init(rdev);
1605 /* check combios for a valid hardcoded EDID - Sun servers */
1606 if (!rdev->is_atom_bios) {
1607 /* check for hardcoded EDID in BIOS */
1608 radeon_combios_check_hardcoded_edid(rdev);
1611 /* allocate crtcs */
1612 for (i = 0; i < rdev->num_crtc; i++) {
1613 radeon_crtc_init(rdev->ddev, i);
1616 /* okay we should have all the bios connectors */
1617 ret = radeon_setup_enc_conn(rdev->ddev);
1622 /* init dig PHYs, disp eng pll */
1623 if (rdev->is_atom_bios) {
1624 radeon_atom_encoder_init(rdev);
1625 radeon_atom_disp_eng_pll_init(rdev);
1628 /* initialize hpd */
1629 radeon_hpd_init(rdev);
1632 radeon_afmt_init(rdev);
1634 radeon_fbdev_init(rdev);
1635 drm_kms_helper_poll_init(rdev->ddev);
1637 if (rdev->pm.dpm_enabled) {
1638 /* do dpm late init */
1639 ret = radeon_pm_late_init(rdev);
1641 rdev->pm.dpm_enabled = false;
1642 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1644 /* set the dpm state for PX since there won't be
1645 * a modeset to call this.
1647 radeon_pm_compute_clocks(rdev);
1653 void radeon_modeset_fini(struct radeon_device *rdev)
1655 radeon_fbdev_fini(rdev);
1656 kfree(rdev->mode_info.bios_hardcoded_edid);
1658 if (rdev->mode_info.mode_config_initialized) {
1659 radeon_afmt_fini(rdev);
1660 drm_kms_helper_poll_fini(rdev->ddev);
1661 radeon_hpd_fini(rdev);
1662 drm_mode_config_cleanup(rdev->ddev);
1663 rdev->mode_info.mode_config_initialized = false;
1665 /* free i2c buses */
1666 radeon_i2c_fini(rdev);
1669 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1671 /* try and guess if this is a tv or a monitor */
1672 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1673 (mode->vdisplay == 576) || /* 576p */
1674 (mode->vdisplay == 720) || /* 720p */
1675 (mode->vdisplay == 1080)) /* 1080p */
1681 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1682 const struct drm_display_mode *mode,
1683 struct drm_display_mode *adjusted_mode)
1685 struct drm_device *dev = crtc->dev;
1686 struct radeon_device *rdev = dev->dev_private;
1687 struct drm_encoder *encoder;
1688 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1689 struct radeon_encoder *radeon_encoder;
1690 struct drm_connector *connector;
1691 struct radeon_connector *radeon_connector;
1693 u32 src_v = 1, dst_v = 1;
1694 u32 src_h = 1, dst_h = 1;
1696 radeon_crtc->h_border = 0;
1697 radeon_crtc->v_border = 0;
1699 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1700 if (encoder->crtc != crtc)
1702 radeon_encoder = to_radeon_encoder(encoder);
1703 connector = radeon_get_connector_for_encoder(encoder);
1704 radeon_connector = to_radeon_connector(connector);
1708 if (radeon_encoder->rmx_type == RMX_OFF)
1709 radeon_crtc->rmx_type = RMX_OFF;
1710 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1711 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1712 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1714 radeon_crtc->rmx_type = RMX_OFF;
1715 /* copy native mode */
1716 memcpy(&radeon_crtc->native_mode,
1717 &radeon_encoder->native_mode,
1718 sizeof(struct drm_display_mode));
1719 src_v = crtc->mode.vdisplay;
1720 dst_v = radeon_crtc->native_mode.vdisplay;
1721 src_h = crtc->mode.hdisplay;
1722 dst_h = radeon_crtc->native_mode.hdisplay;
1724 /* fix up for overscan on hdmi */
1725 if (ASIC_IS_AVIVO(rdev) &&
1726 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1727 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1728 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1729 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1730 is_hdtv_mode(mode)))) {
1731 if (radeon_encoder->underscan_hborder != 0)
1732 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1734 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1735 if (radeon_encoder->underscan_vborder != 0)
1736 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1738 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1739 radeon_crtc->rmx_type = RMX_FULL;
1740 src_v = crtc->mode.vdisplay;
1741 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1742 src_h = crtc->mode.hdisplay;
1743 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1747 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1748 /* WARNING: Right now this can't happen but
1749 * in the future we need to check that scaling
1750 * are consistent across different encoder
1751 * (ie all encoder can work with the same
1754 DRM_ERROR("Scaling not consistent across encoder.\n");
1759 if (radeon_crtc->rmx_type != RMX_OFF) {
1761 a.full = dfixed_const(src_v);
1762 b.full = dfixed_const(dst_v);
1763 radeon_crtc->vsc.full = dfixed_div(a, b);
1764 a.full = dfixed_const(src_h);
1765 b.full = dfixed_const(dst_h);
1766 radeon_crtc->hsc.full = dfixed_div(a, b);
1768 radeon_crtc->vsc.full = dfixed_const(1);
1769 radeon_crtc->hsc.full = dfixed_const(1);
1775 * Retrieve current video scanout position of crtc on a given gpu, and
1776 * an optional accurate timestamp of when query happened.
1778 * \param dev Device to query.
1779 * \param crtc Crtc to query.
1780 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1781 * \param *vpos Location where vertical scanout position should be stored.
1782 * \param *hpos Location where horizontal scanout position should go.
1783 * \param *stime Target location for timestamp taken immediately before
1784 * scanout position query. Can be NULL to skip timestamp.
1785 * \param *etime Target location for timestamp taken immediately after
1786 * scanout position query. Can be NULL to skip timestamp.
1788 * Returns vpos as a positive number while in active scanout area.
1789 * Returns vpos as a negative number inside vblank, counting the number
1790 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1791 * until start of active scanout / end of vblank."
1793 * \return Flags, or'ed together as follows:
1795 * DRM_SCANOUTPOS_VALID = Query successful.
1796 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1797 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1798 * this flag means that returned position may be offset by a constant but
1799 * unknown small number of scanlines wrt. real scanout position.
1802 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1803 unsigned int flags, int *vpos, int *hpos,
1804 ktime_t *stime, ktime_t *etime,
1805 const struct drm_display_mode *mode)
1807 u32 stat_crtc = 0, vbl = 0, position = 0;
1808 int vbl_start, vbl_end, vtotal, ret = 0;
1811 struct radeon_device *rdev = dev->dev_private;
1813 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1815 /* Get optional system timestamp before query. */
1817 *stime = ktime_get();
1819 if (ASIC_IS_DCE4(rdev)) {
1821 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1822 EVERGREEN_CRTC0_REGISTER_OFFSET);
1823 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1824 EVERGREEN_CRTC0_REGISTER_OFFSET);
1825 ret |= DRM_SCANOUTPOS_VALID;
1828 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1829 EVERGREEN_CRTC1_REGISTER_OFFSET);
1830 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1831 EVERGREEN_CRTC1_REGISTER_OFFSET);
1832 ret |= DRM_SCANOUTPOS_VALID;
1835 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1836 EVERGREEN_CRTC2_REGISTER_OFFSET);
1837 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1838 EVERGREEN_CRTC2_REGISTER_OFFSET);
1839 ret |= DRM_SCANOUTPOS_VALID;
1842 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1843 EVERGREEN_CRTC3_REGISTER_OFFSET);
1844 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1845 EVERGREEN_CRTC3_REGISTER_OFFSET);
1846 ret |= DRM_SCANOUTPOS_VALID;
1849 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1850 EVERGREEN_CRTC4_REGISTER_OFFSET);
1851 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1852 EVERGREEN_CRTC4_REGISTER_OFFSET);
1853 ret |= DRM_SCANOUTPOS_VALID;
1856 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1857 EVERGREEN_CRTC5_REGISTER_OFFSET);
1858 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1859 EVERGREEN_CRTC5_REGISTER_OFFSET);
1860 ret |= DRM_SCANOUTPOS_VALID;
1862 } else if (ASIC_IS_AVIVO(rdev)) {
1864 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1865 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1866 ret |= DRM_SCANOUTPOS_VALID;
1869 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1870 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1871 ret |= DRM_SCANOUTPOS_VALID;
1874 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1876 /* Assume vbl_end == 0, get vbl_start from
1879 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1880 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1881 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1882 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1883 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1884 if (!(stat_crtc & 1))
1887 ret |= DRM_SCANOUTPOS_VALID;
1890 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1891 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1892 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1893 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1894 if (!(stat_crtc & 1))
1897 ret |= DRM_SCANOUTPOS_VALID;
1901 /* Get optional system timestamp after query. */
1903 *etime = ktime_get();
1905 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1907 /* Decode into vertical and horizontal scanout position. */
1908 *vpos = position & 0x1fff;
1909 *hpos = (position >> 16) & 0x1fff;
1911 /* Valid vblank area boundaries from gpu retrieved? */
1914 ret |= DRM_SCANOUTPOS_ACCURATE;
1915 vbl_start = vbl & 0x1fff;
1916 vbl_end = (vbl >> 16) & 0x1fff;
1919 /* No: Fake something reasonable which gives at least ok results. */
1920 vbl_start = mode->crtc_vdisplay;
1924 /* Test scanout position against vblank region. */
1925 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1928 /* Check if inside vblank area and apply corrective offsets:
1929 * vpos will then be >=0 in video scanout area, but negative
1930 * within vblank area, counting down the number of lines until
1934 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1935 if (in_vbl && (*vpos >= vbl_start)) {
1936 vtotal = mode->crtc_vtotal;
1937 *vpos = *vpos - vtotal;
1940 /* Correct for shifted end of vbl at vbl_end. */
1941 *vpos = *vpos - vbl_end;
1945 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1947 /* Is vpos outside nominal vblank area, but less than
1948 * 1/100 of a frame height away from start of vblank?
1949 * If so, assume this isn't a massively delayed vblank
1950 * interrupt, but a vblank interrupt that fired a few
1951 * microseconds before true start of vblank. Compensate
1952 * by adding a full frame duration to the final timestamp.
1953 * Happens, e.g., on ATI R500, R600.
1955 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1957 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1958 vbl_start = mode->crtc_vdisplay;
1959 vtotal = mode->crtc_vtotal;
1961 if (vbl_start - *vpos < vtotal / 100) {
1964 /* Signal this correction as "applied". */