2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/radeon_drm.h>
31 #include <asm/div64.h>
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
37 #include <linux/gcd.h>
39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
46 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
47 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
58 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
59 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
62 for (i = 0; i < 256; i++) {
63 WREG32(AVIVO_DC_LUT_30_COLOR,
64 (radeon_crtc->lut_r[i] << 20) |
65 (radeon_crtc->lut_g[i] << 10) |
66 (radeon_crtc->lut_b[i] << 0));
69 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
74 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
75 struct drm_device *dev = crtc->dev;
76 struct radeon_device *rdev = dev->dev_private;
79 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
80 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
91 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
93 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
94 for (i = 0; i < 256; i++) {
95 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
96 (radeon_crtc->lut_r[i] << 20) |
97 (radeon_crtc->lut_g[i] << 10) |
98 (radeon_crtc->lut_b[i] << 0));
102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
104 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
105 struct drm_device *dev = crtc->dev;
106 struct radeon_device *rdev = dev->dev_private;
109 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
111 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
112 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
113 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
114 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
115 NI_GRPH_PRESCALE_BYPASS);
116 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
117 NI_OVL_PRESCALE_BYPASS);
118 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
119 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
120 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
122 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
132 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
133 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
135 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
136 for (i = 0; i < 256; i++) {
137 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
138 (radeon_crtc->lut_r[i] << 20) |
139 (radeon_crtc->lut_g[i] << 10) |
140 (radeon_crtc->lut_b[i] << 0));
143 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
144 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
147 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
148 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
150 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
151 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
152 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
153 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
154 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
155 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
156 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
157 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
158 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
159 if (ASIC_IS_DCE8(rdev)) {
160 /* XXX this only needs to be programmed once per crtc at startup,
161 * not sure where the best place for it is
163 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
164 CIK_CURSOR_ALPHA_BLND_ENA);
168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
176 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
177 if (radeon_crtc->crtc_id == 0)
178 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
180 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
181 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
183 WREG8(RADEON_PALETTE_INDEX, 0);
184 for (i = 0; i < 256; i++) {
185 WREG32(RADEON_PALETTE_30_DATA,
186 (radeon_crtc->lut_r[i] << 20) |
187 (radeon_crtc->lut_g[i] << 10) |
188 (radeon_crtc->lut_b[i] << 0));
192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
194 struct drm_device *dev = crtc->dev;
195 struct radeon_device *rdev = dev->dev_private;
200 if (ASIC_IS_DCE5(rdev))
201 dce5_crtc_load_lut(crtc);
202 else if (ASIC_IS_DCE4(rdev))
203 dce4_crtc_load_lut(crtc);
204 else if (ASIC_IS_AVIVO(rdev))
205 avivo_crtc_load_lut(crtc);
207 legacy_crtc_load_lut(crtc);
210 /** Sets the color ramps on behalf of fbcon */
211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
216 radeon_crtc->lut_r[regno] = red >> 6;
217 radeon_crtc->lut_g[regno] = green >> 6;
218 radeon_crtc->lut_b[regno] = blue >> 6;
221 /** Gets the color ramps on behalf of fbcon */
222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
223 u16 *blue, int regno)
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 *red = radeon_crtc->lut_r[regno] << 6;
228 *green = radeon_crtc->lut_g[regno] << 6;
229 *blue = radeon_crtc->lut_b[regno] << 6;
232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
233 u16 *blue, uint32_t start, uint32_t size)
235 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
236 int end = (start + size > 256) ? 256 : start + size, i;
238 /* userspace palettes are always correct as is */
239 for (i = start; i < end; i++) {
240 radeon_crtc->lut_r[i] = red[i] >> 6;
241 radeon_crtc->lut_g[i] = green[i] >> 6;
242 radeon_crtc->lut_b[i] = blue[i] >> 6;
244 radeon_crtc_load_lut(crtc);
247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 drm_crtc_cleanup(crtc);
256 * Handle unpin events outside the interrupt handler proper.
258 static void radeon_unpin_work_func(struct work_struct *__work)
260 struct radeon_unpin_work *work =
261 container_of(__work, struct radeon_unpin_work, work);
264 /* unpin of the old buffer */
265 r = radeon_bo_reserve(work->old_rbo, false);
266 if (likely(r == 0)) {
267 r = radeon_bo_unpin(work->old_rbo);
268 if (unlikely(r != 0)) {
269 DRM_ERROR("failed to unpin buffer after flip\n");
271 radeon_bo_unreserve(work->old_rbo);
273 DRM_ERROR("failed to reserve buffer after flip\n");
275 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
281 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
282 struct radeon_unpin_work *work;
287 /* can happen during initialization */
288 if (radeon_crtc == NULL)
291 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
292 work = radeon_crtc->unpin_work;
294 (work->fence && !radeon_fence_signaled(work->fence))) {
295 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
298 /* New pageflip, or just completion of a previous one? */
299 if (!radeon_crtc->deferred_flip_completion) {
300 /* do the flip (mmio) */
301 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
303 /* This is just a completion of a flip queued in crtc
304 * at last invocation. Make sure we go directly to
305 * completion routine.
308 radeon_crtc->deferred_flip_completion = 0;
311 /* Has the pageflip already completed in crtc, or is it certain
312 * to complete in this vblank?
314 if (update_pending &&
315 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
316 &vpos, &hpos, NULL, NULL)) &&
317 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
318 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
319 /* crtc didn't flip in this target vblank interval,
320 * but flip is pending in crtc. Based on the current
321 * scanout position we know that the current frame is
322 * (nearly) complete and the flip will (likely)
323 * complete before the start of the next frame.
327 if (update_pending) {
328 /* crtc didn't flip in this target vblank interval,
329 * but flip is pending in crtc. It will complete it
330 * in next vblank interval, so complete the flip at
333 radeon_crtc->deferred_flip_completion = 1;
334 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
338 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
339 radeon_crtc->unpin_work = NULL;
341 /* wakeup userspace */
343 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
345 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
347 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
348 radeon_fence_unref(&work->fence);
349 radeon_post_page_flip(work->rdev, work->crtc_id);
350 schedule_work(&work->work);
353 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
354 struct drm_framebuffer *fb,
355 struct drm_pending_vblank_event *event,
356 uint32_t page_flip_flags)
358 struct drm_device *dev = crtc->dev;
359 struct radeon_device *rdev = dev->dev_private;
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct radeon_framebuffer *old_radeon_fb;
362 struct radeon_framebuffer *new_radeon_fb;
363 struct drm_gem_object *obj;
364 struct radeon_bo *rbo;
365 struct radeon_unpin_work *work;
367 u32 tiling_flags, pitch_pixels;
371 work = kzalloc(sizeof *work, GFP_KERNEL);
377 work->crtc_id = radeon_crtc->crtc_id;
378 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
379 new_radeon_fb = to_radeon_framebuffer(fb);
380 /* schedule unpin of the old buffer */
381 obj = old_radeon_fb->obj;
382 /* take a reference to the old object */
383 drm_gem_object_reference(obj);
384 rbo = gem_to_radeon_bo(obj);
386 obj = new_radeon_fb->obj;
387 rbo = gem_to_radeon_bo(obj);
389 spin_lock(&rbo->tbo.bdev->fence_lock);
390 if (rbo->tbo.sync_obj)
391 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
392 spin_unlock(&rbo->tbo.bdev->fence_lock);
394 INIT_WORK(&work->work, radeon_unpin_work_func);
396 /* We borrow the event spin lock for protecting unpin_work */
397 spin_lock_irqsave(&dev->event_lock, flags);
398 if (radeon_crtc->unpin_work) {
399 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
403 radeon_crtc->unpin_work = work;
404 radeon_crtc->deferred_flip_completion = 0;
405 spin_unlock_irqrestore(&dev->event_lock, flags);
407 /* pin the new buffer */
408 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
411 r = radeon_bo_reserve(rbo, false);
412 if (unlikely(r != 0)) {
413 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
416 /* Only 27 bit offset for legacy CRTC */
417 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
418 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
419 if (unlikely(r != 0)) {
420 radeon_bo_unreserve(rbo);
422 DRM_ERROR("failed to pin new rbo buffer before flip\n");
425 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
426 radeon_bo_unreserve(rbo);
428 if (!ASIC_IS_AVIVO(rdev)) {
429 /* crtc offset is from display base addr not FB location */
430 base -= radeon_crtc->legacy_display_base_addr;
431 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
433 if (tiling_flags & RADEON_TILING_MACRO) {
434 if (ASIC_IS_R300(rdev)) {
437 int byteshift = fb->bits_per_pixel >> 4;
438 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
439 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
442 int offset = crtc->y * pitch_pixels + crtc->x;
443 switch (fb->bits_per_pixel) {
464 spin_lock_irqsave(&dev->event_lock, flags);
465 work->new_crtc_base = base;
466 spin_unlock_irqrestore(&dev->event_lock, flags);
469 crtc->primary->fb = fb;
471 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
473 DRM_ERROR("failed to get vblank before flip\n");
477 /* set the proper interrupt */
478 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
483 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
484 DRM_ERROR("failed to reserve new rbo in error path\n");
487 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
488 DRM_ERROR("failed to unpin new rbo in error path\n");
490 radeon_bo_unreserve(rbo);
493 spin_lock_irqsave(&dev->event_lock, flags);
494 radeon_crtc->unpin_work = NULL;
496 spin_unlock_irqrestore(&dev->event_lock, flags);
497 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
498 radeon_fence_unref(&work->fence);
505 radeon_crtc_set_config(struct drm_mode_set *set)
507 struct drm_device *dev;
508 struct radeon_device *rdev;
509 struct drm_crtc *crtc;
513 if (!set || !set->crtc)
516 dev = set->crtc->dev;
518 ret = pm_runtime_get_sync(dev->dev);
522 ret = drm_crtc_helper_set_config(set);
524 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
528 pm_runtime_mark_last_busy(dev->dev);
530 rdev = dev->dev_private;
531 /* if we have active crtcs and we don't have a power ref,
532 take the current one */
533 if (active && !rdev->have_disp_power_ref) {
534 rdev->have_disp_power_ref = true;
537 /* if we have no active crtcs, then drop the power ref
539 if (!active && rdev->have_disp_power_ref) {
540 pm_runtime_put_autosuspend(dev->dev);
541 rdev->have_disp_power_ref = false;
544 /* drop the power reference we got coming in here */
545 pm_runtime_put_autosuspend(dev->dev);
548 static const struct drm_crtc_funcs radeon_crtc_funcs = {
549 .cursor_set = radeon_crtc_cursor_set,
550 .cursor_move = radeon_crtc_cursor_move,
551 .gamma_set = radeon_crtc_gamma_set,
552 .set_config = radeon_crtc_set_config,
553 .destroy = radeon_crtc_destroy,
554 .page_flip = radeon_crtc_page_flip,
557 static void radeon_crtc_init(struct drm_device *dev, int index)
559 struct radeon_device *rdev = dev->dev_private;
560 struct radeon_crtc *radeon_crtc;
563 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
564 if (radeon_crtc == NULL)
567 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
569 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
570 radeon_crtc->crtc_id = index;
571 rdev->mode_info.crtcs[index] = radeon_crtc;
573 if (rdev->family >= CHIP_BONAIRE) {
574 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
575 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
577 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
578 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
580 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
581 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
584 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
585 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
586 radeon_crtc->mode_set.num_connectors = 0;
589 for (i = 0; i < 256; i++) {
590 radeon_crtc->lut_r[i] = i << 2;
591 radeon_crtc->lut_g[i] = i << 2;
592 radeon_crtc->lut_b[i] = i << 2;
595 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
596 radeon_atombios_init_crtc(dev, radeon_crtc);
598 radeon_legacy_init_crtc(dev, radeon_crtc);
601 static const char *encoder_names[38] = {
621 "INTERNAL_KLDSCP_TMDS1",
622 "INTERNAL_KLDSCP_DVO1",
623 "INTERNAL_KLDSCP_DAC1",
624 "INTERNAL_KLDSCP_DAC2",
633 "INTERNAL_KLDSCP_LVTMA",
642 static const char *hpd_names[6] = {
651 static void radeon_print_display_setup(struct drm_device *dev)
653 struct drm_connector *connector;
654 struct radeon_connector *radeon_connector;
655 struct drm_encoder *encoder;
656 struct radeon_encoder *radeon_encoder;
660 DRM_INFO("Radeon Display Connectors\n");
661 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
662 radeon_connector = to_radeon_connector(connector);
663 DRM_INFO("Connector %d:\n", i);
664 DRM_INFO(" %s\n", drm_get_connector_name(connector));
665 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
666 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
667 if (radeon_connector->ddc_bus) {
668 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
669 radeon_connector->ddc_bus->rec.mask_clk_reg,
670 radeon_connector->ddc_bus->rec.mask_data_reg,
671 radeon_connector->ddc_bus->rec.a_clk_reg,
672 radeon_connector->ddc_bus->rec.a_data_reg,
673 radeon_connector->ddc_bus->rec.en_clk_reg,
674 radeon_connector->ddc_bus->rec.en_data_reg,
675 radeon_connector->ddc_bus->rec.y_clk_reg,
676 radeon_connector->ddc_bus->rec.y_data_reg);
677 if (radeon_connector->router.ddc_valid)
678 DRM_INFO(" DDC Router 0x%x/0x%x\n",
679 radeon_connector->router.ddc_mux_control_pin,
680 radeon_connector->router.ddc_mux_state);
681 if (radeon_connector->router.cd_valid)
682 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
683 radeon_connector->router.cd_mux_control_pin,
684 radeon_connector->router.cd_mux_state);
686 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
687 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
688 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
689 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
690 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
691 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
692 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
694 DRM_INFO(" Encoders:\n");
695 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
696 radeon_encoder = to_radeon_encoder(encoder);
697 devices = radeon_encoder->devices & radeon_connector->devices;
699 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
700 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
701 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
702 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
703 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
704 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
705 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
706 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
707 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
708 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
709 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
710 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
711 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
712 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
713 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
714 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
715 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
716 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
717 if (devices & ATOM_DEVICE_TV1_SUPPORT)
718 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
719 if (devices & ATOM_DEVICE_CV_SUPPORT)
720 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
727 static bool radeon_setup_enc_conn(struct drm_device *dev)
729 struct radeon_device *rdev = dev->dev_private;
733 if (rdev->is_atom_bios) {
734 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
736 ret = radeon_get_atom_connector_info_from_object_table(dev);
738 ret = radeon_get_legacy_connector_info_from_bios(dev);
740 ret = radeon_get_legacy_connector_info_from_table(dev);
743 if (!ASIC_IS_AVIVO(rdev))
744 ret = radeon_get_legacy_connector_info_from_table(dev);
747 radeon_setup_encoder_clones(dev);
748 radeon_print_display_setup(dev);
754 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
756 struct drm_device *dev = radeon_connector->base.dev;
757 struct radeon_device *rdev = dev->dev_private;
760 /* on hw with routers, select right port */
761 if (radeon_connector->router.ddc_valid)
762 radeon_router_select_ddc_port(radeon_connector);
764 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
765 ENCODER_OBJECT_ID_NONE) {
766 if (radeon_connector->ddc_bus->has_aux)
767 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
768 &radeon_connector->ddc_bus->aux.ddc);
769 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
770 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
771 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
773 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
774 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
775 radeon_connector->ddc_bus->has_aux)
776 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
777 &radeon_connector->ddc_bus->aux.ddc);
778 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
779 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
780 &radeon_connector->ddc_bus->adapter);
782 if (radeon_connector->ddc_bus && !radeon_connector->edid)
783 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
784 &radeon_connector->ddc_bus->adapter);
787 if (!radeon_connector->edid) {
788 if (rdev->is_atom_bios) {
789 /* some laptops provide a hardcoded edid in rom for LCDs */
790 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
791 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
792 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
794 /* some servers provide a hardcoded edid in rom for KVMs */
795 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
797 if (radeon_connector->edid) {
798 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
799 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
800 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
803 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
810 * avivo_reduce_ratio - fractional number reduction
814 * @nom_min: minimum value for nominator
815 * @den_min: minimum value for denominator
817 * Find the greatest common divisor and apply it on both nominator and
818 * denominator, but make nominator and denominator are at least as large
819 * as their minimum values.
821 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
822 unsigned nom_min, unsigned den_min)
826 /* reduce the numbers to a simpler ratio */
827 tmp = gcd(*nom, *den);
831 /* make sure nominator is large enough */
832 if (*nom < nom_min) {
833 tmp = (nom_min + *nom - 1) / *nom;
838 /* make sure the denominator is large enough */
839 if (*den < den_min) {
840 tmp = (den_min + *den - 1) / *den;
847 * avivo_get_fb_ref_div - feedback and ref divider calculation
851 * @post_div: post divider
852 * @fb_div_max: feedback divider maximum
853 * @ref_div_max: reference divider maximum
854 * @fb_div: resulting feedback divider
855 * @ref_div: resulting reference divider
857 * Calculate feedback and reference divider for a given post divider. Makes
858 * sure we stay within the limits.
860 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
861 unsigned fb_div_max, unsigned ref_div_max,
862 unsigned *fb_div, unsigned *ref_div)
864 /* limit reference * post divider to a maximum */
865 ref_div_max = min(210 / post_div, ref_div_max);
867 /* get matching reference and feedback divider */
868 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
869 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
871 /* limit fb divider to its maximum */
872 if (*fb_div > fb_div_max) {
873 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
874 *fb_div = fb_div_max;
879 * radeon_compute_pll_avivo - compute PLL paramaters
881 * @pll: information about the PLL
882 * @dot_clock_p: resulting pixel clock
883 * fb_div_p: resulting feedback divider
884 * frac_fb_div_p: fractional part of the feedback divider
885 * ref_div_p: resulting reference divider
886 * post_div_p: resulting reference divider
888 * Try to calculate the PLL parameters to generate the given frequency:
889 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
891 void radeon_compute_pll_avivo(struct radeon_pll *pll,
899 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
902 unsigned fb_div_min, fb_div_max, fb_div;
903 unsigned post_div_min, post_div_max, post_div;
904 unsigned ref_div_min, ref_div_max, ref_div;
905 unsigned post_div_best, diff_best;
908 /* determine allowed feedback divider range */
909 fb_div_min = pll->min_feedback_div;
910 fb_div_max = pll->max_feedback_div;
912 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
917 /* determine allowed ref divider range */
918 if (pll->flags & RADEON_PLL_USE_REF_DIV)
919 ref_div_min = pll->reference_div;
921 ref_div_min = pll->min_ref_div;
923 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
924 pll->flags & RADEON_PLL_USE_REF_DIV)
925 ref_div_max = pll->reference_div;
927 ref_div_max = pll->max_ref_div;
929 /* determine allowed post divider range */
930 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
931 post_div_min = pll->post_div;
932 post_div_max = pll->post_div;
934 unsigned vco_min, vco_max;
936 if (pll->flags & RADEON_PLL_IS_LCD) {
937 vco_min = pll->lcd_pll_out_min;
938 vco_max = pll->lcd_pll_out_max;
940 vco_min = pll->pll_out_min;
941 vco_max = pll->pll_out_max;
944 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
949 post_div_min = vco_min / target_clock;
950 if ((target_clock * post_div_min) < vco_min)
952 if (post_div_min < pll->min_post_div)
953 post_div_min = pll->min_post_div;
955 post_div_max = vco_max / target_clock;
956 if ((target_clock * post_div_max) > vco_max)
958 if (post_div_max > pll->max_post_div)
959 post_div_max = pll->max_post_div;
962 /* represent the searched ratio as fractional number */
964 den = pll->reference_freq;
966 /* reduce the numbers to a simpler ratio */
967 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
969 /* now search for a post divider */
970 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
971 post_div_best = post_div_min;
973 post_div_best = post_div_max;
976 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
978 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
979 ref_div_max, &fb_div, &ref_div);
980 diff = abs(target_clock - (pll->reference_freq * fb_div) /
981 (ref_div * post_div));
983 if (diff < diff_best || (diff == diff_best &&
984 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
986 post_div_best = post_div;
990 post_div = post_div_best;
992 /* get the feedback and reference divider for the optimal value */
993 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
996 /* reduce the numbers to a simpler ratio once more */
997 /* this also makes sure that the reference divider is large enough */
998 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1000 /* and finally save the result */
1001 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1002 *fb_div_p = fb_div / 10;
1003 *frac_fb_div_p = fb_div % 10;
1009 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1010 (pll->reference_freq * *frac_fb_div_p)) /
1011 (ref_div * post_div * 10);
1012 *ref_div_p = ref_div;
1013 *post_div_p = post_div;
1015 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1016 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1021 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1031 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1033 uint32_t *dot_clock_p,
1035 uint32_t *frac_fb_div_p,
1036 uint32_t *ref_div_p,
1037 uint32_t *post_div_p)
1039 uint32_t min_ref_div = pll->min_ref_div;
1040 uint32_t max_ref_div = pll->max_ref_div;
1041 uint32_t min_post_div = pll->min_post_div;
1042 uint32_t max_post_div = pll->max_post_div;
1043 uint32_t min_fractional_feed_div = 0;
1044 uint32_t max_fractional_feed_div = 0;
1045 uint32_t best_vco = pll->best_vco;
1046 uint32_t best_post_div = 1;
1047 uint32_t best_ref_div = 1;
1048 uint32_t best_feedback_div = 1;
1049 uint32_t best_frac_feedback_div = 0;
1050 uint32_t best_freq = -1;
1051 uint32_t best_error = 0xffffffff;
1052 uint32_t best_vco_diff = 1;
1054 u32 pll_out_min, pll_out_max;
1056 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1059 if (pll->flags & RADEON_PLL_IS_LCD) {
1060 pll_out_min = pll->lcd_pll_out_min;
1061 pll_out_max = pll->lcd_pll_out_max;
1063 pll_out_min = pll->pll_out_min;
1064 pll_out_max = pll->pll_out_max;
1067 if (pll_out_min > 64800)
1068 pll_out_min = 64800;
1070 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1071 min_ref_div = max_ref_div = pll->reference_div;
1073 while (min_ref_div < max_ref_div-1) {
1074 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1075 uint32_t pll_in = pll->reference_freq / mid;
1076 if (pll_in < pll->pll_in_min)
1078 else if (pll_in > pll->pll_in_max)
1085 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1086 min_post_div = max_post_div = pll->post_div;
1088 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1089 min_fractional_feed_div = pll->min_frac_feedback_div;
1090 max_fractional_feed_div = pll->max_frac_feedback_div;
1093 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1096 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1099 /* legacy radeons only have a few post_divs */
1100 if (pll->flags & RADEON_PLL_LEGACY) {
1101 if ((post_div == 5) ||
1112 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1113 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1114 uint32_t pll_in = pll->reference_freq / ref_div;
1115 uint32_t min_feed_div = pll->min_feedback_div;
1116 uint32_t max_feed_div = pll->max_feedback_div + 1;
1118 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1121 while (min_feed_div < max_feed_div) {
1123 uint32_t min_frac_feed_div = min_fractional_feed_div;
1124 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1125 uint32_t frac_feedback_div;
1128 feedback_div = (min_feed_div + max_feed_div) / 2;
1130 tmp = (uint64_t)pll->reference_freq * feedback_div;
1131 vco = radeon_div(tmp, ref_div);
1133 if (vco < pll_out_min) {
1134 min_feed_div = feedback_div + 1;
1136 } else if (vco > pll_out_max) {
1137 max_feed_div = feedback_div;
1141 while (min_frac_feed_div < max_frac_feed_div) {
1142 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1143 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1144 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1145 current_freq = radeon_div(tmp, ref_div * post_div);
1147 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1148 if (freq < current_freq)
1151 error = freq - current_freq;
1153 error = abs(current_freq - freq);
1154 vco_diff = abs(vco - best_vco);
1156 if ((best_vco == 0 && error < best_error) ||
1158 ((best_error > 100 && error < best_error - 100) ||
1159 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1160 best_post_div = post_div;
1161 best_ref_div = ref_div;
1162 best_feedback_div = feedback_div;
1163 best_frac_feedback_div = frac_feedback_div;
1164 best_freq = current_freq;
1166 best_vco_diff = vco_diff;
1167 } else if (current_freq == freq) {
1168 if (best_freq == -1) {
1169 best_post_div = post_div;
1170 best_ref_div = ref_div;
1171 best_feedback_div = feedback_div;
1172 best_frac_feedback_div = frac_feedback_div;
1173 best_freq = current_freq;
1175 best_vco_diff = vco_diff;
1176 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1177 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1178 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1179 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1180 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1181 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1182 best_post_div = post_div;
1183 best_ref_div = ref_div;
1184 best_feedback_div = feedback_div;
1185 best_frac_feedback_div = frac_feedback_div;
1186 best_freq = current_freq;
1188 best_vco_diff = vco_diff;
1191 if (current_freq < freq)
1192 min_frac_feed_div = frac_feedback_div + 1;
1194 max_frac_feed_div = frac_feedback_div;
1196 if (current_freq < freq)
1197 min_feed_div = feedback_div + 1;
1199 max_feed_div = feedback_div;
1204 *dot_clock_p = best_freq / 10000;
1205 *fb_div_p = best_feedback_div;
1206 *frac_fb_div_p = best_frac_feedback_div;
1207 *ref_div_p = best_ref_div;
1208 *post_div_p = best_post_div;
1209 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1211 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1212 best_ref_div, best_post_div);
1216 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1218 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1220 if (radeon_fb->obj) {
1221 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1223 drm_framebuffer_cleanup(fb);
1227 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1228 struct drm_file *file_priv,
1229 unsigned int *handle)
1231 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1233 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1236 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1237 .destroy = radeon_user_framebuffer_destroy,
1238 .create_handle = radeon_user_framebuffer_create_handle,
1242 radeon_framebuffer_init(struct drm_device *dev,
1243 struct radeon_framebuffer *rfb,
1244 struct drm_mode_fb_cmd2 *mode_cmd,
1245 struct drm_gem_object *obj)
1249 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1250 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1258 static struct drm_framebuffer *
1259 radeon_user_framebuffer_create(struct drm_device *dev,
1260 struct drm_file *file_priv,
1261 struct drm_mode_fb_cmd2 *mode_cmd)
1263 struct drm_gem_object *obj;
1264 struct radeon_framebuffer *radeon_fb;
1267 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1269 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1270 "can't create framebuffer\n", mode_cmd->handles[0]);
1271 return ERR_PTR(-ENOENT);
1274 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1275 if (radeon_fb == NULL) {
1276 drm_gem_object_unreference_unlocked(obj);
1277 return ERR_PTR(-ENOMEM);
1280 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1283 drm_gem_object_unreference_unlocked(obj);
1284 return ERR_PTR(ret);
1287 return &radeon_fb->base;
1290 static void radeon_output_poll_changed(struct drm_device *dev)
1292 struct radeon_device *rdev = dev->dev_private;
1293 radeon_fb_output_poll_changed(rdev);
1296 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1297 .fb_create = radeon_user_framebuffer_create,
1298 .output_poll_changed = radeon_output_poll_changed
1301 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1306 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1307 { { TV_STD_NTSC, "ntsc" },
1308 { TV_STD_PAL, "pal" },
1309 { TV_STD_PAL_M, "pal-m" },
1310 { TV_STD_PAL_60, "pal-60" },
1311 { TV_STD_NTSC_J, "ntsc-j" },
1312 { TV_STD_SCART_PAL, "scart-pal" },
1313 { TV_STD_PAL_CN, "pal-cn" },
1314 { TV_STD_SECAM, "secam" },
1317 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1318 { { UNDERSCAN_OFF, "off" },
1319 { UNDERSCAN_ON, "on" },
1320 { UNDERSCAN_AUTO, "auto" },
1323 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1324 { { RADEON_AUDIO_DISABLE, "off" },
1325 { RADEON_AUDIO_ENABLE, "on" },
1326 { RADEON_AUDIO_AUTO, "auto" },
1329 /* XXX support different dither options? spatial, temporal, both, etc. */
1330 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1331 { { RADEON_FMT_DITHER_DISABLE, "off" },
1332 { RADEON_FMT_DITHER_ENABLE, "on" },
1335 static int radeon_modeset_create_props(struct radeon_device *rdev)
1339 if (rdev->is_atom_bios) {
1340 rdev->mode_info.coherent_mode_property =
1341 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1342 if (!rdev->mode_info.coherent_mode_property)
1346 if (!ASIC_IS_AVIVO(rdev)) {
1347 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1348 rdev->mode_info.tmds_pll_property =
1349 drm_property_create_enum(rdev->ddev, 0,
1351 radeon_tmds_pll_enum_list, sz);
1354 rdev->mode_info.load_detect_property =
1355 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1356 if (!rdev->mode_info.load_detect_property)
1359 drm_mode_create_scaling_mode_property(rdev->ddev);
1361 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1362 rdev->mode_info.tv_std_property =
1363 drm_property_create_enum(rdev->ddev, 0,
1365 radeon_tv_std_enum_list, sz);
1367 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1368 rdev->mode_info.underscan_property =
1369 drm_property_create_enum(rdev->ddev, 0,
1371 radeon_underscan_enum_list, sz);
1373 rdev->mode_info.underscan_hborder_property =
1374 drm_property_create_range(rdev->ddev, 0,
1375 "underscan hborder", 0, 128);
1376 if (!rdev->mode_info.underscan_hborder_property)
1379 rdev->mode_info.underscan_vborder_property =
1380 drm_property_create_range(rdev->ddev, 0,
1381 "underscan vborder", 0, 128);
1382 if (!rdev->mode_info.underscan_vborder_property)
1385 sz = ARRAY_SIZE(radeon_audio_enum_list);
1386 rdev->mode_info.audio_property =
1387 drm_property_create_enum(rdev->ddev, 0,
1389 radeon_audio_enum_list, sz);
1391 sz = ARRAY_SIZE(radeon_dither_enum_list);
1392 rdev->mode_info.dither_property =
1393 drm_property_create_enum(rdev->ddev, 0,
1395 radeon_dither_enum_list, sz);
1400 void radeon_update_display_priority(struct radeon_device *rdev)
1402 /* adjustment options for the display watermarks */
1403 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1404 /* set display priority to high for r3xx, rv515 chips
1405 * this avoids flickering due to underflow to the
1406 * display controllers during heavy acceleration.
1407 * Don't force high on rs4xx igp chips as it seems to
1408 * affect the sound card. See kernel bug 15982.
1410 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1411 !(rdev->flags & RADEON_IS_IGP))
1412 rdev->disp_priority = 2;
1414 rdev->disp_priority = 0;
1416 rdev->disp_priority = radeon_disp_priority;
1421 * Allocate hdmi structs and determine register offsets
1423 static void radeon_afmt_init(struct radeon_device *rdev)
1427 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1428 rdev->mode_info.afmt[i] = NULL;
1430 if (ASIC_IS_NODCE(rdev)) {
1432 } else if (ASIC_IS_DCE4(rdev)) {
1433 static uint32_t eg_offsets[] = {
1434 EVERGREEN_CRTC0_REGISTER_OFFSET,
1435 EVERGREEN_CRTC1_REGISTER_OFFSET,
1436 EVERGREEN_CRTC2_REGISTER_OFFSET,
1437 EVERGREEN_CRTC3_REGISTER_OFFSET,
1438 EVERGREEN_CRTC4_REGISTER_OFFSET,
1439 EVERGREEN_CRTC5_REGISTER_OFFSET,
1444 /* DCE8 has 7 audio blocks tied to DIG encoders */
1445 /* DCE6 has 6 audio blocks tied to DIG encoders */
1446 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1447 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1448 if (ASIC_IS_DCE8(rdev))
1450 else if (ASIC_IS_DCE6(rdev))
1452 else if (ASIC_IS_DCE5(rdev))
1454 else if (ASIC_IS_DCE41(rdev))
1459 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1460 for (i = 0; i < num_afmt; i++) {
1461 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1462 if (rdev->mode_info.afmt[i]) {
1463 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1464 rdev->mode_info.afmt[i]->id = i;
1467 } else if (ASIC_IS_DCE3(rdev)) {
1468 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1469 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1470 if (rdev->mode_info.afmt[0]) {
1471 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1472 rdev->mode_info.afmt[0]->id = 0;
1474 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1475 if (rdev->mode_info.afmt[1]) {
1476 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1477 rdev->mode_info.afmt[1]->id = 1;
1479 } else if (ASIC_IS_DCE2(rdev)) {
1480 /* DCE2 has at least 1 routable audio block */
1481 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1482 if (rdev->mode_info.afmt[0]) {
1483 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1484 rdev->mode_info.afmt[0]->id = 0;
1486 /* r6xx has 2 routable audio blocks */
1487 if (rdev->family >= CHIP_R600) {
1488 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1489 if (rdev->mode_info.afmt[1]) {
1490 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1491 rdev->mode_info.afmt[1]->id = 1;
1497 static void radeon_afmt_fini(struct radeon_device *rdev)
1501 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1502 kfree(rdev->mode_info.afmt[i]);
1503 rdev->mode_info.afmt[i] = NULL;
1507 int radeon_modeset_init(struct radeon_device *rdev)
1512 drm_mode_config_init(rdev->ddev);
1513 rdev->mode_info.mode_config_initialized = true;
1515 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1517 if (ASIC_IS_DCE5(rdev)) {
1518 rdev->ddev->mode_config.max_width = 16384;
1519 rdev->ddev->mode_config.max_height = 16384;
1520 } else if (ASIC_IS_AVIVO(rdev)) {
1521 rdev->ddev->mode_config.max_width = 8192;
1522 rdev->ddev->mode_config.max_height = 8192;
1524 rdev->ddev->mode_config.max_width = 4096;
1525 rdev->ddev->mode_config.max_height = 4096;
1528 rdev->ddev->mode_config.preferred_depth = 24;
1529 rdev->ddev->mode_config.prefer_shadow = 1;
1531 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1533 ret = radeon_modeset_create_props(rdev);
1538 /* init i2c buses */
1539 radeon_i2c_init(rdev);
1541 /* check combios for a valid hardcoded EDID - Sun servers */
1542 if (!rdev->is_atom_bios) {
1543 /* check for hardcoded EDID in BIOS */
1544 radeon_combios_check_hardcoded_edid(rdev);
1547 /* allocate crtcs */
1548 for (i = 0; i < rdev->num_crtc; i++) {
1549 radeon_crtc_init(rdev->ddev, i);
1552 /* okay we should have all the bios connectors */
1553 ret = radeon_setup_enc_conn(rdev->ddev);
1558 /* init dig PHYs, disp eng pll */
1559 if (rdev->is_atom_bios) {
1560 radeon_atom_encoder_init(rdev);
1561 radeon_atom_disp_eng_pll_init(rdev);
1564 /* initialize hpd */
1565 radeon_hpd_init(rdev);
1568 radeon_afmt_init(rdev);
1570 radeon_fbdev_init(rdev);
1571 drm_kms_helper_poll_init(rdev->ddev);
1573 if (rdev->pm.dpm_enabled) {
1574 /* do dpm late init */
1575 ret = radeon_pm_late_init(rdev);
1577 rdev->pm.dpm_enabled = false;
1578 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1580 /* set the dpm state for PX since there won't be
1581 * a modeset to call this.
1583 radeon_pm_compute_clocks(rdev);
1589 void radeon_modeset_fini(struct radeon_device *rdev)
1591 radeon_fbdev_fini(rdev);
1592 kfree(rdev->mode_info.bios_hardcoded_edid);
1594 if (rdev->mode_info.mode_config_initialized) {
1595 radeon_afmt_fini(rdev);
1596 drm_kms_helper_poll_fini(rdev->ddev);
1597 radeon_hpd_fini(rdev);
1598 drm_mode_config_cleanup(rdev->ddev);
1599 rdev->mode_info.mode_config_initialized = false;
1601 /* free i2c buses */
1602 radeon_i2c_fini(rdev);
1605 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1607 /* try and guess if this is a tv or a monitor */
1608 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1609 (mode->vdisplay == 576) || /* 576p */
1610 (mode->vdisplay == 720) || /* 720p */
1611 (mode->vdisplay == 1080)) /* 1080p */
1617 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1618 const struct drm_display_mode *mode,
1619 struct drm_display_mode *adjusted_mode)
1621 struct drm_device *dev = crtc->dev;
1622 struct radeon_device *rdev = dev->dev_private;
1623 struct drm_encoder *encoder;
1624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1625 struct radeon_encoder *radeon_encoder;
1626 struct drm_connector *connector;
1627 struct radeon_connector *radeon_connector;
1629 u32 src_v = 1, dst_v = 1;
1630 u32 src_h = 1, dst_h = 1;
1632 radeon_crtc->h_border = 0;
1633 radeon_crtc->v_border = 0;
1635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1636 if (encoder->crtc != crtc)
1638 radeon_encoder = to_radeon_encoder(encoder);
1639 connector = radeon_get_connector_for_encoder(encoder);
1640 radeon_connector = to_radeon_connector(connector);
1644 if (radeon_encoder->rmx_type == RMX_OFF)
1645 radeon_crtc->rmx_type = RMX_OFF;
1646 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1647 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1648 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1650 radeon_crtc->rmx_type = RMX_OFF;
1651 /* copy native mode */
1652 memcpy(&radeon_crtc->native_mode,
1653 &radeon_encoder->native_mode,
1654 sizeof(struct drm_display_mode));
1655 src_v = crtc->mode.vdisplay;
1656 dst_v = radeon_crtc->native_mode.vdisplay;
1657 src_h = crtc->mode.hdisplay;
1658 dst_h = radeon_crtc->native_mode.hdisplay;
1660 /* fix up for overscan on hdmi */
1661 if (ASIC_IS_AVIVO(rdev) &&
1662 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1663 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1664 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1665 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1666 is_hdtv_mode(mode)))) {
1667 if (radeon_encoder->underscan_hborder != 0)
1668 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1670 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1671 if (radeon_encoder->underscan_vborder != 0)
1672 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1674 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1675 radeon_crtc->rmx_type = RMX_FULL;
1676 src_v = crtc->mode.vdisplay;
1677 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1678 src_h = crtc->mode.hdisplay;
1679 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1683 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1684 /* WARNING: Right now this can't happen but
1685 * in the future we need to check that scaling
1686 * are consistent across different encoder
1687 * (ie all encoder can work with the same
1690 DRM_ERROR("Scaling not consistent across encoder.\n");
1695 if (radeon_crtc->rmx_type != RMX_OFF) {
1697 a.full = dfixed_const(src_v);
1698 b.full = dfixed_const(dst_v);
1699 radeon_crtc->vsc.full = dfixed_div(a, b);
1700 a.full = dfixed_const(src_h);
1701 b.full = dfixed_const(dst_h);
1702 radeon_crtc->hsc.full = dfixed_div(a, b);
1704 radeon_crtc->vsc.full = dfixed_const(1);
1705 radeon_crtc->hsc.full = dfixed_const(1);
1711 * Retrieve current video scanout position of crtc on a given gpu, and
1712 * an optional accurate timestamp of when query happened.
1714 * \param dev Device to query.
1715 * \param crtc Crtc to query.
1716 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1717 * \param *vpos Location where vertical scanout position should be stored.
1718 * \param *hpos Location where horizontal scanout position should go.
1719 * \param *stime Target location for timestamp taken immediately before
1720 * scanout position query. Can be NULL to skip timestamp.
1721 * \param *etime Target location for timestamp taken immediately after
1722 * scanout position query. Can be NULL to skip timestamp.
1724 * Returns vpos as a positive number while in active scanout area.
1725 * Returns vpos as a negative number inside vblank, counting the number
1726 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1727 * until start of active scanout / end of vblank."
1729 * \return Flags, or'ed together as follows:
1731 * DRM_SCANOUTPOS_VALID = Query successful.
1732 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1733 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1734 * this flag means that returned position may be offset by a constant but
1735 * unknown small number of scanlines wrt. real scanout position.
1738 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1739 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1741 u32 stat_crtc = 0, vbl = 0, position = 0;
1742 int vbl_start, vbl_end, vtotal, ret = 0;
1745 struct radeon_device *rdev = dev->dev_private;
1747 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1749 /* Get optional system timestamp before query. */
1751 *stime = ktime_get();
1753 if (ASIC_IS_DCE4(rdev)) {
1755 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1756 EVERGREEN_CRTC0_REGISTER_OFFSET);
1757 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1758 EVERGREEN_CRTC0_REGISTER_OFFSET);
1759 ret |= DRM_SCANOUTPOS_VALID;
1762 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1763 EVERGREEN_CRTC1_REGISTER_OFFSET);
1764 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1765 EVERGREEN_CRTC1_REGISTER_OFFSET);
1766 ret |= DRM_SCANOUTPOS_VALID;
1769 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1770 EVERGREEN_CRTC2_REGISTER_OFFSET);
1771 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1772 EVERGREEN_CRTC2_REGISTER_OFFSET);
1773 ret |= DRM_SCANOUTPOS_VALID;
1776 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1777 EVERGREEN_CRTC3_REGISTER_OFFSET);
1778 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1779 EVERGREEN_CRTC3_REGISTER_OFFSET);
1780 ret |= DRM_SCANOUTPOS_VALID;
1783 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1784 EVERGREEN_CRTC4_REGISTER_OFFSET);
1785 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1786 EVERGREEN_CRTC4_REGISTER_OFFSET);
1787 ret |= DRM_SCANOUTPOS_VALID;
1790 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1791 EVERGREEN_CRTC5_REGISTER_OFFSET);
1792 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1793 EVERGREEN_CRTC5_REGISTER_OFFSET);
1794 ret |= DRM_SCANOUTPOS_VALID;
1796 } else if (ASIC_IS_AVIVO(rdev)) {
1798 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1799 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1800 ret |= DRM_SCANOUTPOS_VALID;
1803 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1804 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1805 ret |= DRM_SCANOUTPOS_VALID;
1808 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1810 /* Assume vbl_end == 0, get vbl_start from
1813 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1814 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1815 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1816 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1817 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1818 if (!(stat_crtc & 1))
1821 ret |= DRM_SCANOUTPOS_VALID;
1824 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1825 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1826 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1827 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1828 if (!(stat_crtc & 1))
1831 ret |= DRM_SCANOUTPOS_VALID;
1835 /* Get optional system timestamp after query. */
1837 *etime = ktime_get();
1839 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1841 /* Decode into vertical and horizontal scanout position. */
1842 *vpos = position & 0x1fff;
1843 *hpos = (position >> 16) & 0x1fff;
1845 /* Valid vblank area boundaries from gpu retrieved? */
1848 ret |= DRM_SCANOUTPOS_ACCURATE;
1849 vbl_start = vbl & 0x1fff;
1850 vbl_end = (vbl >> 16) & 0x1fff;
1853 /* No: Fake something reasonable which gives at least ok results. */
1854 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1858 /* Test scanout position against vblank region. */
1859 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1862 /* Check if inside vblank area and apply corrective offsets:
1863 * vpos will then be >=0 in video scanout area, but negative
1864 * within vblank area, counting down the number of lines until
1868 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1869 if (in_vbl && (*vpos >= vbl_start)) {
1870 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1871 *vpos = *vpos - vtotal;
1874 /* Correct for shifted end of vbl at vbl_end. */
1875 *vpos = *vpos - vbl_end;
1879 ret |= DRM_SCANOUTPOS_INVBL;
1881 /* Is vpos outside nominal vblank area, but less than
1882 * 1/100 of a frame height away from start of vblank?
1883 * If so, assume this isn't a massively delayed vblank
1884 * interrupt, but a vblank interrupt that fired a few
1885 * microseconds before true start of vblank. Compensate
1886 * by adding a full frame duration to the final timestamp.
1887 * Happens, e.g., on ATI R500, R600.
1889 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1891 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1892 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1893 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1895 if (vbl_start - *vpos < vtotal / 100) {
1898 /* Signal this correction as "applied". */