2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
37 #include "radeon_reg.h"
41 static const char radeon_family_name[][16] = {
107 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
108 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
110 struct radeon_px_quirk {
118 static struct radeon_px_quirk radeon_px_quirk_list[] = {
119 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
120 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
122 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
123 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
124 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
126 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
127 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
128 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
130 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
131 /* macbook pro 8.2 */
132 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
136 bool radeon_is_px(struct drm_device *dev)
138 struct radeon_device *rdev = dev->dev_private;
140 if (rdev->flags & RADEON_IS_PX)
145 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
147 struct radeon_px_quirk *p = radeon_px_quirk_list;
149 /* Apply PX quirks */
150 while (p && p->chip_device != 0) {
151 if (rdev->pdev->vendor == p->chip_vendor &&
152 rdev->pdev->device == p->chip_device &&
153 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
154 rdev->pdev->subsystem_device == p->subsys_device) {
155 rdev->px_quirk_flags = p->px_quirk_flags;
161 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
162 rdev->flags &= ~RADEON_IS_PX;
166 * radeon_program_register_sequence - program an array of registers.
168 * @rdev: radeon_device pointer
169 * @registers: pointer to the register array
170 * @array_size: size of the register array
172 * Programs an array or registers with and and or masks.
173 * This is a helper for setting golden registers.
175 void radeon_program_register_sequence(struct radeon_device *rdev,
176 const u32 *registers,
177 const u32 array_size)
179 u32 tmp, reg, and_mask, or_mask;
185 for (i = 0; i < array_size; i +=3) {
186 reg = registers[i + 0];
187 and_mask = registers[i + 1];
188 or_mask = registers[i + 2];
190 if (and_mask == 0xffffffff) {
201 void radeon_pci_config_reset(struct radeon_device *rdev)
203 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
207 * radeon_surface_init - Clear GPU surface registers.
209 * @rdev: radeon_device pointer
211 * Clear GPU surface registers (r1xx-r5xx).
213 void radeon_surface_init(struct radeon_device *rdev)
215 /* FIXME: check this out */
216 if (rdev->family < CHIP_R600) {
219 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
220 if (rdev->surface_regs[i].bo)
221 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
223 radeon_clear_surface_reg(rdev, i);
225 /* enable surfaces */
226 WREG32(RADEON_SURFACE_CNTL, 0);
231 * GPU scratch registers helpers function.
234 * radeon_scratch_init - Init scratch register driver information.
236 * @rdev: radeon_device pointer
238 * Init CP scratch register driver information (r1xx-r5xx)
240 void radeon_scratch_init(struct radeon_device *rdev)
244 /* FIXME: check this out */
245 if (rdev->family < CHIP_R300) {
246 rdev->scratch.num_reg = 5;
248 rdev->scratch.num_reg = 7;
250 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
251 for (i = 0; i < rdev->scratch.num_reg; i++) {
252 rdev->scratch.free[i] = true;
253 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
258 * radeon_scratch_get - Allocate a scratch register
260 * @rdev: radeon_device pointer
261 * @reg: scratch register mmio offset
263 * Allocate a CP scratch register for use by the driver (all asics).
264 * Returns 0 on success or -EINVAL on failure.
266 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
270 for (i = 0; i < rdev->scratch.num_reg; i++) {
271 if (rdev->scratch.free[i]) {
272 rdev->scratch.free[i] = false;
273 *reg = rdev->scratch.reg[i];
281 * radeon_scratch_free - Free a scratch register
283 * @rdev: radeon_device pointer
284 * @reg: scratch register mmio offset
286 * Free a CP scratch register allocated for use by the driver (all asics)
288 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
292 for (i = 0; i < rdev->scratch.num_reg; i++) {
293 if (rdev->scratch.reg[i] == reg) {
294 rdev->scratch.free[i] = true;
301 * GPU doorbell aperture helpers function.
304 * radeon_doorbell_init - Init doorbell driver information.
306 * @rdev: radeon_device pointer
308 * Init doorbell driver information (CIK)
309 * Returns 0 on success, error on failure.
311 static int radeon_doorbell_init(struct radeon_device *rdev)
313 /* doorbell bar mapping */
314 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
315 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
317 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
318 if (rdev->doorbell.num_doorbells == 0)
321 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
322 if (rdev->doorbell.ptr == NULL) {
325 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
326 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
328 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
334 * radeon_doorbell_fini - Tear down doorbell driver information.
336 * @rdev: radeon_device pointer
338 * Tear down doorbell driver information (CIK)
340 static void radeon_doorbell_fini(struct radeon_device *rdev)
342 iounmap(rdev->doorbell.ptr);
343 rdev->doorbell.ptr = NULL;
347 * radeon_doorbell_get - Allocate a doorbell entry
349 * @rdev: radeon_device pointer
350 * @doorbell: doorbell index
352 * Allocate a doorbell for use by the driver (all asics).
353 * Returns 0 on success or -EINVAL on failure.
355 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
357 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
358 if (offset < rdev->doorbell.num_doorbells) {
359 __set_bit(offset, rdev->doorbell.used);
368 * radeon_doorbell_free - Free a doorbell entry
370 * @rdev: radeon_device pointer
371 * @doorbell: doorbell index
373 * Free a doorbell allocated for use by the driver (all asics)
375 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
377 if (doorbell < rdev->doorbell.num_doorbells)
378 __clear_bit(doorbell, rdev->doorbell.used);
382 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
385 * @rdev: radeon_device pointer
386 * @aperture_base: output returning doorbell aperture base physical address
387 * @aperture_size: output returning doorbell aperture size in bytes
388 * @start_offset: output returning # of doorbell bytes reserved for radeon.
390 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
391 * takes doorbells required for its own rings and reports the setup to KFD.
392 * Radeon reserved doorbells are at the start of the doorbell aperture.
394 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
395 phys_addr_t *aperture_base,
396 size_t *aperture_size,
397 size_t *start_offset)
399 /* The first num_doorbells are used by radeon.
400 * KFD takes whatever's left in the aperture. */
401 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
402 *aperture_base = rdev->doorbell.base;
403 *aperture_size = rdev->doorbell.size;
404 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
414 * Writeback is the the method by which the the GPU updates special pages
415 * in memory with the status of certain GPU events (fences, ring pointers,
420 * radeon_wb_disable - Disable Writeback
422 * @rdev: radeon_device pointer
424 * Disables Writeback (all asics). Used for suspend.
426 void radeon_wb_disable(struct radeon_device *rdev)
428 rdev->wb.enabled = false;
432 * radeon_wb_fini - Disable Writeback and free memory
434 * @rdev: radeon_device pointer
436 * Disables Writeback and frees the Writeback memory (all asics).
437 * Used at driver shutdown.
439 void radeon_wb_fini(struct radeon_device *rdev)
441 radeon_wb_disable(rdev);
442 if (rdev->wb.wb_obj) {
443 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
444 radeon_bo_kunmap(rdev->wb.wb_obj);
445 radeon_bo_unpin(rdev->wb.wb_obj);
446 radeon_bo_unreserve(rdev->wb.wb_obj);
448 radeon_bo_unref(&rdev->wb.wb_obj);
450 rdev->wb.wb_obj = NULL;
455 * radeon_wb_init- Init Writeback driver info and allocate memory
457 * @rdev: radeon_device pointer
459 * Disables Writeback and frees the Writeback memory (all asics).
460 * Used at driver startup.
461 * Returns 0 on success or an -error on failure.
463 int radeon_wb_init(struct radeon_device *rdev)
467 if (rdev->wb.wb_obj == NULL) {
468 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
469 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
472 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
475 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
476 if (unlikely(r != 0)) {
477 radeon_wb_fini(rdev);
480 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
483 radeon_bo_unreserve(rdev->wb.wb_obj);
484 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
485 radeon_wb_fini(rdev);
488 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
489 radeon_bo_unreserve(rdev->wb.wb_obj);
491 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
492 radeon_wb_fini(rdev);
497 /* clear wb memory */
498 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
499 /* disable event_write fences */
500 rdev->wb.use_event = false;
501 /* disabled via module param */
502 if (radeon_no_wb == 1) {
503 rdev->wb.enabled = false;
505 if (rdev->flags & RADEON_IS_AGP) {
506 /* often unreliable on AGP */
507 rdev->wb.enabled = false;
508 } else if (rdev->family < CHIP_R300) {
509 /* often unreliable on pre-r300 */
510 rdev->wb.enabled = false;
512 rdev->wb.enabled = true;
513 /* event_write fences are only available on r600+ */
514 if (rdev->family >= CHIP_R600) {
515 rdev->wb.use_event = true;
519 /* always use writeback/events on NI, APUs */
520 if (rdev->family >= CHIP_PALM) {
521 rdev->wb.enabled = true;
522 rdev->wb.use_event = true;
525 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
531 * radeon_vram_location - try to find VRAM location
532 * @rdev: radeon device structure holding all necessary informations
533 * @mc: memory controller structure holding memory informations
534 * @base: base address at which to put VRAM
536 * Function will place try to place VRAM at base address provided
537 * as parameter (which is so far either PCI aperture address or
538 * for IGP TOM base address).
540 * If there is not enough space to fit the unvisible VRAM in the 32bits
541 * address space then we limit the VRAM size to the aperture.
543 * If we are using AGP and if the AGP aperture doesn't allow us to have
544 * room for all the VRAM than we restrict the VRAM to the PCI aperture
545 * size and print a warning.
547 * This function will never fails, worst case are limiting VRAM.
549 * Note: GTT start, end, size should be initialized before calling this
550 * function on AGP platform.
552 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
553 * this shouldn't be a problem as we are using the PCI aperture as a reference.
554 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
557 * Note: we use mc_vram_size as on some board we need to program the mc to
558 * cover the whole aperture even if VRAM size is inferior to aperture size
559 * Novell bug 204882 + along with lots of ubuntu ones
561 * Note: when limiting vram it's safe to overwritte real_vram_size because
562 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
563 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
566 * Note: IGP TOM addr should be the same as the aperture addr, we don't
567 * explicitly check for that thought.
569 * FIXME: when reducing VRAM size align new size on power of 2.
571 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
573 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
575 mc->vram_start = base;
576 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
577 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
578 mc->real_vram_size = mc->aper_size;
579 mc->mc_vram_size = mc->aper_size;
581 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
582 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
583 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
584 mc->real_vram_size = mc->aper_size;
585 mc->mc_vram_size = mc->aper_size;
587 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
588 if (limit && limit < mc->real_vram_size)
589 mc->real_vram_size = limit;
590 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
591 mc->mc_vram_size >> 20, mc->vram_start,
592 mc->vram_end, mc->real_vram_size >> 20);
596 * radeon_gtt_location - try to find GTT location
597 * @rdev: radeon device structure holding all necessary informations
598 * @mc: memory controller structure holding memory informations
600 * Function will place try to place GTT before or after VRAM.
602 * If GTT size is bigger than space left then we ajust GTT size.
603 * Thus function will never fails.
605 * FIXME: when reducing GTT size align new size on power of 2.
607 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
609 u64 size_af, size_bf;
611 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
612 size_bf = mc->vram_start & ~mc->gtt_base_align;
613 if (size_bf > size_af) {
614 if (mc->gtt_size > size_bf) {
615 dev_warn(rdev->dev, "limiting GTT\n");
616 mc->gtt_size = size_bf;
618 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
620 if (mc->gtt_size > size_af) {
621 dev_warn(rdev->dev, "limiting GTT\n");
622 mc->gtt_size = size_af;
624 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
626 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
627 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
628 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
632 * GPU helpers function.
636 * radeon_device_is_virtual - check if we are running is a virtual environment
638 * Check if the asic has been passed through to a VM (all asics).
639 * Used at driver startup.
640 * Returns true if virtual or false if not.
642 bool radeon_device_is_virtual(void)
645 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
652 * radeon_card_posted - check if the hw has already been initialized
654 * @rdev: radeon_device pointer
656 * Check if the asic has been initialized (all asics).
657 * Used at driver startup.
658 * Returns true if initialized or false if not.
660 bool radeon_card_posted(struct radeon_device *rdev)
664 /* for pass through, always force asic_init for CI */
665 if (rdev->family >= CHIP_BONAIRE &&
666 radeon_device_is_virtual())
669 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
670 if (efi_enabled(EFI_BOOT) &&
671 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
672 (rdev->family < CHIP_R600))
675 if (ASIC_IS_NODCE(rdev))
678 /* first check CRTCs */
679 if (ASIC_IS_DCE4(rdev)) {
680 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
681 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
682 if (rdev->num_crtc >= 4) {
683 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
684 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
686 if (rdev->num_crtc >= 6) {
687 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
688 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
690 if (reg & EVERGREEN_CRTC_MASTER_EN)
692 } else if (ASIC_IS_AVIVO(rdev)) {
693 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
694 RREG32(AVIVO_D2CRTC_CONTROL);
695 if (reg & AVIVO_CRTC_EN) {
699 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
700 RREG32(RADEON_CRTC2_GEN_CNTL);
701 if (reg & RADEON_CRTC_EN) {
707 /* then check MEM_SIZE, in case the crtcs are off */
708 if (rdev->family >= CHIP_R600)
709 reg = RREG32(R600_CONFIG_MEMSIZE);
711 reg = RREG32(RADEON_CONFIG_MEMSIZE);
721 * radeon_update_bandwidth_info - update display bandwidth params
723 * @rdev: radeon_device pointer
725 * Used when sclk/mclk are switched or display modes are set.
726 * params are used to calculate display watermarks (all asics)
728 void radeon_update_bandwidth_info(struct radeon_device *rdev)
731 u32 sclk = rdev->pm.current_sclk;
732 u32 mclk = rdev->pm.current_mclk;
734 /* sclk/mclk in Mhz */
735 a.full = dfixed_const(100);
736 rdev->pm.sclk.full = dfixed_const(sclk);
737 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
738 rdev->pm.mclk.full = dfixed_const(mclk);
739 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
741 if (rdev->flags & RADEON_IS_IGP) {
742 a.full = dfixed_const(16);
743 /* core_bandwidth = sclk(Mhz) * 16 */
744 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
749 * radeon_boot_test_post_card - check and possibly initialize the hw
751 * @rdev: radeon_device pointer
753 * Check if the asic is initialized and if not, attempt to initialize
755 * Returns true if initialized or false if not.
757 bool radeon_boot_test_post_card(struct radeon_device *rdev)
759 if (radeon_card_posted(rdev))
763 DRM_INFO("GPU not posted. posting now...\n");
764 if (rdev->is_atom_bios)
765 atom_asic_init(rdev->mode_info.atom_context);
767 radeon_combios_asic_init(rdev->ddev);
770 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
776 * radeon_dummy_page_init - init dummy page used by the driver
778 * @rdev: radeon_device pointer
780 * Allocate the dummy page used by the driver (all asics).
781 * This dummy page is used by the driver as a filler for gart entries
782 * when pages are taken out of the GART
783 * Returns 0 on sucess, -ENOMEM on failure.
785 int radeon_dummy_page_init(struct radeon_device *rdev)
787 if (rdev->dummy_page.page)
789 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
790 if (rdev->dummy_page.page == NULL)
792 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
793 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
794 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
795 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
796 __free_page(rdev->dummy_page.page);
797 rdev->dummy_page.page = NULL;
800 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
801 RADEON_GART_PAGE_DUMMY);
806 * radeon_dummy_page_fini - free dummy page used by the driver
808 * @rdev: radeon_device pointer
810 * Frees the dummy page used by the driver (all asics).
812 void radeon_dummy_page_fini(struct radeon_device *rdev)
814 if (rdev->dummy_page.page == NULL)
816 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
817 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
818 __free_page(rdev->dummy_page.page);
819 rdev->dummy_page.page = NULL;
823 /* ATOM accessor methods */
825 * ATOM is an interpreted byte code stored in tables in the vbios. The
826 * driver registers callbacks to access registers and the interpreter
827 * in the driver parses the tables and executes then to program specific
828 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
829 * atombios.h, and atom.c
833 * cail_pll_read - read PLL register
835 * @info: atom card_info pointer
836 * @reg: PLL register offset
838 * Provides a PLL register accessor for the atom interpreter (r4xx+).
839 * Returns the value of the PLL register.
841 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
843 struct radeon_device *rdev = info->dev->dev_private;
846 r = rdev->pll_rreg(rdev, reg);
851 * cail_pll_write - write PLL register
853 * @info: atom card_info pointer
854 * @reg: PLL register offset
855 * @val: value to write to the pll register
857 * Provides a PLL register accessor for the atom interpreter (r4xx+).
859 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
861 struct radeon_device *rdev = info->dev->dev_private;
863 rdev->pll_wreg(rdev, reg, val);
867 * cail_mc_read - read MC (Memory Controller) register
869 * @info: atom card_info pointer
870 * @reg: MC register offset
872 * Provides an MC register accessor for the atom interpreter (r4xx+).
873 * Returns the value of the MC register.
875 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
877 struct radeon_device *rdev = info->dev->dev_private;
880 r = rdev->mc_rreg(rdev, reg);
885 * cail_mc_write - write MC (Memory Controller) register
887 * @info: atom card_info pointer
888 * @reg: MC register offset
889 * @val: value to write to the pll register
891 * Provides a MC register accessor for the atom interpreter (r4xx+).
893 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
895 struct radeon_device *rdev = info->dev->dev_private;
897 rdev->mc_wreg(rdev, reg, val);
901 * cail_reg_write - write MMIO register
903 * @info: atom card_info pointer
904 * @reg: MMIO register offset
905 * @val: value to write to the pll register
907 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
909 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
911 struct radeon_device *rdev = info->dev->dev_private;
917 * cail_reg_read - read MMIO register
919 * @info: atom card_info pointer
920 * @reg: MMIO register offset
922 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
923 * Returns the value of the MMIO register.
925 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
927 struct radeon_device *rdev = info->dev->dev_private;
935 * cail_ioreg_write - write IO register
937 * @info: atom card_info pointer
938 * @reg: IO register offset
939 * @val: value to write to the pll register
941 * Provides a IO register accessor for the atom interpreter (r4xx+).
943 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
945 struct radeon_device *rdev = info->dev->dev_private;
947 WREG32_IO(reg*4, val);
951 * cail_ioreg_read - read IO register
953 * @info: atom card_info pointer
954 * @reg: IO register offset
956 * Provides an IO register accessor for the atom interpreter (r4xx+).
957 * Returns the value of the IO register.
959 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
961 struct radeon_device *rdev = info->dev->dev_private;
964 r = RREG32_IO(reg*4);
969 * radeon_atombios_init - init the driver info and callbacks for atombios
971 * @rdev: radeon_device pointer
973 * Initializes the driver info and register access callbacks for the
974 * ATOM interpreter (r4xx+).
975 * Returns 0 on sucess, -ENOMEM on failure.
976 * Called at driver startup.
978 int radeon_atombios_init(struct radeon_device *rdev)
980 struct card_info *atom_card_info =
981 kzalloc(sizeof(struct card_info), GFP_KERNEL);
986 rdev->mode_info.atom_card_info = atom_card_info;
987 atom_card_info->dev = rdev->ddev;
988 atom_card_info->reg_read = cail_reg_read;
989 atom_card_info->reg_write = cail_reg_write;
990 /* needed for iio ops */
992 atom_card_info->ioreg_read = cail_ioreg_read;
993 atom_card_info->ioreg_write = cail_ioreg_write;
995 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
996 atom_card_info->ioreg_read = cail_reg_read;
997 atom_card_info->ioreg_write = cail_reg_write;
999 atom_card_info->mc_read = cail_mc_read;
1000 atom_card_info->mc_write = cail_mc_write;
1001 atom_card_info->pll_read = cail_pll_read;
1002 atom_card_info->pll_write = cail_pll_write;
1004 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1005 if (!rdev->mode_info.atom_context) {
1006 radeon_atombios_fini(rdev);
1010 mutex_init(&rdev->mode_info.atom_context->mutex);
1011 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1012 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1013 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1018 * radeon_atombios_fini - free the driver info and callbacks for atombios
1020 * @rdev: radeon_device pointer
1022 * Frees the driver info and register access callbacks for the ATOM
1023 * interpreter (r4xx+).
1024 * Called at driver shutdown.
1026 void radeon_atombios_fini(struct radeon_device *rdev)
1028 if (rdev->mode_info.atom_context) {
1029 kfree(rdev->mode_info.atom_context->scratch);
1031 kfree(rdev->mode_info.atom_context);
1032 rdev->mode_info.atom_context = NULL;
1033 kfree(rdev->mode_info.atom_card_info);
1034 rdev->mode_info.atom_card_info = NULL;
1039 * COMBIOS is the bios format prior to ATOM. It provides
1040 * command tables similar to ATOM, but doesn't have a unified
1041 * parser. See radeon_combios.c
1045 * radeon_combios_init - init the driver info for combios
1047 * @rdev: radeon_device pointer
1049 * Initializes the driver info for combios (r1xx-r3xx).
1050 * Returns 0 on sucess.
1051 * Called at driver startup.
1053 int radeon_combios_init(struct radeon_device *rdev)
1055 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1060 * radeon_combios_fini - free the driver info for combios
1062 * @rdev: radeon_device pointer
1064 * Frees the driver info for combios (r1xx-r3xx).
1065 * Called at driver shutdown.
1067 void radeon_combios_fini(struct radeon_device *rdev)
1071 /* if we get transitioned to only one device, take VGA back */
1073 * radeon_vga_set_decode - enable/disable vga decode
1075 * @cookie: radeon_device pointer
1076 * @state: enable/disable vga decode
1078 * Enable/disable vga decode (all asics).
1079 * Returns VGA resource flags.
1081 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1083 struct radeon_device *rdev = cookie;
1084 radeon_vga_set_state(rdev, state);
1086 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1087 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1089 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1093 * radeon_check_pot_argument - check that argument is a power of two
1095 * @arg: value to check
1097 * Validates that a certain argument is a power of two (all asics).
1098 * Returns true if argument is valid.
1100 static bool radeon_check_pot_argument(int arg)
1102 return (arg & (arg - 1)) == 0;
1106 * Determine a sensible default GART size according to ASIC family.
1108 * @family ASIC family name
1110 static int radeon_gart_size_auto(enum radeon_family family)
1112 /* default to a larger gart size on newer asics */
1113 if (family >= CHIP_TAHITI)
1115 else if (family >= CHIP_RV770)
1122 * radeon_check_arguments - validate module params
1124 * @rdev: radeon_device pointer
1126 * Validates certain module parameters and updates
1127 * the associated values used by the driver (all asics).
1129 static void radeon_check_arguments(struct radeon_device *rdev)
1131 /* vramlimit must be a power of two */
1132 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1133 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1135 radeon_vram_limit = 0;
1138 if (radeon_gart_size == -1) {
1139 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1141 /* gtt size must be power of two and greater or equal to 32M */
1142 if (radeon_gart_size < 32) {
1143 dev_warn(rdev->dev, "gart size (%d) too small\n",
1145 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1146 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1147 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1149 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1151 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1153 /* AGP mode can only be -1, 1, 2, 4, 8 */
1154 switch (radeon_agpmode) {
1163 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1164 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1169 if (!radeon_check_pot_argument(radeon_vm_size)) {
1170 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1175 if (radeon_vm_size < 1) {
1176 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1182 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1184 if (radeon_vm_size > 1024) {
1185 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1190 /* defines number of bits in page table versus page directory,
1191 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1192 * page table and the remaining bits are in the page directory */
1193 if (radeon_vm_block_size == -1) {
1195 /* Total bits covered by PD + PTs */
1196 unsigned bits = ilog2(radeon_vm_size) + 18;
1198 /* Make sure the PD is 4K in size up to 8GB address space.
1199 Above that split equal between PD and PTs */
1200 if (radeon_vm_size <= 8)
1201 radeon_vm_block_size = bits - 9;
1203 radeon_vm_block_size = (bits + 3) / 2;
1205 } else if (radeon_vm_block_size < 9) {
1206 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1207 radeon_vm_block_size);
1208 radeon_vm_block_size = 9;
1211 if (radeon_vm_block_size > 24 ||
1212 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1213 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1214 radeon_vm_block_size);
1215 radeon_vm_block_size = 9;
1220 * radeon_switcheroo_set_state - set switcheroo state
1222 * @pdev: pci dev pointer
1223 * @state: vga_switcheroo state
1225 * Callback for the switcheroo driver. Suspends or resumes the
1226 * the asics before or after it is powered up using ACPI methods.
1228 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1230 struct drm_device *dev = pci_get_drvdata(pdev);
1231 struct radeon_device *rdev = dev->dev_private;
1233 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1236 if (state == VGA_SWITCHEROO_ON) {
1237 unsigned d3_delay = dev->pdev->d3_delay;
1239 printk(KERN_INFO "radeon: switched on\n");
1240 /* don't suspend or resume card normally */
1241 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1243 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1244 dev->pdev->d3_delay = 20;
1246 radeon_resume_kms(dev, true, true);
1248 dev->pdev->d3_delay = d3_delay;
1250 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1251 drm_kms_helper_poll_enable(dev);
1253 printk(KERN_INFO "radeon: switched off\n");
1254 drm_kms_helper_poll_disable(dev);
1255 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1256 radeon_suspend_kms(dev, true, true, false);
1257 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1262 * radeon_switcheroo_can_switch - see if switcheroo state can change
1264 * @pdev: pci dev pointer
1266 * Callback for the switcheroo driver. Check of the switcheroo
1267 * state can be changed.
1268 * Returns true if the state can be changed, false if not.
1270 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1272 struct drm_device *dev = pci_get_drvdata(pdev);
1275 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1276 * locking inversion with the driver load path. And the access here is
1277 * completely racy anyway. So don't bother with locking for now.
1279 return dev->open_count == 0;
1282 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1283 .set_gpu_state = radeon_switcheroo_set_state,
1285 .can_switch = radeon_switcheroo_can_switch,
1289 * radeon_device_init - initialize the driver
1291 * @rdev: radeon_device pointer
1292 * @pdev: drm dev pointer
1293 * @pdev: pci dev pointer
1294 * @flags: driver flags
1296 * Initializes the driver info and hw (all asics).
1297 * Returns 0 for success or an error on failure.
1298 * Called at driver startup.
1300 int radeon_device_init(struct radeon_device *rdev,
1301 struct drm_device *ddev,
1302 struct pci_dev *pdev,
1307 bool runtime = false;
1309 rdev->shutdown = false;
1310 rdev->dev = &pdev->dev;
1313 rdev->flags = flags;
1314 rdev->family = flags & RADEON_FAMILY_MASK;
1315 rdev->is_atom_bios = false;
1316 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1317 rdev->mc.gtt_size = 512 * 1024 * 1024;
1318 rdev->accel_working = false;
1319 /* set up ring ids */
1320 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1321 rdev->ring[i].idx = i;
1323 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1325 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1326 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1327 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1329 /* mutex initialization are all done here so we
1330 * can recall function without having locking issues */
1331 mutex_init(&rdev->ring_lock);
1332 mutex_init(&rdev->dc_hw_i2c_mutex);
1333 atomic_set(&rdev->ih.lock, 0);
1334 mutex_init(&rdev->gem.mutex);
1335 mutex_init(&rdev->pm.mutex);
1336 mutex_init(&rdev->gpu_clock_mutex);
1337 mutex_init(&rdev->srbm_mutex);
1338 mutex_init(&rdev->grbm_idx_mutex);
1339 init_rwsem(&rdev->pm.mclk_lock);
1340 init_rwsem(&rdev->exclusive_lock);
1341 init_waitqueue_head(&rdev->irq.vblank_queue);
1342 mutex_init(&rdev->mn_lock);
1343 hash_init(rdev->mn_hash);
1344 r = radeon_gem_init(rdev);
1348 radeon_check_arguments(rdev);
1349 /* Adjust VM size here.
1350 * Max GPUVM size for cayman+ is 40 bits.
1352 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1354 /* Set asic functions */
1355 r = radeon_asic_init(rdev);
1359 /* all of the newer IGP chips have an internal gart
1360 * However some rs4xx report as AGP, so remove that here.
1362 if ((rdev->family >= CHIP_RS400) &&
1363 (rdev->flags & RADEON_IS_IGP)) {
1364 rdev->flags &= ~RADEON_IS_AGP;
1367 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1368 radeon_agp_disable(rdev);
1371 /* Set the internal MC address mask
1372 * This is the max address of the GPU's
1373 * internal address space.
1375 if (rdev->family >= CHIP_CAYMAN)
1376 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1377 else if (rdev->family >= CHIP_CEDAR)
1378 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1380 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1382 /* set DMA mask + need_dma32 flags.
1383 * PCIE - can handle 40-bits.
1384 * IGP - can handle 40-bits
1385 * AGP - generally dma32 is safest
1386 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1388 rdev->need_dma32 = false;
1389 if (rdev->flags & RADEON_IS_AGP)
1390 rdev->need_dma32 = true;
1391 if ((rdev->flags & RADEON_IS_PCI) &&
1392 (rdev->family <= CHIP_RS740))
1393 rdev->need_dma32 = true;
1395 dma_bits = rdev->need_dma32 ? 32 : 40;
1396 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1398 rdev->need_dma32 = true;
1400 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1402 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1404 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1405 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1408 /* Registers mapping */
1409 /* TODO: block userspace mapping of io register */
1410 spin_lock_init(&rdev->mmio_idx_lock);
1411 spin_lock_init(&rdev->smc_idx_lock);
1412 spin_lock_init(&rdev->pll_idx_lock);
1413 spin_lock_init(&rdev->mc_idx_lock);
1414 spin_lock_init(&rdev->pcie_idx_lock);
1415 spin_lock_init(&rdev->pciep_idx_lock);
1416 spin_lock_init(&rdev->pif_idx_lock);
1417 spin_lock_init(&rdev->cg_idx_lock);
1418 spin_lock_init(&rdev->uvd_idx_lock);
1419 spin_lock_init(&rdev->rcu_idx_lock);
1420 spin_lock_init(&rdev->didt_idx_lock);
1421 spin_lock_init(&rdev->end_idx_lock);
1422 if (rdev->family >= CHIP_BONAIRE) {
1423 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1424 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1426 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1427 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1429 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1430 if (rdev->rmmio == NULL) {
1433 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1434 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1436 /* doorbell bar mapping */
1437 if (rdev->family >= CHIP_BONAIRE)
1438 radeon_doorbell_init(rdev);
1440 /* io port mapping */
1441 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1442 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1443 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1444 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1448 if (rdev->rio_mem == NULL)
1449 DRM_ERROR("Unable to find PCI I/O BAR\n");
1451 if (rdev->flags & RADEON_IS_PX)
1452 radeon_device_handle_px_quirks(rdev);
1454 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1455 /* this will fail for cards that aren't VGA class devices, just
1457 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1459 if (rdev->flags & RADEON_IS_PX)
1461 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1463 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1465 r = radeon_init(rdev);
1469 r = radeon_gem_debugfs_init(rdev);
1471 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1474 r = radeon_mst_debugfs_init(rdev);
1476 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1479 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1480 /* Acceleration not working on AGP card try again
1481 * with fallback to PCI or PCIE GART
1483 radeon_asic_reset(rdev);
1485 radeon_agp_disable(rdev);
1486 r = radeon_init(rdev);
1491 r = radeon_ib_ring_tests(rdev);
1493 DRM_ERROR("ib ring test failed (%d).\n", r);
1496 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1497 * after the CP ring have chew one packet at least. Hence here we stop
1498 * and restart DPM after the radeon_ib_ring_tests().
1500 if (rdev->pm.dpm_enabled &&
1501 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1502 (rdev->family == CHIP_TURKS) &&
1503 (rdev->flags & RADEON_IS_MOBILITY)) {
1504 mutex_lock(&rdev->pm.mutex);
1505 radeon_dpm_disable(rdev);
1506 radeon_dpm_enable(rdev);
1507 mutex_unlock(&rdev->pm.mutex);
1510 if ((radeon_testing & 1)) {
1511 if (rdev->accel_working)
1512 radeon_test_moves(rdev);
1514 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1516 if ((radeon_testing & 2)) {
1517 if (rdev->accel_working)
1518 radeon_test_syncing(rdev);
1520 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1522 if (radeon_benchmarking) {
1523 if (rdev->accel_working)
1524 radeon_benchmark(rdev, radeon_benchmarking);
1526 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1531 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1532 if (radeon_is_px(ddev))
1533 pm_runtime_put_noidle(ddev->dev);
1535 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1539 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1542 * radeon_device_fini - tear down the driver
1544 * @rdev: radeon_device pointer
1546 * Tear down the driver info (all asics).
1547 * Called at driver shutdown.
1549 void radeon_device_fini(struct radeon_device *rdev)
1551 DRM_INFO("radeon: finishing device.\n");
1552 rdev->shutdown = true;
1553 /* evict vram memory */
1554 radeon_bo_evict_vram(rdev);
1556 vga_switcheroo_unregister_client(rdev->pdev);
1557 if (rdev->flags & RADEON_IS_PX)
1558 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1559 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1561 pci_iounmap(rdev->pdev, rdev->rio_mem);
1562 rdev->rio_mem = NULL;
1563 iounmap(rdev->rmmio);
1565 if (rdev->family >= CHIP_BONAIRE)
1566 radeon_doorbell_fini(rdev);
1567 radeon_debugfs_remove_files(rdev);
1575 * radeon_suspend_kms - initiate device suspend
1577 * @pdev: drm dev pointer
1578 * @state: suspend state
1580 * Puts the hw in the suspend state (all asics).
1581 * Returns 0 for success or an error on failure.
1582 * Called at driver suspend.
1584 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1585 bool fbcon, bool freeze)
1587 struct radeon_device *rdev;
1588 struct drm_crtc *crtc;
1589 struct drm_connector *connector;
1592 if (dev == NULL || dev->dev_private == NULL) {
1596 rdev = dev->dev_private;
1598 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1601 drm_kms_helper_poll_disable(dev);
1603 drm_modeset_lock_all(dev);
1604 /* turn off display hw */
1605 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1606 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1608 drm_modeset_unlock_all(dev);
1610 /* unpin the front buffers and cursors */
1611 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1612 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1613 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1614 struct radeon_bo *robj;
1616 if (radeon_crtc->cursor_bo) {
1617 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1618 r = radeon_bo_reserve(robj, false);
1620 radeon_bo_unpin(robj);
1621 radeon_bo_unreserve(robj);
1625 if (rfb == NULL || rfb->obj == NULL) {
1628 robj = gem_to_radeon_bo(rfb->obj);
1629 /* don't unpin kernel fb objects */
1630 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1631 r = radeon_bo_reserve(robj, false);
1633 radeon_bo_unpin(robj);
1634 radeon_bo_unreserve(robj);
1638 /* evict vram memory */
1639 radeon_bo_evict_vram(rdev);
1641 /* wait for gpu to finish processing current batch */
1642 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1643 r = radeon_fence_wait_empty(rdev, i);
1645 /* delay GPU reset to resume */
1646 radeon_fence_driver_force_completion(rdev, i);
1650 radeon_save_bios_scratch_regs(rdev);
1652 radeon_suspend(rdev);
1653 radeon_hpd_fini(rdev);
1654 /* evict remaining vram memory */
1655 radeon_bo_evict_vram(rdev);
1657 radeon_agp_suspend(rdev);
1659 pci_save_state(dev->pdev);
1660 if (freeze && rdev->family >= CHIP_CEDAR) {
1661 rdev->asic->asic_reset(rdev, true);
1662 pci_restore_state(dev->pdev);
1663 } else if (suspend) {
1664 /* Shut down the device */
1665 pci_disable_device(dev->pdev);
1666 pci_set_power_state(dev->pdev, PCI_D3hot);
1671 radeon_fbdev_set_suspend(rdev, 1);
1678 * radeon_resume_kms - initiate device resume
1680 * @pdev: drm dev pointer
1682 * Bring the hw back to operating state (all asics).
1683 * Returns 0 for success or an error on failure.
1684 * Called at driver resume.
1686 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1688 struct drm_connector *connector;
1689 struct radeon_device *rdev = dev->dev_private;
1690 struct drm_crtc *crtc;
1693 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1700 pci_set_power_state(dev->pdev, PCI_D0);
1701 pci_restore_state(dev->pdev);
1702 if (pci_enable_device(dev->pdev)) {
1708 /* resume AGP if in use */
1709 radeon_agp_resume(rdev);
1710 radeon_resume(rdev);
1712 r = radeon_ib_ring_tests(rdev);
1714 DRM_ERROR("ib ring test failed (%d).\n", r);
1716 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1717 /* do dpm late init */
1718 r = radeon_pm_late_init(rdev);
1720 rdev->pm.dpm_enabled = false;
1721 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1724 /* resume old pm late */
1725 radeon_pm_resume(rdev);
1728 radeon_restore_bios_scratch_regs(rdev);
1731 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1732 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1734 if (radeon_crtc->cursor_bo) {
1735 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1736 r = radeon_bo_reserve(robj, false);
1738 /* Only 27 bit offset for legacy cursor */
1739 r = radeon_bo_pin_restricted(robj,
1740 RADEON_GEM_DOMAIN_VRAM,
1741 ASIC_IS_AVIVO(rdev) ?
1743 &radeon_crtc->cursor_addr);
1745 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1746 radeon_bo_unreserve(robj);
1751 /* init dig PHYs, disp eng pll */
1752 if (rdev->is_atom_bios) {
1753 radeon_atom_encoder_init(rdev);
1754 radeon_atom_disp_eng_pll_init(rdev);
1755 /* turn on the BL */
1756 if (rdev->mode_info.bl_encoder) {
1757 u8 bl_level = radeon_get_backlight_level(rdev,
1758 rdev->mode_info.bl_encoder);
1759 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1763 /* reset hpd state */
1764 radeon_hpd_init(rdev);
1765 /* blat the mode back in */
1767 drm_helper_resume_force_mode(dev);
1768 /* turn on display hw */
1769 drm_modeset_lock_all(dev);
1770 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1771 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1773 drm_modeset_unlock_all(dev);
1776 drm_kms_helper_poll_enable(dev);
1778 /* set the power state here in case we are a PX system or headless */
1779 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1780 radeon_pm_compute_clocks(rdev);
1783 radeon_fbdev_set_suspend(rdev, 0);
1791 * radeon_gpu_reset - reset the asic
1793 * @rdev: radeon device pointer
1795 * Attempt the reset the GPU if it has hung (all asics).
1796 * Returns 0 for success or an error on failure.
1798 int radeon_gpu_reset(struct radeon_device *rdev)
1800 unsigned ring_sizes[RADEON_NUM_RINGS];
1801 uint32_t *ring_data[RADEON_NUM_RINGS];
1808 down_write(&rdev->exclusive_lock);
1810 if (!rdev->needs_reset) {
1811 up_write(&rdev->exclusive_lock);
1815 atomic_inc(&rdev->gpu_reset_counter);
1817 radeon_save_bios_scratch_regs(rdev);
1819 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1820 radeon_suspend(rdev);
1821 radeon_hpd_fini(rdev);
1823 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1824 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1826 if (ring_sizes[i]) {
1828 dev_info(rdev->dev, "Saved %d dwords of commands "
1829 "on ring %d.\n", ring_sizes[i], i);
1833 r = radeon_asic_reset(rdev);
1835 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1836 radeon_resume(rdev);
1839 radeon_restore_bios_scratch_regs(rdev);
1841 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1842 if (!r && ring_data[i]) {
1843 radeon_ring_restore(rdev, &rdev->ring[i],
1844 ring_sizes[i], ring_data[i]);
1846 radeon_fence_driver_force_completion(rdev, i);
1847 kfree(ring_data[i]);
1851 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1852 /* do dpm late init */
1853 r = radeon_pm_late_init(rdev);
1855 rdev->pm.dpm_enabled = false;
1856 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1859 /* resume old pm late */
1860 radeon_pm_resume(rdev);
1863 /* init dig PHYs, disp eng pll */
1864 if (rdev->is_atom_bios) {
1865 radeon_atom_encoder_init(rdev);
1866 radeon_atom_disp_eng_pll_init(rdev);
1867 /* turn on the BL */
1868 if (rdev->mode_info.bl_encoder) {
1869 u8 bl_level = radeon_get_backlight_level(rdev,
1870 rdev->mode_info.bl_encoder);
1871 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1875 /* reset hpd state */
1876 radeon_hpd_init(rdev);
1878 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1880 rdev->in_reset = true;
1881 rdev->needs_reset = false;
1883 downgrade_write(&rdev->exclusive_lock);
1885 drm_helper_resume_force_mode(rdev->ddev);
1887 /* set the power state here in case we are a PX system or headless */
1888 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1889 radeon_pm_compute_clocks(rdev);
1892 r = radeon_ib_ring_tests(rdev);
1896 /* bad news, how to tell it to userspace ? */
1897 dev_info(rdev->dev, "GPU reset failed\n");
1900 rdev->needs_reset = r == -EAGAIN;
1901 rdev->in_reset = false;
1903 up_read(&rdev->exclusive_lock);
1911 int radeon_debugfs_add_files(struct radeon_device *rdev,
1912 struct drm_info_list *files,
1917 for (i = 0; i < rdev->debugfs_count; i++) {
1918 if (rdev->debugfs[i].files == files) {
1919 /* Already registered */
1924 i = rdev->debugfs_count + 1;
1925 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1926 DRM_ERROR("Reached maximum number of debugfs components.\n");
1927 DRM_ERROR("Report so we increase "
1928 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1931 rdev->debugfs[rdev->debugfs_count].files = files;
1932 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1933 rdev->debugfs_count = i;
1934 #if defined(CONFIG_DEBUG_FS)
1935 drm_debugfs_create_files(files, nfiles,
1936 rdev->ddev->control->debugfs_root,
1937 rdev->ddev->control);
1938 drm_debugfs_create_files(files, nfiles,
1939 rdev->ddev->primary->debugfs_root,
1940 rdev->ddev->primary);
1945 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1947 #if defined(CONFIG_DEBUG_FS)
1950 for (i = 0; i < rdev->debugfs_count; i++) {
1951 drm_debugfs_remove_files(rdev->debugfs[i].files,
1952 rdev->debugfs[i].num_files,
1953 rdev->ddev->control);
1954 drm_debugfs_remove_files(rdev->debugfs[i].files,
1955 rdev->debugfs[i].num_files,
1956 rdev->ddev->primary);