2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
101 * radeon_surface_init - Clear GPU surface registers.
103 * @rdev: radeon_device pointer
105 * Clear GPU surface registers (r1xx-r5xx).
107 void radeon_surface_init(struct radeon_device *rdev)
109 /* FIXME: check this out */
110 if (rdev->family < CHIP_R600) {
113 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
114 if (rdev->surface_regs[i].bo)
115 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
117 radeon_clear_surface_reg(rdev, i);
119 /* enable surfaces */
120 WREG32(RADEON_SURFACE_CNTL, 0);
125 * GPU scratch registers helpers function.
128 * radeon_scratch_init - Init scratch register driver information.
130 * @rdev: radeon_device pointer
132 * Init CP scratch register driver information (r1xx-r5xx)
134 void radeon_scratch_init(struct radeon_device *rdev)
138 /* FIXME: check this out */
139 if (rdev->family < CHIP_R300) {
140 rdev->scratch.num_reg = 5;
142 rdev->scratch.num_reg = 7;
144 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
145 for (i = 0; i < rdev->scratch.num_reg; i++) {
146 rdev->scratch.free[i] = true;
147 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
152 * radeon_scratch_get - Allocate a scratch register
154 * @rdev: radeon_device pointer
155 * @reg: scratch register mmio offset
157 * Allocate a CP scratch register for use by the driver (all asics).
158 * Returns 0 on success or -EINVAL on failure.
160 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
164 for (i = 0; i < rdev->scratch.num_reg; i++) {
165 if (rdev->scratch.free[i]) {
166 rdev->scratch.free[i] = false;
167 *reg = rdev->scratch.reg[i];
175 * radeon_scratch_free - Free a scratch register
177 * @rdev: radeon_device pointer
178 * @reg: scratch register mmio offset
180 * Free a CP scratch register allocated for use by the driver (all asics)
182 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
186 for (i = 0; i < rdev->scratch.num_reg; i++) {
187 if (rdev->scratch.reg[i] == reg) {
188 rdev->scratch.free[i] = true;
196 * Writeback is the the method by which the the GPU updates special pages
197 * in memory with the status of certain GPU events (fences, ring pointers,
202 * radeon_wb_disable - Disable Writeback
204 * @rdev: radeon_device pointer
206 * Disables Writeback (all asics). Used for suspend.
208 void radeon_wb_disable(struct radeon_device *rdev)
212 if (rdev->wb.wb_obj) {
213 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
214 if (unlikely(r != 0))
216 radeon_bo_kunmap(rdev->wb.wb_obj);
217 radeon_bo_unpin(rdev->wb.wb_obj);
218 radeon_bo_unreserve(rdev->wb.wb_obj);
220 rdev->wb.enabled = false;
224 * radeon_wb_fini - Disable Writeback and free memory
226 * @rdev: radeon_device pointer
228 * Disables Writeback and frees the Writeback memory (all asics).
229 * Used at driver shutdown.
231 void radeon_wb_fini(struct radeon_device *rdev)
233 radeon_wb_disable(rdev);
234 if (rdev->wb.wb_obj) {
235 radeon_bo_unref(&rdev->wb.wb_obj);
237 rdev->wb.wb_obj = NULL;
242 * radeon_wb_init- Init Writeback driver info and allocate memory
244 * @rdev: radeon_device pointer
246 * Disables Writeback and frees the Writeback memory (all asics).
247 * Used at driver startup.
248 * Returns 0 on success or an -error on failure.
250 int radeon_wb_init(struct radeon_device *rdev)
254 if (rdev->wb.wb_obj == NULL) {
255 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
256 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
258 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
262 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
263 if (unlikely(r != 0)) {
264 radeon_wb_fini(rdev);
267 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
270 radeon_bo_unreserve(rdev->wb.wb_obj);
271 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
272 radeon_wb_fini(rdev);
275 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
276 radeon_bo_unreserve(rdev->wb.wb_obj);
278 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
279 radeon_wb_fini(rdev);
283 /* clear wb memory */
284 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
285 /* disable event_write fences */
286 rdev->wb.use_event = false;
287 /* disabled via module param */
288 if (radeon_no_wb == 1) {
289 rdev->wb.enabled = false;
291 if (rdev->flags & RADEON_IS_AGP) {
292 /* often unreliable on AGP */
293 rdev->wb.enabled = false;
294 } else if (rdev->family < CHIP_R300) {
295 /* often unreliable on pre-r300 */
296 rdev->wb.enabled = false;
298 rdev->wb.enabled = true;
299 /* event_write fences are only available on r600+ */
300 if (rdev->family >= CHIP_R600) {
301 rdev->wb.use_event = true;
305 /* always use writeback/events on NI, APUs */
306 if (rdev->family >= CHIP_PALM) {
307 rdev->wb.enabled = true;
308 rdev->wb.use_event = true;
311 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
317 * radeon_vram_location - try to find VRAM location
318 * @rdev: radeon device structure holding all necessary informations
319 * @mc: memory controller structure holding memory informations
320 * @base: base address at which to put VRAM
322 * Function will place try to place VRAM at base address provided
323 * as parameter (which is so far either PCI aperture address or
324 * for IGP TOM base address).
326 * If there is not enough space to fit the unvisible VRAM in the 32bits
327 * address space then we limit the VRAM size to the aperture.
329 * If we are using AGP and if the AGP aperture doesn't allow us to have
330 * room for all the VRAM than we restrict the VRAM to the PCI aperture
331 * size and print a warning.
333 * This function will never fails, worst case are limiting VRAM.
335 * Note: GTT start, end, size should be initialized before calling this
336 * function on AGP platform.
338 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
339 * this shouldn't be a problem as we are using the PCI aperture as a reference.
340 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
343 * Note: we use mc_vram_size as on some board we need to program the mc to
344 * cover the whole aperture even if VRAM size is inferior to aperture size
345 * Novell bug 204882 + along with lots of ubuntu ones
347 * Note: when limiting vram it's safe to overwritte real_vram_size because
348 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
349 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
352 * Note: IGP TOM addr should be the same as the aperture addr, we don't
353 * explicitly check for that thought.
355 * FIXME: when reducing VRAM size align new size on power of 2.
357 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
361 mc->vram_start = base;
362 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size;
367 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
368 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
369 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
370 mc->real_vram_size = mc->aper_size;
371 mc->mc_vram_size = mc->aper_size;
373 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
374 if (limit && limit < mc->real_vram_size)
375 mc->real_vram_size = limit;
376 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
377 mc->mc_vram_size >> 20, mc->vram_start,
378 mc->vram_end, mc->real_vram_size >> 20);
382 * radeon_gtt_location - try to find GTT location
383 * @rdev: radeon device structure holding all necessary informations
384 * @mc: memory controller structure holding memory informations
386 * Function will place try to place GTT before or after VRAM.
388 * If GTT size is bigger than space left then we ajust GTT size.
389 * Thus function will never fails.
391 * FIXME: when reducing GTT size align new size on power of 2.
393 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
395 u64 size_af, size_bf;
397 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) {
401 dev_warn(rdev->dev, "limiting GTT\n");
402 mc->gtt_size = size_bf;
404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
406 if (mc->gtt_size > size_af) {
407 dev_warn(rdev->dev, "limiting GTT\n");
408 mc->gtt_size = size_af;
410 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
412 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
413 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
414 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
418 * GPU helpers function.
421 * radeon_card_posted - check if the hw has already been initialized
423 * @rdev: radeon_device pointer
425 * Check if the asic has been initialized (all asics).
426 * Used at driver startup.
427 * Returns true if initialized or false if not.
429 bool radeon_card_posted(struct radeon_device *rdev)
433 if (efi_enabled(EFI_BOOT) &&
434 rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
437 /* first check CRTCs */
438 if (ASIC_IS_DCE41(rdev)) {
439 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
440 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
441 if (reg & EVERGREEN_CRTC_MASTER_EN)
443 } else if (ASIC_IS_DCE4(rdev)) {
444 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
445 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
446 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
450 if (reg & EVERGREEN_CRTC_MASTER_EN)
452 } else if (ASIC_IS_AVIVO(rdev)) {
453 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
454 RREG32(AVIVO_D2CRTC_CONTROL);
455 if (reg & AVIVO_CRTC_EN) {
459 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
460 RREG32(RADEON_CRTC2_GEN_CNTL);
461 if (reg & RADEON_CRTC_EN) {
466 /* then check MEM_SIZE, in case the crtcs are off */
467 if (rdev->family >= CHIP_R600)
468 reg = RREG32(R600_CONFIG_MEMSIZE);
470 reg = RREG32(RADEON_CONFIG_MEMSIZE);
480 * radeon_update_bandwidth_info - update display bandwidth params
482 * @rdev: radeon_device pointer
484 * Used when sclk/mclk are switched or display modes are set.
485 * params are used to calculate display watermarks (all asics)
487 void radeon_update_bandwidth_info(struct radeon_device *rdev)
490 u32 sclk = rdev->pm.current_sclk;
491 u32 mclk = rdev->pm.current_mclk;
493 /* sclk/mclk in Mhz */
494 a.full = dfixed_const(100);
495 rdev->pm.sclk.full = dfixed_const(sclk);
496 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
497 rdev->pm.mclk.full = dfixed_const(mclk);
498 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
500 if (rdev->flags & RADEON_IS_IGP) {
501 a.full = dfixed_const(16);
502 /* core_bandwidth = sclk(Mhz) * 16 */
503 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
508 * radeon_boot_test_post_card - check and possibly initialize the hw
510 * @rdev: radeon_device pointer
512 * Check if the asic is initialized and if not, attempt to initialize
514 * Returns true if initialized or false if not.
516 bool radeon_boot_test_post_card(struct radeon_device *rdev)
518 if (radeon_card_posted(rdev))
522 DRM_INFO("GPU not posted. posting now...\n");
523 if (rdev->is_atom_bios)
524 atom_asic_init(rdev->mode_info.atom_context);
526 radeon_combios_asic_init(rdev->ddev);
529 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
535 * radeon_dummy_page_init - init dummy page used by the driver
537 * @rdev: radeon_device pointer
539 * Allocate the dummy page used by the driver (all asics).
540 * This dummy page is used by the driver as a filler for gart entries
541 * when pages are taken out of the GART
542 * Returns 0 on sucess, -ENOMEM on failure.
544 int radeon_dummy_page_init(struct radeon_device *rdev)
546 if (rdev->dummy_page.page)
548 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
549 if (rdev->dummy_page.page == NULL)
551 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
552 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
553 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
554 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
555 __free_page(rdev->dummy_page.page);
556 rdev->dummy_page.page = NULL;
563 * radeon_dummy_page_fini - free dummy page used by the driver
565 * @rdev: radeon_device pointer
567 * Frees the dummy page used by the driver (all asics).
569 void radeon_dummy_page_fini(struct radeon_device *rdev)
571 if (rdev->dummy_page.page == NULL)
573 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
574 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
575 __free_page(rdev->dummy_page.page);
576 rdev->dummy_page.page = NULL;
580 /* ATOM accessor methods */
582 * ATOM is an interpreted byte code stored in tables in the vbios. The
583 * driver registers callbacks to access registers and the interpreter
584 * in the driver parses the tables and executes then to program specific
585 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
586 * atombios.h, and atom.c
590 * cail_pll_read - read PLL register
592 * @info: atom card_info pointer
593 * @reg: PLL register offset
595 * Provides a PLL register accessor for the atom interpreter (r4xx+).
596 * Returns the value of the PLL register.
598 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
600 struct radeon_device *rdev = info->dev->dev_private;
603 r = rdev->pll_rreg(rdev, reg);
608 * cail_pll_write - write PLL register
610 * @info: atom card_info pointer
611 * @reg: PLL register offset
612 * @val: value to write to the pll register
614 * Provides a PLL register accessor for the atom interpreter (r4xx+).
616 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
618 struct radeon_device *rdev = info->dev->dev_private;
620 rdev->pll_wreg(rdev, reg, val);
624 * cail_mc_read - read MC (Memory Controller) register
626 * @info: atom card_info pointer
627 * @reg: MC register offset
629 * Provides an MC register accessor for the atom interpreter (r4xx+).
630 * Returns the value of the MC register.
632 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
634 struct radeon_device *rdev = info->dev->dev_private;
637 r = rdev->mc_rreg(rdev, reg);
642 * cail_mc_write - write MC (Memory Controller) register
644 * @info: atom card_info pointer
645 * @reg: MC register offset
646 * @val: value to write to the pll register
648 * Provides a MC register accessor for the atom interpreter (r4xx+).
650 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
652 struct radeon_device *rdev = info->dev->dev_private;
654 rdev->mc_wreg(rdev, reg, val);
658 * cail_reg_write - write MMIO register
660 * @info: atom card_info pointer
661 * @reg: MMIO register offset
662 * @val: value to write to the pll register
664 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
666 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
668 struct radeon_device *rdev = info->dev->dev_private;
674 * cail_reg_read - read MMIO register
676 * @info: atom card_info pointer
677 * @reg: MMIO register offset
679 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
680 * Returns the value of the MMIO register.
682 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
684 struct radeon_device *rdev = info->dev->dev_private;
692 * cail_ioreg_write - write IO register
694 * @info: atom card_info pointer
695 * @reg: IO register offset
696 * @val: value to write to the pll register
698 * Provides a IO register accessor for the atom interpreter (r4xx+).
700 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
702 struct radeon_device *rdev = info->dev->dev_private;
704 WREG32_IO(reg*4, val);
708 * cail_ioreg_read - read IO register
710 * @info: atom card_info pointer
711 * @reg: IO register offset
713 * Provides an IO register accessor for the atom interpreter (r4xx+).
714 * Returns the value of the IO register.
716 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
718 struct radeon_device *rdev = info->dev->dev_private;
721 r = RREG32_IO(reg*4);
726 * radeon_atombios_init - init the driver info and callbacks for atombios
728 * @rdev: radeon_device pointer
730 * Initializes the driver info and register access callbacks for the
731 * ATOM interpreter (r4xx+).
732 * Returns 0 on sucess, -ENOMEM on failure.
733 * Called at driver startup.
735 int radeon_atombios_init(struct radeon_device *rdev)
737 struct card_info *atom_card_info =
738 kzalloc(sizeof(struct card_info), GFP_KERNEL);
743 rdev->mode_info.atom_card_info = atom_card_info;
744 atom_card_info->dev = rdev->ddev;
745 atom_card_info->reg_read = cail_reg_read;
746 atom_card_info->reg_write = cail_reg_write;
747 /* needed for iio ops */
749 atom_card_info->ioreg_read = cail_ioreg_read;
750 atom_card_info->ioreg_write = cail_ioreg_write;
752 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
753 atom_card_info->ioreg_read = cail_reg_read;
754 atom_card_info->ioreg_write = cail_reg_write;
756 atom_card_info->mc_read = cail_mc_read;
757 atom_card_info->mc_write = cail_mc_write;
758 atom_card_info->pll_read = cail_pll_read;
759 atom_card_info->pll_write = cail_pll_write;
761 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
762 if (!rdev->mode_info.atom_context) {
763 radeon_atombios_fini(rdev);
767 mutex_init(&rdev->mode_info.atom_context->mutex);
768 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
769 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
774 * radeon_atombios_fini - free the driver info and callbacks for atombios
776 * @rdev: radeon_device pointer
778 * Frees the driver info and register access callbacks for the ATOM
779 * interpreter (r4xx+).
780 * Called at driver shutdown.
782 void radeon_atombios_fini(struct radeon_device *rdev)
784 if (rdev->mode_info.atom_context) {
785 kfree(rdev->mode_info.atom_context->scratch);
787 kfree(rdev->mode_info.atom_context);
788 rdev->mode_info.atom_context = NULL;
789 kfree(rdev->mode_info.atom_card_info);
790 rdev->mode_info.atom_card_info = NULL;
795 * COMBIOS is the bios format prior to ATOM. It provides
796 * command tables similar to ATOM, but doesn't have a unified
797 * parser. See radeon_combios.c
801 * radeon_combios_init - init the driver info for combios
803 * @rdev: radeon_device pointer
805 * Initializes the driver info for combios (r1xx-r3xx).
806 * Returns 0 on sucess.
807 * Called at driver startup.
809 int radeon_combios_init(struct radeon_device *rdev)
811 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
816 * radeon_combios_fini - free the driver info for combios
818 * @rdev: radeon_device pointer
820 * Frees the driver info for combios (r1xx-r3xx).
821 * Called at driver shutdown.
823 void radeon_combios_fini(struct radeon_device *rdev)
827 /* if we get transitioned to only one device, take VGA back */
829 * radeon_vga_set_decode - enable/disable vga decode
831 * @cookie: radeon_device pointer
832 * @state: enable/disable vga decode
834 * Enable/disable vga decode (all asics).
835 * Returns VGA resource flags.
837 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
839 struct radeon_device *rdev = cookie;
840 radeon_vga_set_state(rdev, state);
842 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
843 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
845 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
849 * radeon_check_pot_argument - check that argument is a power of two
851 * @arg: value to check
853 * Validates that a certain argument is a power of two (all asics).
854 * Returns true if argument is valid.
856 static bool radeon_check_pot_argument(int arg)
858 return (arg & (arg - 1)) == 0;
862 * radeon_check_arguments - validate module params
864 * @rdev: radeon_device pointer
866 * Validates certain module parameters and updates
867 * the associated values used by the driver (all asics).
869 static void radeon_check_arguments(struct radeon_device *rdev)
871 /* vramlimit must be a power of two */
872 if (!radeon_check_pot_argument(radeon_vram_limit)) {
873 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
875 radeon_vram_limit = 0;
878 /* gtt size must be power of two and greater or equal to 32M */
879 if (radeon_gart_size < 32) {
880 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
882 radeon_gart_size = 512;
884 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
885 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
887 radeon_gart_size = 512;
889 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
891 /* AGP mode can only be -1, 1, 2, 4, 8 */
892 switch (radeon_agpmode) {
901 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
902 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
909 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
910 * needed for waking up.
912 * @pdev: pci dev pointer
914 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
917 /* 6600m in a macbook pro */
918 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
919 pdev->subsystem_device == 0x00e2) {
920 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
928 * radeon_switcheroo_set_state - set switcheroo state
930 * @pdev: pci dev pointer
931 * @state: vga switcheroo state
933 * Callback for the switcheroo driver. Suspends or resumes the
934 * the asics before or after it is powered up using ACPI methods.
936 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
938 struct drm_device *dev = pci_get_drvdata(pdev);
939 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
940 if (state == VGA_SWITCHEROO_ON) {
941 unsigned d3_delay = dev->pdev->d3_delay;
943 printk(KERN_INFO "radeon: switched on\n");
944 /* don't suspend or resume card normally */
945 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
947 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
948 dev->pdev->d3_delay = 20;
950 radeon_resume_kms(dev);
952 dev->pdev->d3_delay = d3_delay;
954 dev->switch_power_state = DRM_SWITCH_POWER_ON;
955 drm_kms_helper_poll_enable(dev);
957 printk(KERN_INFO "radeon: switched off\n");
958 drm_kms_helper_poll_disable(dev);
959 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
960 radeon_suspend_kms(dev, pmm);
961 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
966 * radeon_switcheroo_can_switch - see if switcheroo state can change
968 * @pdev: pci dev pointer
970 * Callback for the switcheroo driver. Check of the switcheroo
971 * state can be changed.
972 * Returns true if the state can be changed, false if not.
974 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
976 struct drm_device *dev = pci_get_drvdata(pdev);
979 spin_lock(&dev->count_lock);
980 can_switch = (dev->open_count == 0);
981 spin_unlock(&dev->count_lock);
985 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
986 .set_gpu_state = radeon_switcheroo_set_state,
988 .can_switch = radeon_switcheroo_can_switch,
992 * radeon_device_init - initialize the driver
994 * @rdev: radeon_device pointer
995 * @pdev: drm dev pointer
996 * @pdev: pci dev pointer
997 * @flags: driver flags
999 * Initializes the driver info and hw (all asics).
1000 * Returns 0 for success or an error on failure.
1001 * Called at driver startup.
1003 int radeon_device_init(struct radeon_device *rdev,
1004 struct drm_device *ddev,
1005 struct pci_dev *pdev,
1011 rdev->shutdown = false;
1012 rdev->dev = &pdev->dev;
1015 rdev->flags = flags;
1016 rdev->family = flags & RADEON_FAMILY_MASK;
1017 rdev->is_atom_bios = false;
1018 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1019 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1020 rdev->accel_working = false;
1021 /* set up ring ids */
1022 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1023 rdev->ring[i].idx = i;
1026 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1027 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1028 pdev->subsystem_vendor, pdev->subsystem_device);
1030 /* mutex initialization are all done here so we
1031 * can recall function without having locking issues */
1032 mutex_init(&rdev->ring_lock);
1033 mutex_init(&rdev->dc_hw_i2c_mutex);
1034 atomic_set(&rdev->ih.lock, 0);
1035 mutex_init(&rdev->gem.mutex);
1036 mutex_init(&rdev->pm.mutex);
1037 mutex_init(&rdev->gpu_clock_mutex);
1038 init_rwsem(&rdev->pm.mclk_lock);
1039 init_rwsem(&rdev->exclusive_lock);
1040 init_waitqueue_head(&rdev->irq.vblank_queue);
1041 r = radeon_gem_init(rdev);
1044 /* initialize vm here */
1045 mutex_init(&rdev->vm_manager.lock);
1046 /* Adjust VM size here.
1047 * Currently set to 4GB ((1 << 20) 4k pages).
1048 * Max GPUVM size for cayman and SI is 40 bits.
1050 rdev->vm_manager.max_pfn = 1 << 20;
1051 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1053 /* Set asic functions */
1054 r = radeon_asic_init(rdev);
1057 radeon_check_arguments(rdev);
1059 /* all of the newer IGP chips have an internal gart
1060 * However some rs4xx report as AGP, so remove that here.
1062 if ((rdev->family >= CHIP_RS400) &&
1063 (rdev->flags & RADEON_IS_IGP)) {
1064 rdev->flags &= ~RADEON_IS_AGP;
1067 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1068 radeon_agp_disable(rdev);
1071 /* Set the internal MC address mask
1072 * This is the max address of the GPU's
1073 * internal address space.
1075 if (rdev->family >= CHIP_CAYMAN)
1076 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1077 else if (rdev->family >= CHIP_CEDAR)
1078 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1080 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1082 /* set DMA mask + need_dma32 flags.
1083 * PCIE - can handle 40-bits.
1084 * IGP - can handle 40-bits
1085 * AGP - generally dma32 is safest
1086 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1088 rdev->need_dma32 = false;
1089 if (rdev->flags & RADEON_IS_AGP)
1090 rdev->need_dma32 = true;
1091 if ((rdev->flags & RADEON_IS_PCI) &&
1092 (rdev->family <= CHIP_RS740))
1093 rdev->need_dma32 = true;
1095 dma_bits = rdev->need_dma32 ? 32 : 40;
1096 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1098 rdev->need_dma32 = true;
1100 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1102 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1104 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1105 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1108 /* Registers mapping */
1109 /* TODO: block userspace mapping of io register */
1110 spin_lock_init(&rdev->mmio_idx_lock);
1111 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1112 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1113 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1114 if (rdev->rmmio == NULL) {
1117 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1118 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1120 /* io port mapping */
1121 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1122 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1123 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1124 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1128 if (rdev->rio_mem == NULL)
1129 DRM_ERROR("Unable to find PCI I/O BAR\n");
1131 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1132 /* this will fail for cards that aren't VGA class devices, just
1134 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1135 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1137 r = radeon_init(rdev);
1141 r = radeon_ib_ring_tests(rdev);
1143 DRM_ERROR("ib ring test failed (%d).\n", r);
1145 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1146 /* Acceleration not working on AGP card try again
1147 * with fallback to PCI or PCIE GART
1149 radeon_asic_reset(rdev);
1151 radeon_agp_disable(rdev);
1152 r = radeon_init(rdev);
1156 if ((radeon_testing & 1)) {
1157 radeon_test_moves(rdev);
1159 if ((radeon_testing & 2)) {
1160 radeon_test_syncing(rdev);
1162 if (radeon_benchmarking) {
1163 radeon_benchmark(rdev, radeon_benchmarking);
1168 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1171 * radeon_device_fini - tear down the driver
1173 * @rdev: radeon_device pointer
1175 * Tear down the driver info (all asics).
1176 * Called at driver shutdown.
1178 void radeon_device_fini(struct radeon_device *rdev)
1180 DRM_INFO("radeon: finishing device.\n");
1181 rdev->shutdown = true;
1182 /* evict vram memory */
1183 radeon_bo_evict_vram(rdev);
1185 vga_switcheroo_unregister_client(rdev->pdev);
1186 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1188 pci_iounmap(rdev->pdev, rdev->rio_mem);
1189 rdev->rio_mem = NULL;
1190 iounmap(rdev->rmmio);
1192 radeon_debugfs_remove_files(rdev);
1200 * radeon_suspend_kms - initiate device suspend
1202 * @pdev: drm dev pointer
1203 * @state: suspend state
1205 * Puts the hw in the suspend state (all asics).
1206 * Returns 0 for success or an error on failure.
1207 * Called at driver suspend.
1209 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
1211 struct radeon_device *rdev;
1212 struct drm_crtc *crtc;
1213 struct drm_connector *connector;
1215 bool force_completion = false;
1217 if (dev == NULL || dev->dev_private == NULL) {
1220 if (state.event == PM_EVENT_PRETHAW) {
1223 rdev = dev->dev_private;
1225 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1228 drm_kms_helper_poll_disable(dev);
1230 /* turn off display hw */
1231 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1232 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1235 /* unpin the front buffers */
1236 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1237 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1238 struct radeon_bo *robj;
1240 if (rfb == NULL || rfb->obj == NULL) {
1243 robj = gem_to_radeon_bo(rfb->obj);
1244 /* don't unpin kernel fb objects */
1245 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1246 r = radeon_bo_reserve(robj, false);
1248 radeon_bo_unpin(robj);
1249 radeon_bo_unreserve(robj);
1253 /* evict vram memory */
1254 radeon_bo_evict_vram(rdev);
1256 mutex_lock(&rdev->ring_lock);
1257 /* wait for gpu to finish processing current batch */
1258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1259 r = radeon_fence_wait_empty_locked(rdev, i);
1261 /* delay GPU reset to resume */
1262 force_completion = true;
1265 if (force_completion) {
1266 radeon_fence_driver_force_completion(rdev);
1268 mutex_unlock(&rdev->ring_lock);
1270 radeon_save_bios_scratch_regs(rdev);
1272 radeon_pm_suspend(rdev);
1273 radeon_suspend(rdev);
1274 radeon_hpd_fini(rdev);
1275 /* evict remaining vram memory */
1276 radeon_bo_evict_vram(rdev);
1278 radeon_agp_suspend(rdev);
1280 pci_save_state(dev->pdev);
1281 if (state.event == PM_EVENT_SUSPEND) {
1282 /* Shut down the device */
1283 pci_disable_device(dev->pdev);
1284 pci_set_power_state(dev->pdev, PCI_D3hot);
1287 radeon_fbdev_set_suspend(rdev, 1);
1293 * radeon_resume_kms - initiate device resume
1295 * @pdev: drm dev pointer
1297 * Bring the hw back to operating state (all asics).
1298 * Returns 0 for success or an error on failure.
1299 * Called at driver resume.
1301 int radeon_resume_kms(struct drm_device *dev)
1303 struct drm_connector *connector;
1304 struct radeon_device *rdev = dev->dev_private;
1307 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1311 pci_set_power_state(dev->pdev, PCI_D0);
1312 pci_restore_state(dev->pdev);
1313 if (pci_enable_device(dev->pdev)) {
1317 /* resume AGP if in use */
1318 radeon_agp_resume(rdev);
1319 radeon_resume(rdev);
1321 r = radeon_ib_ring_tests(rdev);
1323 DRM_ERROR("ib ring test failed (%d).\n", r);
1325 radeon_pm_resume(rdev);
1326 radeon_restore_bios_scratch_regs(rdev);
1328 radeon_fbdev_set_suspend(rdev, 0);
1331 /* init dig PHYs, disp eng pll */
1332 if (rdev->is_atom_bios) {
1333 radeon_atom_encoder_init(rdev);
1334 radeon_atom_disp_eng_pll_init(rdev);
1335 /* turn on the BL */
1336 if (rdev->mode_info.bl_encoder) {
1337 u8 bl_level = radeon_get_backlight_level(rdev,
1338 rdev->mode_info.bl_encoder);
1339 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1343 /* reset hpd state */
1344 radeon_hpd_init(rdev);
1345 /* blat the mode back in */
1346 drm_helper_resume_force_mode(dev);
1347 /* turn on display hw */
1348 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1349 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1352 drm_kms_helper_poll_enable(dev);
1357 * radeon_gpu_reset - reset the asic
1359 * @rdev: radeon device pointer
1361 * Attempt the reset the GPU if it has hung (all asics).
1362 * Returns 0 for success or an error on failure.
1364 int radeon_gpu_reset(struct radeon_device *rdev)
1366 unsigned ring_sizes[RADEON_NUM_RINGS];
1367 uint32_t *ring_data[RADEON_NUM_RINGS];
1374 down_write(&rdev->exclusive_lock);
1375 radeon_save_bios_scratch_regs(rdev);
1377 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1378 radeon_suspend(rdev);
1380 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1381 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1383 if (ring_sizes[i]) {
1385 dev_info(rdev->dev, "Saved %d dwords of commands "
1386 "on ring %d.\n", ring_sizes[i], i);
1391 r = radeon_asic_reset(rdev);
1393 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1394 radeon_resume(rdev);
1397 radeon_restore_bios_scratch_regs(rdev);
1400 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1401 radeon_ring_restore(rdev, &rdev->ring[i],
1402 ring_sizes[i], ring_data[i]);
1404 ring_data[i] = NULL;
1407 r = radeon_ib_ring_tests(rdev);
1409 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1412 radeon_suspend(rdev);
1417 radeon_fence_driver_force_completion(rdev);
1418 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1419 kfree(ring_data[i]);
1423 drm_helper_resume_force_mode(rdev->ddev);
1425 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1427 /* bad news, how to tell it to userspace ? */
1428 dev_info(rdev->dev, "GPU reset failed\n");
1431 up_write(&rdev->exclusive_lock);
1439 int radeon_debugfs_add_files(struct radeon_device *rdev,
1440 struct drm_info_list *files,
1445 for (i = 0; i < rdev->debugfs_count; i++) {
1446 if (rdev->debugfs[i].files == files) {
1447 /* Already registered */
1452 i = rdev->debugfs_count + 1;
1453 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1454 DRM_ERROR("Reached maximum number of debugfs components.\n");
1455 DRM_ERROR("Report so we increase "
1456 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1459 rdev->debugfs[rdev->debugfs_count].files = files;
1460 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1461 rdev->debugfs_count = i;
1462 #if defined(CONFIG_DEBUG_FS)
1463 drm_debugfs_create_files(files, nfiles,
1464 rdev->ddev->control->debugfs_root,
1465 rdev->ddev->control);
1466 drm_debugfs_create_files(files, nfiles,
1467 rdev->ddev->primary->debugfs_root,
1468 rdev->ddev->primary);
1473 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1475 #if defined(CONFIG_DEBUG_FS)
1478 for (i = 0; i < rdev->debugfs_count; i++) {
1479 drm_debugfs_remove_files(rdev->debugfs[i].files,
1480 rdev->debugfs[i].num_files,
1481 rdev->ddev->control);
1482 drm_debugfs_remove_files(rdev->debugfs[i].files,
1483 rdev->debugfs[i].num_files,
1484 rdev->ddev->primary);
1489 #if defined(CONFIG_DEBUG_FS)
1490 int radeon_debugfs_init(struct drm_minor *minor)
1495 void radeon_debugfs_cleanup(struct drm_minor *minor)