2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include <linux/efi.h>
36 #include "radeon_reg.h"
40 static const char radeon_family_name[][16] = {
106 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
107 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
109 struct radeon_px_quirk {
117 static struct radeon_px_quirk radeon_px_quirk_list[] = {
118 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
119 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
121 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
122 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
123 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
125 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
126 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
127 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
129 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
130 /* macbook pro 8.2 */
131 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
135 bool radeon_is_px(struct drm_device *dev)
137 struct radeon_device *rdev = dev->dev_private;
139 if (rdev->flags & RADEON_IS_PX)
144 static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
146 struct radeon_px_quirk *p = radeon_px_quirk_list;
148 /* Apply PX quirks */
149 while (p && p->chip_device != 0) {
150 if (rdev->pdev->vendor == p->chip_vendor &&
151 rdev->pdev->device == p->chip_device &&
152 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
153 rdev->pdev->subsystem_device == p->subsys_device) {
154 rdev->px_quirk_flags = p->px_quirk_flags;
160 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
161 rdev->flags &= ~RADEON_IS_PX;
165 * radeon_program_register_sequence - program an array of registers.
167 * @rdev: radeon_device pointer
168 * @registers: pointer to the register array
169 * @array_size: size of the register array
171 * Programs an array or registers with and and or masks.
172 * This is a helper for setting golden registers.
174 void radeon_program_register_sequence(struct radeon_device *rdev,
175 const u32 *registers,
176 const u32 array_size)
178 u32 tmp, reg, and_mask, or_mask;
184 for (i = 0; i < array_size; i +=3) {
185 reg = registers[i + 0];
186 and_mask = registers[i + 1];
187 or_mask = registers[i + 2];
189 if (and_mask == 0xffffffff) {
200 void radeon_pci_config_reset(struct radeon_device *rdev)
202 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
206 * radeon_surface_init - Clear GPU surface registers.
208 * @rdev: radeon_device pointer
210 * Clear GPU surface registers (r1xx-r5xx).
212 void radeon_surface_init(struct radeon_device *rdev)
214 /* FIXME: check this out */
215 if (rdev->family < CHIP_R600) {
218 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
219 if (rdev->surface_regs[i].bo)
220 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
222 radeon_clear_surface_reg(rdev, i);
224 /* enable surfaces */
225 WREG32(RADEON_SURFACE_CNTL, 0);
230 * GPU scratch registers helpers function.
233 * radeon_scratch_init - Init scratch register driver information.
235 * @rdev: radeon_device pointer
237 * Init CP scratch register driver information (r1xx-r5xx)
239 void radeon_scratch_init(struct radeon_device *rdev)
243 /* FIXME: check this out */
244 if (rdev->family < CHIP_R300) {
245 rdev->scratch.num_reg = 5;
247 rdev->scratch.num_reg = 7;
249 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
250 for (i = 0; i < rdev->scratch.num_reg; i++) {
251 rdev->scratch.free[i] = true;
252 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
257 * radeon_scratch_get - Allocate a scratch register
259 * @rdev: radeon_device pointer
260 * @reg: scratch register mmio offset
262 * Allocate a CP scratch register for use by the driver (all asics).
263 * Returns 0 on success or -EINVAL on failure.
265 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
269 for (i = 0; i < rdev->scratch.num_reg; i++) {
270 if (rdev->scratch.free[i]) {
271 rdev->scratch.free[i] = false;
272 *reg = rdev->scratch.reg[i];
280 * radeon_scratch_free - Free a scratch register
282 * @rdev: radeon_device pointer
283 * @reg: scratch register mmio offset
285 * Free a CP scratch register allocated for use by the driver (all asics)
287 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
291 for (i = 0; i < rdev->scratch.num_reg; i++) {
292 if (rdev->scratch.reg[i] == reg) {
293 rdev->scratch.free[i] = true;
300 * GPU doorbell aperture helpers function.
303 * radeon_doorbell_init - Init doorbell driver information.
305 * @rdev: radeon_device pointer
307 * Init doorbell driver information (CIK)
308 * Returns 0 on success, error on failure.
310 static int radeon_doorbell_init(struct radeon_device *rdev)
312 /* doorbell bar mapping */
313 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
314 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
316 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
317 if (rdev->doorbell.num_doorbells == 0)
320 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
321 if (rdev->doorbell.ptr == NULL) {
324 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
325 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
327 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
333 * radeon_doorbell_fini - Tear down doorbell driver information.
335 * @rdev: radeon_device pointer
337 * Tear down doorbell driver information (CIK)
339 static void radeon_doorbell_fini(struct radeon_device *rdev)
341 iounmap(rdev->doorbell.ptr);
342 rdev->doorbell.ptr = NULL;
346 * radeon_doorbell_get - Allocate a doorbell entry
348 * @rdev: radeon_device pointer
349 * @doorbell: doorbell index
351 * Allocate a doorbell for use by the driver (all asics).
352 * Returns 0 on success or -EINVAL on failure.
354 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
356 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
357 if (offset < rdev->doorbell.num_doorbells) {
358 __set_bit(offset, rdev->doorbell.used);
367 * radeon_doorbell_free - Free a doorbell entry
369 * @rdev: radeon_device pointer
370 * @doorbell: doorbell index
372 * Free a doorbell allocated for use by the driver (all asics)
374 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
376 if (doorbell < rdev->doorbell.num_doorbells)
377 __clear_bit(doorbell, rdev->doorbell.used);
381 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
384 * @rdev: radeon_device pointer
385 * @aperture_base: output returning doorbell aperture base physical address
386 * @aperture_size: output returning doorbell aperture size in bytes
387 * @start_offset: output returning # of doorbell bytes reserved for radeon.
389 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
390 * takes doorbells required for its own rings and reports the setup to KFD.
391 * Radeon reserved doorbells are at the start of the doorbell aperture.
393 void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
394 phys_addr_t *aperture_base,
395 size_t *aperture_size,
396 size_t *start_offset)
398 /* The first num_doorbells are used by radeon.
399 * KFD takes whatever's left in the aperture. */
400 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
401 *aperture_base = rdev->doorbell.base;
402 *aperture_size = rdev->doorbell.size;
403 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
413 * Writeback is the the method by which the the GPU updates special pages
414 * in memory with the status of certain GPU events (fences, ring pointers,
419 * radeon_wb_disable - Disable Writeback
421 * @rdev: radeon_device pointer
423 * Disables Writeback (all asics). Used for suspend.
425 void radeon_wb_disable(struct radeon_device *rdev)
427 rdev->wb.enabled = false;
431 * radeon_wb_fini - Disable Writeback and free memory
433 * @rdev: radeon_device pointer
435 * Disables Writeback and frees the Writeback memory (all asics).
436 * Used at driver shutdown.
438 void radeon_wb_fini(struct radeon_device *rdev)
440 radeon_wb_disable(rdev);
441 if (rdev->wb.wb_obj) {
442 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
443 radeon_bo_kunmap(rdev->wb.wb_obj);
444 radeon_bo_unpin(rdev->wb.wb_obj);
445 radeon_bo_unreserve(rdev->wb.wb_obj);
447 radeon_bo_unref(&rdev->wb.wb_obj);
449 rdev->wb.wb_obj = NULL;
454 * radeon_wb_init- Init Writeback driver info and allocate memory
456 * @rdev: radeon_device pointer
458 * Disables Writeback and frees the Writeback memory (all asics).
459 * Used at driver startup.
460 * Returns 0 on success or an -error on failure.
462 int radeon_wb_init(struct radeon_device *rdev)
466 if (rdev->wb.wb_obj == NULL) {
467 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
468 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
471 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
474 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
475 if (unlikely(r != 0)) {
476 radeon_wb_fini(rdev);
479 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
482 radeon_bo_unreserve(rdev->wb.wb_obj);
483 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
484 radeon_wb_fini(rdev);
487 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
488 radeon_bo_unreserve(rdev->wb.wb_obj);
490 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
491 radeon_wb_fini(rdev);
496 /* clear wb memory */
497 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
498 /* disable event_write fences */
499 rdev->wb.use_event = false;
500 /* disabled via module param */
501 if (radeon_no_wb == 1) {
502 rdev->wb.enabled = false;
504 if (rdev->flags & RADEON_IS_AGP) {
505 /* often unreliable on AGP */
506 rdev->wb.enabled = false;
507 } else if (rdev->family < CHIP_R300) {
508 /* often unreliable on pre-r300 */
509 rdev->wb.enabled = false;
511 rdev->wb.enabled = true;
512 /* event_write fences are only available on r600+ */
513 if (rdev->family >= CHIP_R600) {
514 rdev->wb.use_event = true;
518 /* always use writeback/events on NI, APUs */
519 if (rdev->family >= CHIP_PALM) {
520 rdev->wb.enabled = true;
521 rdev->wb.use_event = true;
524 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
530 * radeon_vram_location - try to find VRAM location
531 * @rdev: radeon device structure holding all necessary informations
532 * @mc: memory controller structure holding memory informations
533 * @base: base address at which to put VRAM
535 * Function will place try to place VRAM at base address provided
536 * as parameter (which is so far either PCI aperture address or
537 * for IGP TOM base address).
539 * If there is not enough space to fit the unvisible VRAM in the 32bits
540 * address space then we limit the VRAM size to the aperture.
542 * If we are using AGP and if the AGP aperture doesn't allow us to have
543 * room for all the VRAM than we restrict the VRAM to the PCI aperture
544 * size and print a warning.
546 * This function will never fails, worst case are limiting VRAM.
548 * Note: GTT start, end, size should be initialized before calling this
549 * function on AGP platform.
551 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
552 * this shouldn't be a problem as we are using the PCI aperture as a reference.
553 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
556 * Note: we use mc_vram_size as on some board we need to program the mc to
557 * cover the whole aperture even if VRAM size is inferior to aperture size
558 * Novell bug 204882 + along with lots of ubuntu ones
560 * Note: when limiting vram it's safe to overwritte real_vram_size because
561 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
562 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
565 * Note: IGP TOM addr should be the same as the aperture addr, we don't
566 * explicitly check for that thought.
568 * FIXME: when reducing VRAM size align new size on power of 2.
570 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
572 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
574 mc->vram_start = base;
575 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
576 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
577 mc->real_vram_size = mc->aper_size;
578 mc->mc_vram_size = mc->aper_size;
580 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
581 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
582 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
583 mc->real_vram_size = mc->aper_size;
584 mc->mc_vram_size = mc->aper_size;
586 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
587 if (limit && limit < mc->real_vram_size)
588 mc->real_vram_size = limit;
589 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
590 mc->mc_vram_size >> 20, mc->vram_start,
591 mc->vram_end, mc->real_vram_size >> 20);
595 * radeon_gtt_location - try to find GTT location
596 * @rdev: radeon device structure holding all necessary informations
597 * @mc: memory controller structure holding memory informations
599 * Function will place try to place GTT before or after VRAM.
601 * If GTT size is bigger than space left then we ajust GTT size.
602 * Thus function will never fails.
604 * FIXME: when reducing GTT size align new size on power of 2.
606 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
608 u64 size_af, size_bf;
610 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
611 size_bf = mc->vram_start & ~mc->gtt_base_align;
612 if (size_bf > size_af) {
613 if (mc->gtt_size > size_bf) {
614 dev_warn(rdev->dev, "limiting GTT\n");
615 mc->gtt_size = size_bf;
617 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
619 if (mc->gtt_size > size_af) {
620 dev_warn(rdev->dev, "limiting GTT\n");
621 mc->gtt_size = size_af;
623 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
625 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
626 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
627 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
631 * GPU helpers function.
634 * radeon_card_posted - check if the hw has already been initialized
636 * @rdev: radeon_device pointer
638 * Check if the asic has been initialized (all asics).
639 * Used at driver startup.
640 * Returns true if initialized or false if not.
642 bool radeon_card_posted(struct radeon_device *rdev)
646 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
647 if (efi_enabled(EFI_BOOT) &&
648 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
649 (rdev->family < CHIP_R600))
652 if (ASIC_IS_NODCE(rdev))
655 /* first check CRTCs */
656 if (ASIC_IS_DCE4(rdev)) {
657 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
658 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
659 if (rdev->num_crtc >= 4) {
660 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
661 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
663 if (rdev->num_crtc >= 6) {
664 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
667 if (reg & EVERGREEN_CRTC_MASTER_EN)
669 } else if (ASIC_IS_AVIVO(rdev)) {
670 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
671 RREG32(AVIVO_D2CRTC_CONTROL);
672 if (reg & AVIVO_CRTC_EN) {
676 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
677 RREG32(RADEON_CRTC2_GEN_CNTL);
678 if (reg & RADEON_CRTC_EN) {
684 /* then check MEM_SIZE, in case the crtcs are off */
685 if (rdev->family >= CHIP_R600)
686 reg = RREG32(R600_CONFIG_MEMSIZE);
688 reg = RREG32(RADEON_CONFIG_MEMSIZE);
698 * radeon_update_bandwidth_info - update display bandwidth params
700 * @rdev: radeon_device pointer
702 * Used when sclk/mclk are switched or display modes are set.
703 * params are used to calculate display watermarks (all asics)
705 void radeon_update_bandwidth_info(struct radeon_device *rdev)
708 u32 sclk = rdev->pm.current_sclk;
709 u32 mclk = rdev->pm.current_mclk;
711 /* sclk/mclk in Mhz */
712 a.full = dfixed_const(100);
713 rdev->pm.sclk.full = dfixed_const(sclk);
714 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
715 rdev->pm.mclk.full = dfixed_const(mclk);
716 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
718 if (rdev->flags & RADEON_IS_IGP) {
719 a.full = dfixed_const(16);
720 /* core_bandwidth = sclk(Mhz) * 16 */
721 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
726 * radeon_boot_test_post_card - check and possibly initialize the hw
728 * @rdev: radeon_device pointer
730 * Check if the asic is initialized and if not, attempt to initialize
732 * Returns true if initialized or false if not.
734 bool radeon_boot_test_post_card(struct radeon_device *rdev)
736 if (radeon_card_posted(rdev))
740 DRM_INFO("GPU not posted. posting now...\n");
741 if (rdev->is_atom_bios)
742 atom_asic_init(rdev->mode_info.atom_context);
744 radeon_combios_asic_init(rdev->ddev);
747 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
753 * radeon_dummy_page_init - init dummy page used by the driver
755 * @rdev: radeon_device pointer
757 * Allocate the dummy page used by the driver (all asics).
758 * This dummy page is used by the driver as a filler for gart entries
759 * when pages are taken out of the GART
760 * Returns 0 on sucess, -ENOMEM on failure.
762 int radeon_dummy_page_init(struct radeon_device *rdev)
764 if (rdev->dummy_page.page)
766 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
767 if (rdev->dummy_page.page == NULL)
769 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
770 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
771 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
772 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
773 __free_page(rdev->dummy_page.page);
774 rdev->dummy_page.page = NULL;
781 * radeon_dummy_page_fini - free dummy page used by the driver
783 * @rdev: radeon_device pointer
785 * Frees the dummy page used by the driver (all asics).
787 void radeon_dummy_page_fini(struct radeon_device *rdev)
789 if (rdev->dummy_page.page == NULL)
791 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
792 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
793 __free_page(rdev->dummy_page.page);
794 rdev->dummy_page.page = NULL;
798 /* ATOM accessor methods */
800 * ATOM is an interpreted byte code stored in tables in the vbios. The
801 * driver registers callbacks to access registers and the interpreter
802 * in the driver parses the tables and executes then to program specific
803 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
804 * atombios.h, and atom.c
808 * cail_pll_read - read PLL register
810 * @info: atom card_info pointer
811 * @reg: PLL register offset
813 * Provides a PLL register accessor for the atom interpreter (r4xx+).
814 * Returns the value of the PLL register.
816 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
818 struct radeon_device *rdev = info->dev->dev_private;
821 r = rdev->pll_rreg(rdev, reg);
826 * cail_pll_write - write PLL register
828 * @info: atom card_info pointer
829 * @reg: PLL register offset
830 * @val: value to write to the pll register
832 * Provides a PLL register accessor for the atom interpreter (r4xx+).
834 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
836 struct radeon_device *rdev = info->dev->dev_private;
838 rdev->pll_wreg(rdev, reg, val);
842 * cail_mc_read - read MC (Memory Controller) register
844 * @info: atom card_info pointer
845 * @reg: MC register offset
847 * Provides an MC register accessor for the atom interpreter (r4xx+).
848 * Returns the value of the MC register.
850 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
852 struct radeon_device *rdev = info->dev->dev_private;
855 r = rdev->mc_rreg(rdev, reg);
860 * cail_mc_write - write MC (Memory Controller) register
862 * @info: atom card_info pointer
863 * @reg: MC register offset
864 * @val: value to write to the pll register
866 * Provides a MC register accessor for the atom interpreter (r4xx+).
868 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
870 struct radeon_device *rdev = info->dev->dev_private;
872 rdev->mc_wreg(rdev, reg, val);
876 * cail_reg_write - write MMIO register
878 * @info: atom card_info pointer
879 * @reg: MMIO register offset
880 * @val: value to write to the pll register
882 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
884 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
886 struct radeon_device *rdev = info->dev->dev_private;
892 * cail_reg_read - read MMIO register
894 * @info: atom card_info pointer
895 * @reg: MMIO register offset
897 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
898 * Returns the value of the MMIO register.
900 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
902 struct radeon_device *rdev = info->dev->dev_private;
910 * cail_ioreg_write - write IO register
912 * @info: atom card_info pointer
913 * @reg: IO register offset
914 * @val: value to write to the pll register
916 * Provides a IO register accessor for the atom interpreter (r4xx+).
918 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
920 struct radeon_device *rdev = info->dev->dev_private;
922 WREG32_IO(reg*4, val);
926 * cail_ioreg_read - read IO register
928 * @info: atom card_info pointer
929 * @reg: IO register offset
931 * Provides an IO register accessor for the atom interpreter (r4xx+).
932 * Returns the value of the IO register.
934 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
936 struct radeon_device *rdev = info->dev->dev_private;
939 r = RREG32_IO(reg*4);
944 * radeon_atombios_init - init the driver info and callbacks for atombios
946 * @rdev: radeon_device pointer
948 * Initializes the driver info and register access callbacks for the
949 * ATOM interpreter (r4xx+).
950 * Returns 0 on sucess, -ENOMEM on failure.
951 * Called at driver startup.
953 int radeon_atombios_init(struct radeon_device *rdev)
955 struct card_info *atom_card_info =
956 kzalloc(sizeof(struct card_info), GFP_KERNEL);
961 rdev->mode_info.atom_card_info = atom_card_info;
962 atom_card_info->dev = rdev->ddev;
963 atom_card_info->reg_read = cail_reg_read;
964 atom_card_info->reg_write = cail_reg_write;
965 /* needed for iio ops */
967 atom_card_info->ioreg_read = cail_ioreg_read;
968 atom_card_info->ioreg_write = cail_ioreg_write;
970 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
971 atom_card_info->ioreg_read = cail_reg_read;
972 atom_card_info->ioreg_write = cail_reg_write;
974 atom_card_info->mc_read = cail_mc_read;
975 atom_card_info->mc_write = cail_mc_write;
976 atom_card_info->pll_read = cail_pll_read;
977 atom_card_info->pll_write = cail_pll_write;
979 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
980 if (!rdev->mode_info.atom_context) {
981 radeon_atombios_fini(rdev);
985 mutex_init(&rdev->mode_info.atom_context->mutex);
986 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
987 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
988 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
993 * radeon_atombios_fini - free the driver info and callbacks for atombios
995 * @rdev: radeon_device pointer
997 * Frees the driver info and register access callbacks for the ATOM
998 * interpreter (r4xx+).
999 * Called at driver shutdown.
1001 void radeon_atombios_fini(struct radeon_device *rdev)
1003 if (rdev->mode_info.atom_context) {
1004 kfree(rdev->mode_info.atom_context->scratch);
1006 kfree(rdev->mode_info.atom_context);
1007 rdev->mode_info.atom_context = NULL;
1008 kfree(rdev->mode_info.atom_card_info);
1009 rdev->mode_info.atom_card_info = NULL;
1014 * COMBIOS is the bios format prior to ATOM. It provides
1015 * command tables similar to ATOM, but doesn't have a unified
1016 * parser. See radeon_combios.c
1020 * radeon_combios_init - init the driver info for combios
1022 * @rdev: radeon_device pointer
1024 * Initializes the driver info for combios (r1xx-r3xx).
1025 * Returns 0 on sucess.
1026 * Called at driver startup.
1028 int radeon_combios_init(struct radeon_device *rdev)
1030 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1035 * radeon_combios_fini - free the driver info for combios
1037 * @rdev: radeon_device pointer
1039 * Frees the driver info for combios (r1xx-r3xx).
1040 * Called at driver shutdown.
1042 void radeon_combios_fini(struct radeon_device *rdev)
1046 /* if we get transitioned to only one device, take VGA back */
1048 * radeon_vga_set_decode - enable/disable vga decode
1050 * @cookie: radeon_device pointer
1051 * @state: enable/disable vga decode
1053 * Enable/disable vga decode (all asics).
1054 * Returns VGA resource flags.
1056 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1058 struct radeon_device *rdev = cookie;
1059 radeon_vga_set_state(rdev, state);
1061 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1062 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1064 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1068 * radeon_check_pot_argument - check that argument is a power of two
1070 * @arg: value to check
1072 * Validates that a certain argument is a power of two (all asics).
1073 * Returns true if argument is valid.
1075 static bool radeon_check_pot_argument(int arg)
1077 return (arg & (arg - 1)) == 0;
1081 * radeon_check_arguments - validate module params
1083 * @rdev: radeon_device pointer
1085 * Validates certain module parameters and updates
1086 * the associated values used by the driver (all asics).
1088 static void radeon_check_arguments(struct radeon_device *rdev)
1090 /* vramlimit must be a power of two */
1091 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1092 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1094 radeon_vram_limit = 0;
1097 if (radeon_gart_size == -1) {
1098 /* default to a larger gart size on newer asics */
1099 if (rdev->family >= CHIP_RV770)
1100 radeon_gart_size = 1024;
1102 radeon_gart_size = 512;
1104 /* gtt size must be power of two and greater or equal to 32M */
1105 if (radeon_gart_size < 32) {
1106 dev_warn(rdev->dev, "gart size (%d) too small\n",
1108 if (rdev->family >= CHIP_RV770)
1109 radeon_gart_size = 1024;
1111 radeon_gart_size = 512;
1112 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1113 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1115 if (rdev->family >= CHIP_RV770)
1116 radeon_gart_size = 1024;
1118 radeon_gart_size = 512;
1120 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1122 /* AGP mode can only be -1, 1, 2, 4, 8 */
1123 switch (radeon_agpmode) {
1132 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1133 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1138 if (!radeon_check_pot_argument(radeon_vm_size)) {
1139 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1144 if (radeon_vm_size < 1) {
1145 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
1151 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1153 if (radeon_vm_size > 1024) {
1154 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1159 /* defines number of bits in page table versus page directory,
1160 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1161 * page table and the remaining bits are in the page directory */
1162 if (radeon_vm_block_size == -1) {
1164 /* Total bits covered by PD + PTs */
1165 unsigned bits = ilog2(radeon_vm_size) + 18;
1167 /* Make sure the PD is 4K in size up to 8GB address space.
1168 Above that split equal between PD and PTs */
1169 if (radeon_vm_size <= 8)
1170 radeon_vm_block_size = bits - 9;
1172 radeon_vm_block_size = (bits + 3) / 2;
1174 } else if (radeon_vm_block_size < 9) {
1175 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1176 radeon_vm_block_size);
1177 radeon_vm_block_size = 9;
1180 if (radeon_vm_block_size > 24 ||
1181 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1182 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1183 radeon_vm_block_size);
1184 radeon_vm_block_size = 9;
1189 * radeon_switcheroo_set_state - set switcheroo state
1191 * @pdev: pci dev pointer
1192 * @state: vga switcheroo state
1194 * Callback for the switcheroo driver. Suspends or resumes the
1195 * the asics before or after it is powered up using ACPI methods.
1197 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1199 struct drm_device *dev = pci_get_drvdata(pdev);
1200 struct radeon_device *rdev = dev->dev_private;
1202 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1205 if (state == VGA_SWITCHEROO_ON) {
1206 unsigned d3_delay = dev->pdev->d3_delay;
1208 printk(KERN_INFO "radeon: switched on\n");
1209 /* don't suspend or resume card normally */
1210 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1212 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1213 dev->pdev->d3_delay = 20;
1215 radeon_resume_kms(dev, true, true);
1217 dev->pdev->d3_delay = d3_delay;
1219 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1220 drm_kms_helper_poll_enable(dev);
1222 printk(KERN_INFO "radeon: switched off\n");
1223 drm_kms_helper_poll_disable(dev);
1224 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1225 radeon_suspend_kms(dev, true, true);
1226 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1231 * radeon_switcheroo_can_switch - see if switcheroo state can change
1233 * @pdev: pci dev pointer
1235 * Callback for the switcheroo driver. Check of the switcheroo
1236 * state can be changed.
1237 * Returns true if the state can be changed, false if not.
1239 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1241 struct drm_device *dev = pci_get_drvdata(pdev);
1244 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1245 * locking inversion with the driver load path. And the access here is
1246 * completely racy anyway. So don't bother with locking for now.
1248 return dev->open_count == 0;
1251 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1252 .set_gpu_state = radeon_switcheroo_set_state,
1254 .can_switch = radeon_switcheroo_can_switch,
1258 * radeon_device_init - initialize the driver
1260 * @rdev: radeon_device pointer
1261 * @pdev: drm dev pointer
1262 * @pdev: pci dev pointer
1263 * @flags: driver flags
1265 * Initializes the driver info and hw (all asics).
1266 * Returns 0 for success or an error on failure.
1267 * Called at driver startup.
1269 int radeon_device_init(struct radeon_device *rdev,
1270 struct drm_device *ddev,
1271 struct pci_dev *pdev,
1276 bool runtime = false;
1278 rdev->shutdown = false;
1279 rdev->dev = &pdev->dev;
1282 rdev->flags = flags;
1283 rdev->family = flags & RADEON_FAMILY_MASK;
1284 rdev->is_atom_bios = false;
1285 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1286 rdev->mc.gtt_size = 512 * 1024 * 1024;
1287 rdev->accel_working = false;
1288 /* set up ring ids */
1289 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1290 rdev->ring[i].idx = i;
1292 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1294 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1295 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1296 pdev->subsystem_vendor, pdev->subsystem_device);
1298 /* mutex initialization are all done here so we
1299 * can recall function without having locking issues */
1300 mutex_init(&rdev->ring_lock);
1301 mutex_init(&rdev->dc_hw_i2c_mutex);
1302 atomic_set(&rdev->ih.lock, 0);
1303 mutex_init(&rdev->gem.mutex);
1304 mutex_init(&rdev->pm.mutex);
1305 mutex_init(&rdev->gpu_clock_mutex);
1306 mutex_init(&rdev->srbm_mutex);
1307 mutex_init(&rdev->grbm_idx_mutex);
1308 init_rwsem(&rdev->pm.mclk_lock);
1309 init_rwsem(&rdev->exclusive_lock);
1310 init_waitqueue_head(&rdev->irq.vblank_queue);
1311 mutex_init(&rdev->mn_lock);
1312 hash_init(rdev->mn_hash);
1313 r = radeon_gem_init(rdev);
1317 radeon_check_arguments(rdev);
1318 /* Adjust VM size here.
1319 * Max GPUVM size for cayman+ is 40 bits.
1321 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1323 /* Set asic functions */
1324 r = radeon_asic_init(rdev);
1328 /* all of the newer IGP chips have an internal gart
1329 * However some rs4xx report as AGP, so remove that here.
1331 if ((rdev->family >= CHIP_RS400) &&
1332 (rdev->flags & RADEON_IS_IGP)) {
1333 rdev->flags &= ~RADEON_IS_AGP;
1336 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1337 radeon_agp_disable(rdev);
1340 /* Set the internal MC address mask
1341 * This is the max address of the GPU's
1342 * internal address space.
1344 if (rdev->family >= CHIP_CAYMAN)
1345 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1346 else if (rdev->family >= CHIP_CEDAR)
1347 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1349 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1351 /* set DMA mask + need_dma32 flags.
1352 * PCIE - can handle 40-bits.
1353 * IGP - can handle 40-bits
1354 * AGP - generally dma32 is safest
1355 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1357 rdev->need_dma32 = false;
1358 if (rdev->flags & RADEON_IS_AGP)
1359 rdev->need_dma32 = true;
1360 if ((rdev->flags & RADEON_IS_PCI) &&
1361 (rdev->family <= CHIP_RS740))
1362 rdev->need_dma32 = true;
1364 dma_bits = rdev->need_dma32 ? 32 : 40;
1365 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1367 rdev->need_dma32 = true;
1369 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1371 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1373 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1374 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1377 /* Registers mapping */
1378 /* TODO: block userspace mapping of io register */
1379 spin_lock_init(&rdev->mmio_idx_lock);
1380 spin_lock_init(&rdev->smc_idx_lock);
1381 spin_lock_init(&rdev->pll_idx_lock);
1382 spin_lock_init(&rdev->mc_idx_lock);
1383 spin_lock_init(&rdev->pcie_idx_lock);
1384 spin_lock_init(&rdev->pciep_idx_lock);
1385 spin_lock_init(&rdev->pif_idx_lock);
1386 spin_lock_init(&rdev->cg_idx_lock);
1387 spin_lock_init(&rdev->uvd_idx_lock);
1388 spin_lock_init(&rdev->rcu_idx_lock);
1389 spin_lock_init(&rdev->didt_idx_lock);
1390 spin_lock_init(&rdev->end_idx_lock);
1391 if (rdev->family >= CHIP_BONAIRE) {
1392 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1393 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1395 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1396 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1398 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1399 if (rdev->rmmio == NULL) {
1402 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1403 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1405 /* doorbell bar mapping */
1406 if (rdev->family >= CHIP_BONAIRE)
1407 radeon_doorbell_init(rdev);
1409 /* io port mapping */
1410 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1411 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1412 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1413 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1417 if (rdev->rio_mem == NULL)
1418 DRM_ERROR("Unable to find PCI I/O BAR\n");
1420 if (rdev->flags & RADEON_IS_PX)
1421 radeon_device_handle_px_quirks(rdev);
1423 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1424 /* this will fail for cards that aren't VGA class devices, just
1426 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1428 if (rdev->flags & RADEON_IS_PX)
1430 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1432 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1434 r = radeon_init(rdev);
1438 r = radeon_gem_debugfs_init(rdev);
1440 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1443 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1444 /* Acceleration not working on AGP card try again
1445 * with fallback to PCI or PCIE GART
1447 radeon_asic_reset(rdev);
1449 radeon_agp_disable(rdev);
1450 r = radeon_init(rdev);
1455 r = radeon_ib_ring_tests(rdev);
1457 DRM_ERROR("ib ring test failed (%d).\n", r);
1459 if ((radeon_testing & 1)) {
1460 if (rdev->accel_working)
1461 radeon_test_moves(rdev);
1463 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1465 if ((radeon_testing & 2)) {
1466 if (rdev->accel_working)
1467 radeon_test_syncing(rdev);
1469 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1471 if (radeon_benchmarking) {
1472 if (rdev->accel_working)
1473 radeon_benchmark(rdev, radeon_benchmarking);
1475 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1481 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1485 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1488 * radeon_device_fini - tear down the driver
1490 * @rdev: radeon_device pointer
1492 * Tear down the driver info (all asics).
1493 * Called at driver shutdown.
1495 void radeon_device_fini(struct radeon_device *rdev)
1497 DRM_INFO("radeon: finishing device.\n");
1498 rdev->shutdown = true;
1499 /* evict vram memory */
1500 radeon_bo_evict_vram(rdev);
1502 vga_switcheroo_unregister_client(rdev->pdev);
1503 if (rdev->flags & RADEON_IS_PX)
1504 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1505 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1507 pci_iounmap(rdev->pdev, rdev->rio_mem);
1508 rdev->rio_mem = NULL;
1509 iounmap(rdev->rmmio);
1511 if (rdev->family >= CHIP_BONAIRE)
1512 radeon_doorbell_fini(rdev);
1513 radeon_debugfs_remove_files(rdev);
1521 * radeon_suspend_kms - initiate device suspend
1523 * @pdev: drm dev pointer
1524 * @state: suspend state
1526 * Puts the hw in the suspend state (all asics).
1527 * Returns 0 for success or an error on failure.
1528 * Called at driver suspend.
1530 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1532 struct radeon_device *rdev;
1533 struct drm_crtc *crtc;
1534 struct drm_connector *connector;
1537 if (dev == NULL || dev->dev_private == NULL) {
1541 rdev = dev->dev_private;
1543 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1546 drm_kms_helper_poll_disable(dev);
1548 /* turn off display hw */
1549 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1550 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1553 /* unpin the front buffers */
1554 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1555 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1556 struct radeon_bo *robj;
1558 if (rfb == NULL || rfb->obj == NULL) {
1561 robj = gem_to_radeon_bo(rfb->obj);
1562 /* don't unpin kernel fb objects */
1563 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1564 r = radeon_bo_reserve(robj, false);
1566 radeon_bo_unpin(robj);
1567 radeon_bo_unreserve(robj);
1571 /* evict vram memory */
1572 radeon_bo_evict_vram(rdev);
1574 /* wait for gpu to finish processing current batch */
1575 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1576 r = radeon_fence_wait_empty(rdev, i);
1578 /* delay GPU reset to resume */
1579 radeon_fence_driver_force_completion(rdev, i);
1583 radeon_save_bios_scratch_regs(rdev);
1585 radeon_suspend(rdev);
1586 radeon_hpd_fini(rdev);
1587 /* evict remaining vram memory */
1588 radeon_bo_evict_vram(rdev);
1590 radeon_agp_suspend(rdev);
1592 pci_save_state(dev->pdev);
1594 /* Shut down the device */
1595 pci_disable_device(dev->pdev);
1596 pci_set_power_state(dev->pdev, PCI_D3hot);
1601 radeon_fbdev_set_suspend(rdev, 1);
1608 * radeon_resume_kms - initiate device resume
1610 * @pdev: drm dev pointer
1612 * Bring the hw back to operating state (all asics).
1613 * Returns 0 for success or an error on failure.
1614 * Called at driver resume.
1616 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1618 struct drm_connector *connector;
1619 struct radeon_device *rdev = dev->dev_private;
1622 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1629 pci_set_power_state(dev->pdev, PCI_D0);
1630 pci_restore_state(dev->pdev);
1631 if (pci_enable_device(dev->pdev)) {
1637 /* resume AGP if in use */
1638 radeon_agp_resume(rdev);
1639 radeon_resume(rdev);
1641 r = radeon_ib_ring_tests(rdev);
1643 DRM_ERROR("ib ring test failed (%d).\n", r);
1645 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1646 /* do dpm late init */
1647 r = radeon_pm_late_init(rdev);
1649 rdev->pm.dpm_enabled = false;
1650 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1653 /* resume old pm late */
1654 radeon_pm_resume(rdev);
1657 radeon_restore_bios_scratch_regs(rdev);
1659 /* init dig PHYs, disp eng pll */
1660 if (rdev->is_atom_bios) {
1661 radeon_atom_encoder_init(rdev);
1662 radeon_atom_disp_eng_pll_init(rdev);
1663 /* turn on the BL */
1664 if (rdev->mode_info.bl_encoder) {
1665 u8 bl_level = radeon_get_backlight_level(rdev,
1666 rdev->mode_info.bl_encoder);
1667 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1671 /* reset hpd state */
1672 radeon_hpd_init(rdev);
1673 /* blat the mode back in */
1675 drm_helper_resume_force_mode(dev);
1676 /* turn on display hw */
1677 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1678 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1682 drm_kms_helper_poll_enable(dev);
1684 /* set the power state here in case we are a PX system or headless */
1685 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1686 radeon_pm_compute_clocks(rdev);
1689 radeon_fbdev_set_suspend(rdev, 0);
1697 * radeon_gpu_reset - reset the asic
1699 * @rdev: radeon device pointer
1701 * Attempt the reset the GPU if it has hung (all asics).
1702 * Returns 0 for success or an error on failure.
1704 int radeon_gpu_reset(struct radeon_device *rdev)
1706 unsigned ring_sizes[RADEON_NUM_RINGS];
1707 uint32_t *ring_data[RADEON_NUM_RINGS];
1714 down_write(&rdev->exclusive_lock);
1716 if (!rdev->needs_reset) {
1717 up_write(&rdev->exclusive_lock);
1721 radeon_save_bios_scratch_regs(rdev);
1723 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1724 radeon_suspend(rdev);
1725 radeon_hpd_fini(rdev);
1727 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1728 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1730 if (ring_sizes[i]) {
1732 dev_info(rdev->dev, "Saved %d dwords of commands "
1733 "on ring %d.\n", ring_sizes[i], i);
1737 r = radeon_asic_reset(rdev);
1739 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1740 radeon_resume(rdev);
1743 radeon_restore_bios_scratch_regs(rdev);
1745 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1746 if (!r && ring_data[i]) {
1747 radeon_ring_restore(rdev, &rdev->ring[i],
1748 ring_sizes[i], ring_data[i]);
1750 radeon_fence_driver_force_completion(rdev, i);
1751 kfree(ring_data[i]);
1755 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1756 /* do dpm late init */
1757 r = radeon_pm_late_init(rdev);
1759 rdev->pm.dpm_enabled = false;
1760 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1763 /* resume old pm late */
1764 radeon_pm_resume(rdev);
1767 /* init dig PHYs, disp eng pll */
1768 if (rdev->is_atom_bios) {
1769 radeon_atom_encoder_init(rdev);
1770 radeon_atom_disp_eng_pll_init(rdev);
1771 /* turn on the BL */
1772 if (rdev->mode_info.bl_encoder) {
1773 u8 bl_level = radeon_get_backlight_level(rdev,
1774 rdev->mode_info.bl_encoder);
1775 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1779 /* reset hpd state */
1780 radeon_hpd_init(rdev);
1782 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1784 rdev->in_reset = true;
1785 rdev->needs_reset = false;
1787 downgrade_write(&rdev->exclusive_lock);
1789 drm_helper_resume_force_mode(rdev->ddev);
1791 /* set the power state here in case we are a PX system or headless */
1792 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1793 radeon_pm_compute_clocks(rdev);
1796 r = radeon_ib_ring_tests(rdev);
1800 /* bad news, how to tell it to userspace ? */
1801 dev_info(rdev->dev, "GPU reset failed\n");
1804 rdev->needs_reset = r == -EAGAIN;
1805 rdev->in_reset = false;
1807 up_read(&rdev->exclusive_lock);
1815 int radeon_debugfs_add_files(struct radeon_device *rdev,
1816 struct drm_info_list *files,
1821 for (i = 0; i < rdev->debugfs_count; i++) {
1822 if (rdev->debugfs[i].files == files) {
1823 /* Already registered */
1828 i = rdev->debugfs_count + 1;
1829 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1830 DRM_ERROR("Reached maximum number of debugfs components.\n");
1831 DRM_ERROR("Report so we increase "
1832 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1835 rdev->debugfs[rdev->debugfs_count].files = files;
1836 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1837 rdev->debugfs_count = i;
1838 #if defined(CONFIG_DEBUG_FS)
1839 drm_debugfs_create_files(files, nfiles,
1840 rdev->ddev->control->debugfs_root,
1841 rdev->ddev->control);
1842 drm_debugfs_create_files(files, nfiles,
1843 rdev->ddev->primary->debugfs_root,
1844 rdev->ddev->primary);
1849 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1851 #if defined(CONFIG_DEBUG_FS)
1854 for (i = 0; i < rdev->debugfs_count; i++) {
1855 drm_debugfs_remove_files(rdev->debugfs[i].files,
1856 rdev->debugfs[i].num_files,
1857 rdev->ddev->control);
1858 drm_debugfs_remove_files(rdev->debugfs[i].files,
1859 rdev->debugfs[i].num_files,
1860 rdev->ddev->primary);
1865 #if defined(CONFIG_DEBUG_FS)
1866 int radeon_debugfs_init(struct drm_minor *minor)
1871 void radeon_debugfs_cleanup(struct drm_minor *minor)