2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include "radeon_drm.h"
29 #include "radeon_reg.h"
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
35 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
42 if (p->chunk_relocs_idx == -1) {
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
61 for (j = 0; j < i; j++) {
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
79 p->relocs[i].lobj.bo = p->relocs[i].robj;
80 p->relocs[i].lobj.wdomain = r->write_domain;
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
85 radeon_bo_list_add_object(&p->relocs[i].lobj,
89 p->relocs[i].handle = 0;
91 return radeon_bo_list_validate(&p->validated);
94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
96 p->priority = priority;
100 DRM_ERROR("unknown ring id: %d\n", ring);
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
105 case RADEON_CS_RING_COMPUTE:
106 if (p->rdev->family >= CHIP_TAHITI) {
108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
112 p->ring = RADEON_RING_TYPE_GFX_INDEX;
118 static void radeon_cs_sync_to(struct radeon_cs_parser *p,
119 struct radeon_fence *fence)
121 struct radeon_fence *other;
126 other = p->ib.sync_to[fence->ring];
127 p->ib.sync_to[fence->ring] = radeon_fence_later(fence, other);
130 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
134 for (i = 0; i < p->nrelocs; i++) {
135 if (!p->relocs[i].robj)
138 radeon_cs_sync_to(p, p->relocs[i].robj->tbo.sync_obj);
142 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
143 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
145 struct drm_radeon_cs *cs = data;
146 uint64_t *chunk_array_ptr;
148 u32 ring = RADEON_CS_RING_GFX;
151 if (!cs->num_chunks) {
155 INIT_LIST_HEAD(&p->validated);
158 p->ib.semaphore = NULL;
159 p->const_ib.sa_bo = NULL;
160 p->const_ib.semaphore = NULL;
161 p->chunk_ib_idx = -1;
162 p->chunk_relocs_idx = -1;
163 p->chunk_flags_idx = -1;
164 p->chunk_const_ib_idx = -1;
165 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
166 if (p->chunks_array == NULL) {
169 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
170 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
171 sizeof(uint64_t)*cs->num_chunks)) {
175 p->nchunks = cs->num_chunks;
176 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
177 if (p->chunks == NULL) {
180 for (i = 0; i < p->nchunks; i++) {
181 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
182 struct drm_radeon_cs_chunk user_chunk;
183 uint32_t __user *cdata;
185 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
186 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
187 sizeof(struct drm_radeon_cs_chunk))) {
190 p->chunks[i].length_dw = user_chunk.length_dw;
191 p->chunks[i].kdata = NULL;
192 p->chunks[i].chunk_id = user_chunk.chunk_id;
194 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
195 p->chunk_relocs_idx = i;
197 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
199 /* zero length IB isn't useful */
200 if (p->chunks[i].length_dw == 0)
203 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
204 p->chunk_const_ib_idx = i;
205 /* zero length CONST IB isn't useful */
206 if (p->chunks[i].length_dw == 0)
209 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
210 p->chunk_flags_idx = i;
211 /* zero length flags aren't useful */
212 if (p->chunks[i].length_dw == 0)
216 p->chunks[i].length_dw = user_chunk.length_dw;
217 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
219 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
220 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
221 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
222 size = p->chunks[i].length_dw * sizeof(uint32_t);
223 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
224 if (p->chunks[i].kdata == NULL) {
227 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
228 p->chunks[i].user_ptr, size)) {
231 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
232 p->cs_flags = p->chunks[i].kdata[0];
233 if (p->chunks[i].length_dw > 1)
234 ring = p->chunks[i].kdata[1];
235 if (p->chunks[i].length_dw > 2)
236 priority = (s32)p->chunks[i].kdata[2];
241 /* these are KMS only */
243 if ((p->cs_flags & RADEON_CS_USE_VM) &&
244 !p->rdev->vm_manager.enabled) {
245 DRM_ERROR("VM not active on asic!\n");
249 /* we only support VM on SI+ */
250 if ((p->rdev->family >= CHIP_TAHITI) &&
251 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
252 DRM_ERROR("VM required on SI+!\n");
256 if (radeon_cs_get_ring(p, ring, priority))
260 /* deal with non-vm */
261 if ((p->chunk_ib_idx != -1) &&
262 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
263 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
264 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
265 DRM_ERROR("cs IB too big: %d\n",
266 p->chunks[p->chunk_ib_idx].length_dw);
269 if ((p->rdev->flags & RADEON_IS_AGP)) {
270 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
271 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
272 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
273 p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
274 kfree(p->chunks[i].kpage[0]);
275 kfree(p->chunks[i].kpage[1]);
279 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
280 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
281 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
282 p->chunks[p->chunk_ib_idx].last_page_index =
283 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
290 * cs_parser_fini() - clean parser states
291 * @parser: parser structure holding parsing context.
292 * @error: error number
294 * If error is set than unvalidate buffer, otherwise just free memory
295 * used by parsing context.
297 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
302 ttm_eu_fence_buffer_objects(&parser->validated,
305 ttm_eu_backoff_reservation(&parser->validated);
308 if (parser->relocs != NULL) {
309 for (i = 0; i < parser->nrelocs; i++) {
310 if (parser->relocs[i].gobj)
311 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
314 kfree(parser->track);
315 kfree(parser->relocs);
316 kfree(parser->relocs_ptr);
317 for (i = 0; i < parser->nchunks; i++) {
318 kfree(parser->chunks[i].kdata);
319 if ((parser->rdev->flags & RADEON_IS_AGP)) {
320 kfree(parser->chunks[i].kpage[0]);
321 kfree(parser->chunks[i].kpage[1]);
324 kfree(parser->chunks);
325 kfree(parser->chunks_array);
326 radeon_ib_free(parser->rdev, &parser->ib);
327 radeon_ib_free(parser->rdev, &parser->const_ib);
330 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
331 struct radeon_cs_parser *parser)
333 struct radeon_cs_chunk *ib_chunk;
336 if (parser->chunk_ib_idx == -1)
339 if (parser->cs_flags & RADEON_CS_USE_VM)
342 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
343 /* Copy the packet into the IB, the parser will read from the
344 * input memory (cached) and write to the IB (which can be
347 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
348 NULL, ib_chunk->length_dw * 4);
350 DRM_ERROR("Failed to get ib !\n");
353 parser->ib.length_dw = ib_chunk->length_dw;
354 r = radeon_cs_parse(rdev, parser->ring, parser);
355 if (r || parser->parser_error) {
356 DRM_ERROR("Invalid command stream !\n");
359 r = radeon_cs_finish_pages(parser);
361 DRM_ERROR("Invalid command stream !\n");
364 radeon_cs_sync_rings(parser);
365 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
367 DRM_ERROR("Failed to schedule IB !\n");
372 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
373 struct radeon_vm *vm)
375 struct radeon_device *rdev = parser->rdev;
376 struct radeon_bo_list *lobj;
377 struct radeon_bo *bo;
380 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
384 list_for_each_entry(lobj, &parser->validated, tv.head) {
386 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
394 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
395 struct radeon_cs_parser *parser)
397 struct radeon_cs_chunk *ib_chunk;
398 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
399 struct radeon_vm *vm = &fpriv->vm;
402 if (parser->chunk_ib_idx == -1)
404 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
407 if ((rdev->family >= CHIP_TAHITI) &&
408 (parser->chunk_const_ib_idx != -1)) {
409 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
410 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
411 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
414 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
415 vm, ib_chunk->length_dw * 4);
417 DRM_ERROR("Failed to get const ib !\n");
420 parser->const_ib.is_const_ib = true;
421 parser->const_ib.length_dw = ib_chunk->length_dw;
422 /* Copy the packet into the IB */
423 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
424 ib_chunk->length_dw * 4)) {
427 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
433 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
434 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
435 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
438 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
439 vm, ib_chunk->length_dw * 4);
441 DRM_ERROR("Failed to get ib !\n");
444 parser->ib.length_dw = ib_chunk->length_dw;
445 /* Copy the packet into the IB */
446 if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
447 ib_chunk->length_dw * 4)) {
450 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
455 mutex_lock(&rdev->vm_manager.lock);
456 mutex_lock(&vm->mutex);
457 r = radeon_vm_alloc_pt(rdev, vm);
461 r = radeon_bo_vm_update_pte(parser, vm);
465 radeon_cs_sync_rings(parser);
466 radeon_cs_sync_to(parser, vm->last_flush);
467 radeon_cs_sync_to(parser, radeon_vm_grab_id(rdev, vm, parser->ring));
469 if ((rdev->family >= CHIP_TAHITI) &&
470 (parser->chunk_const_ib_idx != -1)) {
471 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
473 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
477 radeon_vm_fence(rdev, vm, parser->ib.fence);
481 mutex_unlock(&vm->mutex);
482 mutex_unlock(&rdev->vm_manager.lock);
486 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
489 r = radeon_gpu_reset(rdev);
496 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
498 struct radeon_device *rdev = dev->dev_private;
499 struct radeon_cs_parser parser;
502 down_read(&rdev->exclusive_lock);
503 if (!rdev->accel_working) {
504 up_read(&rdev->exclusive_lock);
507 /* initialize parser */
508 memset(&parser, 0, sizeof(struct radeon_cs_parser));
511 parser.dev = rdev->dev;
512 parser.family = rdev->family;
513 r = radeon_cs_parser_init(&parser, data);
515 DRM_ERROR("Failed to initialize parser !\n");
516 radeon_cs_parser_fini(&parser, r);
517 up_read(&rdev->exclusive_lock);
518 r = radeon_cs_handle_lockup(rdev, r);
521 r = radeon_cs_parser_relocs(&parser);
523 if (r != -ERESTARTSYS)
524 DRM_ERROR("Failed to parse relocation %d!\n", r);
525 radeon_cs_parser_fini(&parser, r);
526 up_read(&rdev->exclusive_lock);
527 r = radeon_cs_handle_lockup(rdev, r);
530 r = radeon_cs_ib_chunk(rdev, &parser);
534 r = radeon_cs_ib_vm_chunk(rdev, &parser);
539 radeon_cs_parser_fini(&parser, r);
540 up_read(&rdev->exclusive_lock);
541 r = radeon_cs_handle_lockup(rdev, r);
545 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
547 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
549 int size = PAGE_SIZE;
551 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
552 if (i == ibc->last_page_index) {
553 size = (ibc->length_dw * 4) % PAGE_SIZE;
558 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
559 ibc->user_ptr + (i * PAGE_SIZE),
566 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
569 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
571 int size = PAGE_SIZE;
572 bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
574 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
575 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
576 ibc->user_ptr + (i * PAGE_SIZE),
578 p->parser_error = -EFAULT;
583 if (pg_idx == ibc->last_page_index) {
584 size = (ibc->length_dw * 4) % PAGE_SIZE;
589 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
591 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
593 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
594 ibc->user_ptr + (pg_idx * PAGE_SIZE),
596 p->parser_error = -EFAULT;
600 /* copy to IB for non single case */
602 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
604 ibc->last_copied_page = pg_idx;
605 ibc->kpage_idx[new_page] = pg_idx;
610 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
612 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
613 u32 pg_idx, pg_offset;
617 pg_idx = (idx * 4) / PAGE_SIZE;
618 pg_offset = (idx * 4) % PAGE_SIZE;
620 if (ibc->kpage_idx[0] == pg_idx)
621 return ibc->kpage[0][pg_offset/4];
622 if (ibc->kpage_idx[1] == pg_idx)
623 return ibc->kpage[1][pg_offset/4];
625 new_page = radeon_cs_update_pages(p, pg_idx);
627 p->parser_error = new_page;
631 idx_value = ibc->kpage[new_page][pg_offset/4];