drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 454         if (!edid_info)
 455                 return false;
 456
 457         edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
 458                        GFP_KERNEL);
 459         if (edid == NULL)
 460                 return false;
 461
 462         memcpy((unsigned char *)edid,
 463                (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 struct edid *
 475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
 476 {
 477         if (rdev->mode_info.bios_hardcoded_edid)
 478                 return rdev->mode_info.bios_hardcoded_edid;
 479         return NULL;
 480 }
 481
 482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 483                                                        int ddc_line)
 484 {
 485         struct radeon_i2c_bus_rec i2c;
 486
 487         if (ddc_line == RADEON_GPIOPAD_MASK) {
 488                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 489                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 490                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 491                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 492                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 493                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 494                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 495                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 496         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 497                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 498                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 499                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 500                 i2c.a_data_reg = RADEON_MDGPIO_A;
 501                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 502                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 503                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 504                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 505         } else {
 506                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 507                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 508                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 509                 i2c.a_data_mask = RADEON_GPIO_A_0;
 510                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 511                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 512                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 513                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 514
 515                 i2c.mask_clk_reg = ddc_line;
 516                 i2c.mask_data_reg = ddc_line;
 517                 i2c.a_clk_reg = ddc_line;
 518                 i2c.a_data_reg = ddc_line;
 519                 i2c.en_clk_reg = ddc_line;
 520                 i2c.en_data_reg = ddc_line;
 521                 i2c.y_clk_reg = ddc_line;
 522                 i2c.y_data_reg = ddc_line;
 523         }
 524
 525         switch (rdev->family) {
 526         case CHIP_R100:
 527         case CHIP_RV100:
 528         case CHIP_RS100:
 529         case CHIP_RV200:
 530         case CHIP_RS200:
 531         case CHIP_RS300:
 532                 switch (ddc_line) {
 533                 case RADEON_GPIO_DVI_DDC:
 534                         /* in theory this should be hw capable,
 535                          * but it doesn't seem to work
 536                          */
 537                         i2c.hw_capable = false;
 538                         break;
 539                 default:
 540                         i2c.hw_capable = false;
 541                         break;
 542                 }
 543                 break;
 544         case CHIP_R200:
 545                 switch (ddc_line) {
 546                 case RADEON_GPIO_DVI_DDC:
 547                 case RADEON_GPIO_MONID:
 548                         i2c.hw_capable = true;
 549                         break;
 550                 default:
 551                         i2c.hw_capable = false;
 552                         break;
 553                 }
 554                 break;
 555         case CHIP_RV250:
 556         case CHIP_RV280:
 557                 switch (ddc_line) {
 558                 case RADEON_GPIO_VGA_DDC:
 559                 case RADEON_GPIO_DVI_DDC:
 560                 case RADEON_GPIO_CRT2_DDC:
 561                         i2c.hw_capable = true;
 562                         break;
 563                 default:
 564                         i2c.hw_capable = false;
 565                         break;
 566                 }
 567                 break;
 568         case CHIP_R300:
 569         case CHIP_R350:
 570                 switch (ddc_line) {
 571                 case RADEON_GPIO_VGA_DDC:
 572                 case RADEON_GPIO_DVI_DDC:
 573                         i2c.hw_capable = true;
 574                         break;
 575                 default:
 576                         i2c.hw_capable = false;
 577                         break;
 578                 }
 579                 break;
 580         case CHIP_RV350:
 581         case CHIP_RV380:
 582         case CHIP_RS400:
 583         case CHIP_RS480:
 584                 switch (ddc_line) {
 585                 case RADEON_GPIO_VGA_DDC:
 586                 case RADEON_GPIO_DVI_DDC:
 587                         i2c.hw_capable = true;
 588                         break;
 589                 case RADEON_GPIO_MONID:
 590                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 591                          * reliably on some pre-r4xx hardware; not sure why.
 592                          */
 593                         i2c.hw_capable = false;
 594                         break;
 595                 default:
 596                         i2c.hw_capable = false;
 597                         break;
 598                 }
 599                 break;
 600         default:
 601                 i2c.hw_capable = false;
 602                 break;
 603         }
 604         i2c.mm_i2c = false;
 605         i2c.i2c_id = 0;
 606         i2c.hpd_id = 0;
 607
 608         if (ddc_line)
 609                 i2c.valid = true;
 610         else
 611                 i2c.valid = false;
 612
 613         return i2c;
 614 }
 615
 616 bool radeon_combios_get_clock_info(struct drm_device *dev)
 617 {
 618         struct radeon_device *rdev = dev->dev_private;
 619         uint16_t pll_info;
 620         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 621         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 622         struct radeon_pll *spll = &rdev->clock.spll;
 623         struct radeon_pll *mpll = &rdev->clock.mpll;
 624         int8_t rev;
 625         uint16_t sclk, mclk;
 626
 627         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 628         if (pll_info) {
 629                 rev = RBIOS8(pll_info);
 630
 631                 /* pixel clocks */
 632                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 633                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 634                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 635                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 636                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 637                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 638
 639                 if (rev > 9) {
 640                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 641                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 642                 } else {
 643                         p1pll->pll_in_min = 40;
 644                         p1pll->pll_in_max = 500;
 645                 }
 646                 *p2pll = *p1pll;
 647
 648                 /* system clock */
 649                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 650                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 651                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 652                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 653
 654                 if (rev > 10) {
 655                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 656                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 657                 } else {
 658                         /* ??? */
 659                         spll->pll_in_min = 40;
 660                         spll->pll_in_max = 500;
 661                 }
 662
 663                 /* memory clock */
 664                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 665                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 666                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 667                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 668
 669                 if (rev > 10) {
 670                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 671                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 672                 } else {
 673                         /* ??? */
 674                         mpll->pll_in_min = 40;
 675                         mpll->pll_in_max = 500;
 676                 }
 677
 678                 /* default sclk/mclk */
 679                 sclk = RBIOS16(pll_info + 0xa);
 680                 mclk = RBIOS16(pll_info + 0x8);
 681                 if (sclk == 0)
 682                         sclk = 200 * 100;
 683                 if (mclk == 0)
 684                         mclk = 200 * 100;
 685
 686                 rdev->clock.default_sclk = sclk;
 687                 rdev->clock.default_mclk = mclk;
 688
 689                 return true;
 690         }
 691         return false;
 692 }
 693
 694 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 695 {
 696         struct drm_device *dev = rdev->ddev;
 697         u16 igp_info;
 698
 699         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 700
 701         if (igp_info) {
 702                 if (RBIOS16(igp_info + 0x4))
 703                         return true;
 704         }
 705         return false;
 706 }
 707
 708 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 709         0x00000808,             /* r100  */
 710         0x00000808,             /* rv100 */
 711         0x00000808,             /* rs100 */
 712         0x00000808,             /* rv200 */
 713         0x00000808,             /* rs200 */
 714         0x00000808,             /* r200  */
 715         0x00000808,             /* rv250 */
 716         0x00000000,             /* rs300 */
 717         0x00000808,             /* rv280 */
 718         0x00000808,             /* r300  */
 719         0x00000808,             /* r350  */
 720         0x00000808,             /* rv350 */
 721         0x00000808,             /* rv380 */
 722         0x00000808,             /* r420  */
 723         0x00000808,             /* r423  */
 724         0x00000808,             /* rv410 */
 725         0x00000000,             /* rs400 */
 726         0x00000000,             /* rs480 */
 727 };
 728
 729 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 730                                                           struct radeon_encoder_primary_dac *p_dac)
 731 {
 732         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 733         return;
 734 }
 735
 736 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 737                                                                        radeon_encoder
 738                                                                        *encoder)
 739 {
 740         struct drm_device *dev = encoder->base.dev;
 741         struct radeon_device *rdev = dev->dev_private;
 742         uint16_t dac_info;
 743         uint8_t rev, bg, dac;
 744         struct radeon_encoder_primary_dac *p_dac = NULL;
 745         int found = 0;
 746
 747         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 748                         GFP_KERNEL);
 749
 750         if (!p_dac)
 751                 return NULL;
 752
 753         /* check CRT table */
 754         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 755         if (dac_info) {
 756                 rev = RBIOS8(dac_info) & 0x3;
 757                 if (rev < 2) {
 758                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 759                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 760                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 761                 } else {
 762                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 763                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 764                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 765                 }
 766                 found = 1;
 767         }
 768
 769         if (!found) /* fallback to defaults */
 770                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 771
 772         return p_dac;
 773 }
 774
 775 enum radeon_tv_std
 776 radeon_combios_get_tv_info(struct radeon_device *rdev)
 777 {
 778         struct drm_device *dev = rdev->ddev;
 779         uint16_t tv_info;
 780         enum radeon_tv_std tv_std = TV_STD_NTSC;
 781
 782         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 783         if (tv_info) {
 784                 if (RBIOS8(tv_info + 6) == 'T') {
 785                         switch (RBIOS8(tv_info + 7) & 0xf) {
 786                         case 1:
 787                                 tv_std = TV_STD_NTSC;
 788                                 DRM_INFO("Default TV standard: NTSC\n");
 789                                 break;
 790                         case 2:
 791                                 tv_std = TV_STD_PAL;
 792                                 DRM_INFO("Default TV standard: PAL\n");
 793                                 break;
 794                         case 3:
 795                                 tv_std = TV_STD_PAL_M;
 796                                 DRM_INFO("Default TV standard: PAL-M\n");
 797                                 break;
 798                         case 4:
 799                                 tv_std = TV_STD_PAL_60;
 800                                 DRM_INFO("Default TV standard: PAL-60\n");
 801                                 break;
 802                         case 5:
 803                                 tv_std = TV_STD_NTSC_J;
 804                                 DRM_INFO("Default TV standard: NTSC-J\n");
 805                                 break;
 806                         case 6:
 807                                 tv_std = TV_STD_SCART_PAL;
 808                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 809                                 break;
 810                         default:
 811                                 tv_std = TV_STD_NTSC;
 812                                 DRM_INFO
 813                                     ("Unknown TV standard; defaulting to NTSC\n");
 814                                 break;
 815                         }
 816
 817                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 818                         case 0:
 819                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 820                                 break;
 821                         case 1:
 822                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 823                                 break;
 824                         case 2:
 825                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 826                                 break;
 827                         case 3:
 828                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 829                                 break;
 830                         default:
 831                                 break;
 832                         }
 833                 }
 834         }
 835         return tv_std;
 836 }
 837
 838 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 839         0x00000000,             /* r100  */
 840         0x00280000,             /* rv100 */
 841         0x00000000,             /* rs100 */
 842         0x00880000,             /* rv200 */
 843         0x00000000,             /* rs200 */
 844         0x00000000,             /* r200  */
 845         0x00770000,             /* rv250 */
 846         0x00290000,             /* rs300 */
 847         0x00560000,             /* rv280 */
 848         0x00780000,             /* r300  */
 849         0x00770000,             /* r350  */
 850         0x00780000,             /* rv350 */
 851         0x00780000,             /* rv380 */
 852         0x01080000,             /* r420  */
 853         0x01080000,             /* r423  */
 854         0x01080000,             /* rv410 */
 855         0x00780000,             /* rs400 */
 856         0x00780000,             /* rs480 */
 857 };
 858
 859 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 860                                                      struct radeon_encoder_tv_dac *tv_dac)
 861 {
 862         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 863         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 864                 tv_dac->ps2_tvdac_adj = 0x00880000;
 865         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 866         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 867         return;
 868 }
 869
 870 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 871                                                              radeon_encoder
 872                                                              *encoder)
 873 {
 874         struct drm_device *dev = encoder->base.dev;
 875         struct radeon_device *rdev = dev->dev_private;
 876         uint16_t dac_info;
 877         uint8_t rev, bg, dac;
 878         struct radeon_encoder_tv_dac *tv_dac = NULL;
 879         int found = 0;
 880
 881         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 882         if (!tv_dac)
 883                 return NULL;
 884
 885         /* first check TV table */
 886         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 887         if (dac_info) {
 888                 rev = RBIOS8(dac_info + 0x3);
 889                 if (rev > 4) {
 890                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 891                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 892                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 893
 894                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 895                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 896                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 897
 898                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 899                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 900                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 901                         found = 1;
 902                 } else if (rev > 1) {
 903                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 904                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 905                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 906
 907                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 908                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 909                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 910
 911                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 912                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 913                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 914                         found = 1;
 915                 }
 916                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 917         }
 918         if (!found) {
 919                 /* then check CRT table */
 920                 dac_info =
 921                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 922                 if (dac_info) {
 923                         rev = RBIOS8(dac_info) & 0x3;
 924                         if (rev < 2) {
 925                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 926                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 927                                 tv_dac->ps2_tvdac_adj =
 928                                     (bg << 16) | (dac << 20);
 929                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 930                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 931                                 found = 1;
 932                         } else {
 933                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 934                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 935                                 tv_dac->ps2_tvdac_adj =
 936                                     (bg << 16) | (dac << 20);
 937                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 938                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 939                                 found = 1;
 940                         }
 941                 } else {
 942                         DRM_INFO("No TV DAC info found in BIOS\n");
 943                 }
 944         }
 945
 946         if (!found) /* fallback to defaults */
 947                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 948
 949         return tv_dac;
 950 }
 951
 952 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 953                                                                          radeon_device
 954                                                                          *rdev)
 955 {
 956         struct radeon_encoder_lvds *lvds = NULL;
 957         uint32_t fp_vert_stretch, fp_horz_stretch;
 958         uint32_t ppll_div_sel, ppll_val;
 959         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 960
 961         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 962
 963         if (!lvds)
 964                 return NULL;
 965
 966         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 967         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 968
 969         /* These should be fail-safe defaults, fingers crossed */
 970         lvds->panel_pwr_delay = 200;
 971         lvds->panel_vcc_delay = 2000;
 972
 973         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 974         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 975         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 976
 977         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 978                 lvds->native_mode.vdisplay =
 979                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 980                      RADEON_VERT_PANEL_SHIFT) + 1;
 981         else
 982                 lvds->native_mode.vdisplay =
 983                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 984
 985         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 986                 lvds->native_mode.hdisplay =
 987                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 988                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 989         else
 990                 lvds->native_mode.hdisplay =
 991                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 992
 993         if ((lvds->native_mode.hdisplay < 640) ||
 994             (lvds->native_mode.vdisplay < 480)) {
 995                 lvds->native_mode.hdisplay = 640;
 996                 lvds->native_mode.vdisplay = 480;
 997         }
 998
 999         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1000         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1001         if ((ppll_val & 0x000707ff) == 0x1bb)
1002                 lvds->use_bios_dividers = false;
1003         else {
1004                 lvds->panel_ref_divider =
1005                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1006                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1007                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1008
1009                 if ((lvds->panel_ref_divider != 0) &&
1010                     (lvds->panel_fb_divider > 3))
1011                         lvds->use_bios_dividers = true;
1012         }
1013         lvds->panel_vcc_delay = 200;
1014
1015         DRM_INFO("Panel info derived from registers\n");
1016         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1017                  lvds->native_mode.vdisplay);
1018
1019         return lvds;
1020 }
1021
1022 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1023                                                          *encoder)
1024 {
1025         struct drm_device *dev = encoder->base.dev;
1026         struct radeon_device *rdev = dev->dev_private;
1027         uint16_t lcd_info;
1028         uint32_t panel_setup;
1029         char stmp[30];
1030         int tmp, i;
1031         struct radeon_encoder_lvds *lvds = NULL;
1032
1033         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1034
1035         if (lcd_info) {
1036                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1037
1038                 if (!lvds)
1039                         return NULL;
1040
1041                 for (i = 0; i < 24; i++)
1042                         stmp[i] = RBIOS8(lcd_info + i + 1);
1043                 stmp[24] = 0;
1044
1045                 DRM_INFO("Panel ID String: %s\n", stmp);
1046
1047                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1048                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1049
1050                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1051                          lvds->native_mode.vdisplay);
1052
1053                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1054                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1055
1056                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1057                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1058                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1059
1060                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1061                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1062                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1063                 if ((lvds->panel_ref_divider != 0) &&
1064                     (lvds->panel_fb_divider > 3))
1065                         lvds->use_bios_dividers = true;
1066
1067                 panel_setup = RBIOS32(lcd_info + 0x39);
1068                 lvds->lvds_gen_cntl = 0xff00;
1069                 if (panel_setup & 0x1)
1070                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1071
1072                 if ((panel_setup >> 4) & 0x1)
1073                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1074
1075                 switch ((panel_setup >> 8) & 0x7) {
1076                 case 0:
1077                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1078                         break;
1079                 case 1:
1080                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1081                         break;
1082                 case 2:
1083                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1084                         break;
1085                 default:
1086                         break;
1087                 }
1088
1089                 if ((panel_setup >> 16) & 0x1)
1090                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1091
1092                 if ((panel_setup >> 17) & 0x1)
1093                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1094
1095                 if ((panel_setup >> 18) & 0x1)
1096                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1097
1098                 if ((panel_setup >> 23) & 0x1)
1099                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1100
1101                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1102
1103                 for (i = 0; i < 32; i++) {
1104                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1105                         if (tmp == 0)
1106                                 break;
1107
1108                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1109                             (RBIOS16(tmp + 2) ==
1110                              lvds->native_mode.vdisplay)) {
1111                                 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1112                                 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1113                                 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1114                                                                RBIOS16(tmp + 21)) * 8;
1115
1116                                 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1117                                 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1118                                 lvds->native_mode.vsync_end =
1119                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1120                                         (RBIOS16(tmp + 28) & 0x7ff);
1121
1122                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1123                                 lvds->native_mode.flags = 0;
1124                                 /* set crtc values */
1125                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1126
1127                         }
1128                 }
1129         } else {
1130                 DRM_INFO("No panel info found in BIOS\n");
1131                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1132         }
1133
1134         if (lvds)
1135                 encoder->native_mode = lvds->native_mode;
1136         return lvds;
1137 }
1138
1139 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1140         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1141         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1142         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1143         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1144         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1145         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1146         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1147         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1148         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1149         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1150         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1151         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1152         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1153         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1154         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1155         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1156         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1157         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1158 };
1159
1160 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1161                                             struct radeon_encoder_int_tmds *tmds)
1162 {
1163         struct drm_device *dev = encoder->base.dev;
1164         struct radeon_device *rdev = dev->dev_private;
1165         int i;
1166
1167         for (i = 0; i < 4; i++) {
1168                 tmds->tmds_pll[i].value =
1169                         default_tmds_pll[rdev->family][i].value;
1170                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1171         }
1172
1173         return true;
1174 }
1175
1176 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1177                                               struct radeon_encoder_int_tmds *tmds)
1178 {
1179         struct drm_device *dev = encoder->base.dev;
1180         struct radeon_device *rdev = dev->dev_private;
1181         uint16_t tmds_info;
1182         int i, n;
1183         uint8_t ver;
1184
1185         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1186
1187         if (tmds_info) {
1188                 ver = RBIOS8(tmds_info);
1189                 DRM_INFO("DFP table revision: %d\n", ver);
1190                 if (ver == 3) {
1191                         n = RBIOS8(tmds_info + 5) + 1;
1192                         if (n > 4)
1193                                 n = 4;
1194                         for (i = 0; i < n; i++) {
1195                                 tmds->tmds_pll[i].value =
1196                                     RBIOS32(tmds_info + i * 10 + 0x08);
1197                                 tmds->tmds_pll[i].freq =
1198                                     RBIOS16(tmds_info + i * 10 + 0x10);
1199                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1200                                           tmds->tmds_pll[i].freq,
1201                                           tmds->tmds_pll[i].value);
1202                         }
1203                 } else if (ver == 4) {
1204                         int stride = 0;
1205                         n = RBIOS8(tmds_info + 5) + 1;
1206                         if (n > 4)
1207                                 n = 4;
1208                         for (i = 0; i < n; i++) {
1209                                 tmds->tmds_pll[i].value =
1210                                     RBIOS32(tmds_info + stride + 0x08);
1211                                 tmds->tmds_pll[i].freq =
1212                                     RBIOS16(tmds_info + stride + 0x10);
1213                                 if (i == 0)
1214                                         stride += 10;
1215                                 else
1216                                         stride += 6;
1217                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1218                                           tmds->tmds_pll[i].freq,
1219                                           tmds->tmds_pll[i].value);
1220                         }
1221                 }
1222         } else {
1223                 DRM_INFO("No TMDS info found in BIOS\n");
1224                 return false;
1225         }
1226         return true;
1227 }
1228
1229 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1230                                                 struct radeon_encoder_ext_tmds *tmds)
1231 {
1232         struct drm_device *dev = encoder->base.dev;
1233         struct radeon_device *rdev = dev->dev_private;
1234         struct radeon_i2c_bus_rec i2c_bus;
1235
1236         /* default for macs */
1237         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1238         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1239
1240         /* XXX some macs have duallink chips */
1241         switch (rdev->mode_info.connector_table) {
1242         case CT_POWERBOOK_EXTERNAL:
1243         case CT_MINI_EXTERNAL:
1244         default:
1245                 tmds->dvo_chip = DVO_SIL164;
1246                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1247                 break;
1248         }
1249
1250         return true;
1251 }
1252
1253 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1254                                                   struct radeon_encoder_ext_tmds *tmds)
1255 {
1256         struct drm_device *dev = encoder->base.dev;
1257         struct radeon_device *rdev = dev->dev_private;
1258         uint16_t offset;
1259         uint8_t ver, id, blocks, clk, data;
1260         int i;
1261         enum radeon_combios_ddc gpio;
1262         struct radeon_i2c_bus_rec i2c_bus;
1263
1264         tmds->i2c_bus = NULL;
1265         if (rdev->flags & RADEON_IS_IGP) {
1266                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1267                 if (offset) {
1268                         ver = RBIOS8(offset);
1269                         DRM_INFO("GPIO Table revision: %d\n", ver);
1270                         blocks = RBIOS8(offset + 2);
1271                         for (i = 0; i < blocks; i++) {
1272                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1273                                 if (id == 136) {
1274                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1275                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1276                                         i2c_bus.valid = true;
1277                                         i2c_bus.mask_clk_mask = (1 << clk);
1278                                         i2c_bus.mask_data_mask = (1 << data);
1279                                         i2c_bus.a_clk_mask = (1 << clk);
1280                                         i2c_bus.a_data_mask = (1 << data);
1281                                         i2c_bus.en_clk_mask = (1 << clk);
1282                                         i2c_bus.en_data_mask = (1 << data);
1283                                         i2c_bus.y_clk_mask = (1 << clk);
1284                                         i2c_bus.y_data_mask = (1 << data);
1285                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1286                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1287                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1288                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1289                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1290                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1291                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1292                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1293                                         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1294                                         tmds->dvo_chip = DVO_SIL164;
1295                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1296                                         break;
1297                                 }
1298                         }
1299                 }
1300         } else {
1301                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1302                 if (offset) {
1303                         ver = RBIOS8(offset);
1304                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1305                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1306                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1307                         gpio = RBIOS8(offset + 4 + 3);
1308                         switch (gpio) {
1309                         case DDC_MONID:
1310                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1311                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1312                                 break;
1313                         case DDC_DVI:
1314                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1315                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1316                                 break;
1317                         case DDC_VGA:
1318                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1319                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1320                                 break;
1321                         case DDC_CRT2:
1322                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1323                                 if (rdev->family >= CHIP_R300)
1324                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1325                                 else
1326                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1327                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1328                                 break;
1329                         case DDC_LCD: /* MM i2c */
1330                                 i2c_bus.valid = true;
1331                                 i2c_bus.hw_capable = true;
1332                                 i2c_bus.mm_i2c = true;
1333                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1334                                 break;
1335                         default:
1336                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1337                                 break;
1338                         }
1339                 }
1340         }
1341
1342         if (!tmds->i2c_bus) {
1343                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1344                 return false;
1345         }
1346
1347         return true;
1348 }
1349
1350 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1351 {
1352         struct radeon_device *rdev = dev->dev_private;
1353         struct radeon_i2c_bus_rec ddc_i2c;
1354         struct radeon_hpd hpd;
1355
1356         rdev->mode_info.connector_table = radeon_connector_table;
1357         if (rdev->mode_info.connector_table == CT_NONE) {
1358 #ifdef CONFIG_PPC_PMAC
1359                 if (machine_is_compatible("PowerBook3,3")) {
1360                         /* powerbook with VGA */
1361                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1362                 } else if (machine_is_compatible("PowerBook3,4") ||
1363                            machine_is_compatible("PowerBook3,5")) {
1364                         /* powerbook with internal tmds */
1365                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1366                 } else if (machine_is_compatible("PowerBook5,1") ||
1367                            machine_is_compatible("PowerBook5,2") ||
1368                            machine_is_compatible("PowerBook5,3") ||
1369                            machine_is_compatible("PowerBook5,4") ||
1370                            machine_is_compatible("PowerBook5,5")) {
1371                         /* powerbook with external single link tmds (sil164) */
1372                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1373                 } else if (machine_is_compatible("PowerBook5,6")) {
1374                         /* powerbook with external dual or single link tmds */
1375                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1376                 } else if (machine_is_compatible("PowerBook5,7") ||
1377                            machine_is_compatible("PowerBook5,8") ||
1378                            machine_is_compatible("PowerBook5,9")) {
1379                         /* PowerBook6,2 ? */
1380                         /* powerbook with external dual link tmds (sil1178?) */
1381                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1382                 } else if (machine_is_compatible("PowerBook4,1") ||
1383                            machine_is_compatible("PowerBook4,2") ||
1384                            machine_is_compatible("PowerBook4,3") ||
1385                            machine_is_compatible("PowerBook6,3") ||
1386                            machine_is_compatible("PowerBook6,5") ||
1387                            machine_is_compatible("PowerBook6,7")) {
1388                         /* ibook */
1389                         rdev->mode_info.connector_table = CT_IBOOK;
1390                 } else if (machine_is_compatible("PowerMac4,4")) {
1391                         /* emac */
1392                         rdev->mode_info.connector_table = CT_EMAC;
1393                 } else if (machine_is_compatible("PowerMac10,1")) {
1394                         /* mini with internal tmds */
1395                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1396                 } else if (machine_is_compatible("PowerMac10,2")) {
1397                         /* mini with external tmds */
1398                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1399                 } else if (machine_is_compatible("PowerMac12,1")) {
1400                         /* PowerMac8,1 ? */
1401                         /* imac g5 isight */
1402                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1403                 } else
1404 #endif /* CONFIG_PPC_PMAC */
1405                         rdev->mode_info.connector_table = CT_GENERIC;
1406         }
1407
1408         switch (rdev->mode_info.connector_table) {
1409         case CT_GENERIC:
1410                 DRM_INFO("Connector Table: %d (generic)\n",
1411                          rdev->mode_info.connector_table);
1412                 /* these are the most common settings */
1413                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1414                         /* VGA - primary dac */
1415                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1416                         hpd.hpd = RADEON_HPD_NONE;
1417                         radeon_add_legacy_encoder(dev,
1418                                                   radeon_get_encoder_id(dev,
1419                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1420                                                                         1),
1421                                                   ATOM_DEVICE_CRT1_SUPPORT);
1422                         radeon_add_legacy_connector(dev, 0,
1423                                                     ATOM_DEVICE_CRT1_SUPPORT,
1424                                                     DRM_MODE_CONNECTOR_VGA,
1425                                                     &ddc_i2c,
1426                                                     CONNECTOR_OBJECT_ID_VGA,
1427                                                     &hpd);
1428                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1429                         /* LVDS */
1430                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1431                         hpd.hpd = RADEON_HPD_NONE;
1432                         radeon_add_legacy_encoder(dev,
1433                                                   radeon_get_encoder_id(dev,
1434                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1435                                                                         0),
1436                                                   ATOM_DEVICE_LCD1_SUPPORT);
1437                         radeon_add_legacy_connector(dev, 0,
1438                                                     ATOM_DEVICE_LCD1_SUPPORT,
1439                                                     DRM_MODE_CONNECTOR_LVDS,
1440                                                     &ddc_i2c,
1441                                                     CONNECTOR_OBJECT_ID_LVDS,
1442                                                     &hpd);
1443
1444                         /* VGA - primary dac */
1445                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1446                         hpd.hpd = RADEON_HPD_NONE;
1447                         radeon_add_legacy_encoder(dev,
1448                                                   radeon_get_encoder_id(dev,
1449                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1450                                                                         1),
1451                                                   ATOM_DEVICE_CRT1_SUPPORT);
1452                         radeon_add_legacy_connector(dev, 1,
1453                                                     ATOM_DEVICE_CRT1_SUPPORT,
1454                                                     DRM_MODE_CONNECTOR_VGA,
1455                                                     &ddc_i2c,
1456                                                     CONNECTOR_OBJECT_ID_VGA,
1457                                                     &hpd);
1458                 } else {
1459                         /* DVI-I - tv dac, int tmds */
1460                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1461                         hpd.hpd = RADEON_HPD_1;
1462                         radeon_add_legacy_encoder(dev,
1463                                                   radeon_get_encoder_id(dev,
1464                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1465                                                                         0),
1466                                                   ATOM_DEVICE_DFP1_SUPPORT);
1467                         radeon_add_legacy_encoder(dev,
1468                                                   radeon_get_encoder_id(dev,
1469                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1470                                                                         2),
1471                                                   ATOM_DEVICE_CRT2_SUPPORT);
1472                         radeon_add_legacy_connector(dev, 0,
1473                                                     ATOM_DEVICE_DFP1_SUPPORT |
1474                                                     ATOM_DEVICE_CRT2_SUPPORT,
1475                                                     DRM_MODE_CONNECTOR_DVII,
1476                                                     &ddc_i2c,
1477                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1478                                                     &hpd);
1479
1480                         /* VGA - primary dac */
1481                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1482                         hpd.hpd = RADEON_HPD_NONE;
1483                         radeon_add_legacy_encoder(dev,
1484                                                   radeon_get_encoder_id(dev,
1485                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1486                                                                         1),
1487                                                   ATOM_DEVICE_CRT1_SUPPORT);
1488                         radeon_add_legacy_connector(dev, 1,
1489                                                     ATOM_DEVICE_CRT1_SUPPORT,
1490                                                     DRM_MODE_CONNECTOR_VGA,
1491                                                     &ddc_i2c,
1492                                                     CONNECTOR_OBJECT_ID_VGA,
1493                                                     &hpd);
1494                 }
1495
1496                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1497                         /* TV - tv dac */
1498                         ddc_i2c.valid = false;
1499                         hpd.hpd = RADEON_HPD_NONE;
1500                         radeon_add_legacy_encoder(dev,
1501                                                   radeon_get_encoder_id(dev,
1502                                                                         ATOM_DEVICE_TV1_SUPPORT,
1503                                                                         2),
1504                                                   ATOM_DEVICE_TV1_SUPPORT);
1505                         radeon_add_legacy_connector(dev, 2,
1506                                                     ATOM_DEVICE_TV1_SUPPORT,
1507                                                     DRM_MODE_CONNECTOR_SVIDEO,
1508                                                     &ddc_i2c,
1509                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1510                                                     &hpd);
1511                 }
1512                 break;
1513         case CT_IBOOK:
1514                 DRM_INFO("Connector Table: %d (ibook)\n",
1515                          rdev->mode_info.connector_table);
1516                 /* LVDS */
1517                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1518                 hpd.hpd = RADEON_HPD_NONE;
1519                 radeon_add_legacy_encoder(dev,
1520                                           radeon_get_encoder_id(dev,
1521                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1522                                                                 0),
1523                                           ATOM_DEVICE_LCD1_SUPPORT);
1524                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1525                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1526                                             CONNECTOR_OBJECT_ID_LVDS,
1527                                             &hpd);
1528                 /* VGA - TV DAC */
1529                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1530                 hpd.hpd = RADEON_HPD_NONE;
1531                 radeon_add_legacy_encoder(dev,
1532                                           radeon_get_encoder_id(dev,
1533                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1534                                                                 2),
1535                                           ATOM_DEVICE_CRT2_SUPPORT);
1536                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1537                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1538                                             CONNECTOR_OBJECT_ID_VGA,
1539                                             &hpd);
1540                 /* TV - TV DAC */
1541                 ddc_i2c.valid = false;
1542                 hpd.hpd = RADEON_HPD_NONE;
1543                 radeon_add_legacy_encoder(dev,
1544                                           radeon_get_encoder_id(dev,
1545                                                                 ATOM_DEVICE_TV1_SUPPORT,
1546                                                                 2),
1547                                           ATOM_DEVICE_TV1_SUPPORT);
1548                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1549                                             DRM_MODE_CONNECTOR_SVIDEO,
1550                                             &ddc_i2c,
1551                                             CONNECTOR_OBJECT_ID_SVIDEO,
1552                                             &hpd);
1553                 break;
1554         case CT_POWERBOOK_EXTERNAL:
1555                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1556                          rdev->mode_info.connector_table);
1557                 /* LVDS */
1558                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1559                 hpd.hpd = RADEON_HPD_NONE;
1560                 radeon_add_legacy_encoder(dev,
1561                                           radeon_get_encoder_id(dev,
1562                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1563                                                                 0),
1564                                           ATOM_DEVICE_LCD1_SUPPORT);
1565                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1566                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1567                                             CONNECTOR_OBJECT_ID_LVDS,
1568                                             &hpd);
1569                 /* DVI-I - primary dac, ext tmds */
1570                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1571                 hpd.hpd = RADEON_HPD_2; /* ??? */
1572                 radeon_add_legacy_encoder(dev,
1573                                           radeon_get_encoder_id(dev,
1574                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1575                                                                 0),
1576                                           ATOM_DEVICE_DFP2_SUPPORT);
1577                 radeon_add_legacy_encoder(dev,
1578                                           radeon_get_encoder_id(dev,
1579                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1580                                                                 1),
1581                                           ATOM_DEVICE_CRT1_SUPPORT);
1582                 /* XXX some are SL */
1583                 radeon_add_legacy_connector(dev, 1,
1584                                             ATOM_DEVICE_DFP2_SUPPORT |
1585                                             ATOM_DEVICE_CRT1_SUPPORT,
1586                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1587                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1588                                             &hpd);
1589                 /* TV - TV DAC */
1590                 ddc_i2c.valid = false;
1591                 hpd.hpd = RADEON_HPD_NONE;
1592                 radeon_add_legacy_encoder(dev,
1593                                           radeon_get_encoder_id(dev,
1594                                                                 ATOM_DEVICE_TV1_SUPPORT,
1595                                                                 2),
1596                                           ATOM_DEVICE_TV1_SUPPORT);
1597                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1598                                             DRM_MODE_CONNECTOR_SVIDEO,
1599                                             &ddc_i2c,
1600                                             CONNECTOR_OBJECT_ID_SVIDEO,
1601                                             &hpd);
1602                 break;
1603         case CT_POWERBOOK_INTERNAL:
1604                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1605                          rdev->mode_info.connector_table);
1606                 /* LVDS */
1607                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1608                 hpd.hpd = RADEON_HPD_NONE;
1609                 radeon_add_legacy_encoder(dev,
1610                                           radeon_get_encoder_id(dev,
1611                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1612                                                                 0),
1613                                           ATOM_DEVICE_LCD1_SUPPORT);
1614                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1615                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1616                                             CONNECTOR_OBJECT_ID_LVDS,
1617                                             &hpd);
1618                 /* DVI-I - primary dac, int tmds */
1619                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1620                 hpd.hpd = RADEON_HPD_1; /* ??? */
1621                 radeon_add_legacy_encoder(dev,
1622                                           radeon_get_encoder_id(dev,
1623                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1624                                                                 0),
1625                                           ATOM_DEVICE_DFP1_SUPPORT);
1626                 radeon_add_legacy_encoder(dev,
1627                                           radeon_get_encoder_id(dev,
1628                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1629                                                                 1),
1630                                           ATOM_DEVICE_CRT1_SUPPORT);
1631                 radeon_add_legacy_connector(dev, 1,
1632                                             ATOM_DEVICE_DFP1_SUPPORT |
1633                                             ATOM_DEVICE_CRT1_SUPPORT,
1634                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1635                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1636                                             &hpd);
1637                 /* TV - TV DAC */
1638                 ddc_i2c.valid = false;
1639                 hpd.hpd = RADEON_HPD_NONE;
1640                 radeon_add_legacy_encoder(dev,
1641                                           radeon_get_encoder_id(dev,
1642                                                                 ATOM_DEVICE_TV1_SUPPORT,
1643                                                                 2),
1644                                           ATOM_DEVICE_TV1_SUPPORT);
1645                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1646                                             DRM_MODE_CONNECTOR_SVIDEO,
1647                                             &ddc_i2c,
1648                                             CONNECTOR_OBJECT_ID_SVIDEO,
1649                                             &hpd);
1650                 break;
1651         case CT_POWERBOOK_VGA:
1652                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1653                          rdev->mode_info.connector_table);
1654                 /* LVDS */
1655                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1656                 hpd.hpd = RADEON_HPD_NONE;
1657                 radeon_add_legacy_encoder(dev,
1658                                           radeon_get_encoder_id(dev,
1659                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1660                                                                 0),
1661                                           ATOM_DEVICE_LCD1_SUPPORT);
1662                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1663                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1664                                             CONNECTOR_OBJECT_ID_LVDS,
1665                                             &hpd);
1666                 /* VGA - primary dac */
1667                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1668                 hpd.hpd = RADEON_HPD_NONE;
1669                 radeon_add_legacy_encoder(dev,
1670                                           radeon_get_encoder_id(dev,
1671                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1672                                                                 1),
1673                                           ATOM_DEVICE_CRT1_SUPPORT);
1674                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1675                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1676                                             CONNECTOR_OBJECT_ID_VGA,
1677                                             &hpd);
1678                 /* TV - TV DAC */
1679                 ddc_i2c.valid = false;
1680                 hpd.hpd = RADEON_HPD_NONE;
1681                 radeon_add_legacy_encoder(dev,
1682                                           radeon_get_encoder_id(dev,
1683                                                                 ATOM_DEVICE_TV1_SUPPORT,
1684                                                                 2),
1685                                           ATOM_DEVICE_TV1_SUPPORT);
1686                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1687                                             DRM_MODE_CONNECTOR_SVIDEO,
1688                                             &ddc_i2c,
1689                                             CONNECTOR_OBJECT_ID_SVIDEO,
1690                                             &hpd);
1691                 break;
1692         case CT_MINI_EXTERNAL:
1693                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1694                          rdev->mode_info.connector_table);
1695                 /* DVI-I - tv dac, ext tmds */
1696                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1697                 hpd.hpd = RADEON_HPD_2; /* ??? */
1698                 radeon_add_legacy_encoder(dev,
1699                                           radeon_get_encoder_id(dev,
1700                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1701                                                                 0),
1702                                           ATOM_DEVICE_DFP2_SUPPORT);
1703                 radeon_add_legacy_encoder(dev,
1704                                           radeon_get_encoder_id(dev,
1705                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1706                                                                 2),
1707                                           ATOM_DEVICE_CRT2_SUPPORT);
1708                 /* XXX are any DL? */
1709                 radeon_add_legacy_connector(dev, 0,
1710                                             ATOM_DEVICE_DFP2_SUPPORT |
1711                                             ATOM_DEVICE_CRT2_SUPPORT,
1712                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1713                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1714                                             &hpd);
1715                 /* TV - TV DAC */
1716                 ddc_i2c.valid = false;
1717                 hpd.hpd = RADEON_HPD_NONE;
1718                 radeon_add_legacy_encoder(dev,
1719                                           radeon_get_encoder_id(dev,
1720                                                                 ATOM_DEVICE_TV1_SUPPORT,
1721                                                                 2),
1722                                           ATOM_DEVICE_TV1_SUPPORT);
1723                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1724                                             DRM_MODE_CONNECTOR_SVIDEO,
1725                                             &ddc_i2c,
1726                                             CONNECTOR_OBJECT_ID_SVIDEO,
1727                                             &hpd);
1728                 break;
1729         case CT_MINI_INTERNAL:
1730                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1731                          rdev->mode_info.connector_table);
1732                 /* DVI-I - tv dac, int tmds */
1733                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1734                 hpd.hpd = RADEON_HPD_1; /* ??? */
1735                 radeon_add_legacy_encoder(dev,
1736                                           radeon_get_encoder_id(dev,
1737                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1738                                                                 0),
1739                                           ATOM_DEVICE_DFP1_SUPPORT);
1740                 radeon_add_legacy_encoder(dev,
1741                                           radeon_get_encoder_id(dev,
1742                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1743                                                                 2),
1744                                           ATOM_DEVICE_CRT2_SUPPORT);
1745                 radeon_add_legacy_connector(dev, 0,
1746                                             ATOM_DEVICE_DFP1_SUPPORT |
1747                                             ATOM_DEVICE_CRT2_SUPPORT,
1748                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1749                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1750                                             &hpd);
1751                 /* TV - TV DAC */
1752                 ddc_i2c.valid = false;
1753                 hpd.hpd = RADEON_HPD_NONE;
1754                 radeon_add_legacy_encoder(dev,
1755                                           radeon_get_encoder_id(dev,
1756                                                                 ATOM_DEVICE_TV1_SUPPORT,
1757                                                                 2),
1758                                           ATOM_DEVICE_TV1_SUPPORT);
1759                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1760                                             DRM_MODE_CONNECTOR_SVIDEO,
1761                                             &ddc_i2c,
1762                                             CONNECTOR_OBJECT_ID_SVIDEO,
1763                                             &hpd);
1764                 break;
1765         case CT_IMAC_G5_ISIGHT:
1766                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1767                          rdev->mode_info.connector_table);
1768                 /* DVI-D - int tmds */
1769                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1770                 hpd.hpd = RADEON_HPD_1; /* ??? */
1771                 radeon_add_legacy_encoder(dev,
1772                                           radeon_get_encoder_id(dev,
1773                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1774                                                                 0),
1775                                           ATOM_DEVICE_DFP1_SUPPORT);
1776                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1777                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1778                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1779                                             &hpd);
1780                 /* VGA - tv dac */
1781                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1782                 hpd.hpd = RADEON_HPD_NONE;
1783                 radeon_add_legacy_encoder(dev,
1784                                           radeon_get_encoder_id(dev,
1785                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1786                                                                 2),
1787                                           ATOM_DEVICE_CRT2_SUPPORT);
1788                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1789                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1790                                             CONNECTOR_OBJECT_ID_VGA,
1791                                             &hpd);
1792                 /* TV - TV DAC */
1793                 ddc_i2c.valid = false;
1794                 hpd.hpd = RADEON_HPD_NONE;
1795                 radeon_add_legacy_encoder(dev,
1796                                           radeon_get_encoder_id(dev,
1797                                                                 ATOM_DEVICE_TV1_SUPPORT,
1798                                                                 2),
1799                                           ATOM_DEVICE_TV1_SUPPORT);
1800                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1801                                             DRM_MODE_CONNECTOR_SVIDEO,
1802                                             &ddc_i2c,
1803                                             CONNECTOR_OBJECT_ID_SVIDEO,
1804                                             &hpd);
1805                 break;
1806         case CT_EMAC:
1807                 DRM_INFO("Connector Table: %d (emac)\n",
1808                          rdev->mode_info.connector_table);
1809                 /* VGA - primary dac */
1810                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1811                 hpd.hpd = RADEON_HPD_NONE;
1812                 radeon_add_legacy_encoder(dev,
1813                                           radeon_get_encoder_id(dev,
1814                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1815                                                                 1),
1816                                           ATOM_DEVICE_CRT1_SUPPORT);
1817                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1818                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1819                                             CONNECTOR_OBJECT_ID_VGA,
1820                                             &hpd);
1821                 /* VGA - tv dac */
1822                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1823                 hpd.hpd = RADEON_HPD_NONE;
1824                 radeon_add_legacy_encoder(dev,
1825                                           radeon_get_encoder_id(dev,
1826                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1827                                                                 2),
1828                                           ATOM_DEVICE_CRT2_SUPPORT);
1829                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1830                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1831                                             CONNECTOR_OBJECT_ID_VGA,
1832                                             &hpd);
1833                 /* TV - TV DAC */
1834                 ddc_i2c.valid = false;
1835                 hpd.hpd = RADEON_HPD_NONE;
1836                 radeon_add_legacy_encoder(dev,
1837                                           radeon_get_encoder_id(dev,
1838                                                                 ATOM_DEVICE_TV1_SUPPORT,
1839                                                                 2),
1840                                           ATOM_DEVICE_TV1_SUPPORT);
1841                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1842                                             DRM_MODE_CONNECTOR_SVIDEO,
1843                                             &ddc_i2c,
1844                                             CONNECTOR_OBJECT_ID_SVIDEO,
1845                                             &hpd);
1846                 break;
1847         default:
1848                 DRM_INFO("Connector table: %d (invalid)\n",
1849                          rdev->mode_info.connector_table);
1850                 return false;
1851         }
1852
1853         radeon_link_encoder_connector(dev);
1854
1855         return true;
1856 }
1857
1858 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1859                                        int bios_index,
1860                                        enum radeon_combios_connector
1861                                        *legacy_connector,
1862                                        struct radeon_i2c_bus_rec *ddc_i2c,
1863                                        struct radeon_hpd *hpd)
1864 {
1865         struct radeon_device *rdev = dev->dev_private;
1866
1867         /* XPRESS DDC quirks */
1868         if ((rdev->family == CHIP_RS400 ||
1869              rdev->family == CHIP_RS480) &&
1870             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1871                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1872         else if ((rdev->family == CHIP_RS400 ||
1873                   rdev->family == CHIP_RS480) &&
1874                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1875                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1876                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1877                 ddc_i2c->mask_data_mask = 0x80;
1878                 ddc_i2c->a_clk_mask = (0x20 << 8);
1879                 ddc_i2c->a_data_mask = 0x80;
1880                 ddc_i2c->en_clk_mask = (0x20 << 8);
1881                 ddc_i2c->en_data_mask = 0x80;
1882                 ddc_i2c->y_clk_mask = (0x20 << 8);
1883                 ddc_i2c->y_data_mask = 0x80;
1884         }
1885
1886         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1887         if ((rdev->family >= CHIP_R300) &&
1888             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1889                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1890
1891         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1892            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1893         if (dev->pdev->device == 0x515e &&
1894             dev->pdev->subsystem_vendor == 0x1014) {
1895                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1896                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1897                         return false;
1898         }
1899
1900         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1901         if (dev->pdev->device == 0x5159 &&
1902             dev->pdev->subsystem_vendor == 0x1002 &&
1903             dev->pdev->subsystem_device == 0x013a) {
1904                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1905                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1906
1907         }
1908
1909         /* X300 card with extra non-existent DVI port */
1910         if (dev->pdev->device == 0x5B60 &&
1911             dev->pdev->subsystem_vendor == 0x17af &&
1912             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1913                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1914                         return false;
1915         }
1916
1917         return true;
1918 }
1919
1920 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1921 {
1922         /* Acer 5102 has non-existent TV port */
1923         if (dev->pdev->device == 0x5975 &&
1924             dev->pdev->subsystem_vendor == 0x1025 &&
1925             dev->pdev->subsystem_device == 0x009f)
1926                 return false;
1927
1928         /* HP dc5750 has non-existent TV port */
1929         if (dev->pdev->device == 0x5974 &&
1930             dev->pdev->subsystem_vendor == 0x103c &&
1931             dev->pdev->subsystem_device == 0x280a)
1932                 return false;
1933
1934         /* MSI S270 has non-existent TV port */
1935         if (dev->pdev->device == 0x5955 &&
1936             dev->pdev->subsystem_vendor == 0x1462 &&
1937             dev->pdev->subsystem_device == 0x0131)
1938                 return false;
1939
1940         return true;
1941 }
1942
1943 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1944 {
1945         struct radeon_device *rdev = dev->dev_private;
1946         uint32_t ext_tmds_info;
1947
1948         if (rdev->flags & RADEON_IS_IGP) {
1949                 if (is_dvi_d)
1950                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1951                 else
1952                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1953         }
1954         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1955         if (ext_tmds_info) {
1956                 uint8_t rev = RBIOS8(ext_tmds_info);
1957                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1958                 if (rev >= 3) {
1959                         if (is_dvi_d)
1960                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1961                         else
1962                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1963                 } else {
1964                         if (flags & 1) {
1965                                 if (is_dvi_d)
1966                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1967                                 else
1968                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1969                         }
1970                 }
1971         }
1972         if (is_dvi_d)
1973                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1974         else
1975                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1976 }
1977
1978 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1979 {
1980         struct radeon_device *rdev = dev->dev_private;
1981         uint32_t conn_info, entry, devices;
1982         uint16_t tmp, connector_object_id;
1983         enum radeon_combios_ddc ddc_type;
1984         enum radeon_combios_connector connector;
1985         int i = 0;
1986         struct radeon_i2c_bus_rec ddc_i2c;
1987         struct radeon_hpd hpd;
1988
1989         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1990         if (conn_info) {
1991                 for (i = 0; i < 4; i++) {
1992                         entry = conn_info + 2 + i * 2;
1993
1994                         if (!RBIOS16(entry))
1995                                 break;
1996
1997                         tmp = RBIOS16(entry);
1998
1999                         connector = (tmp >> 12) & 0xf;
2000
2001                         ddc_type = (tmp >> 8) & 0xf;
2002                         switch (ddc_type) {
2003                         case DDC_MONID:
2004                                 ddc_i2c =
2005                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2006                                 break;
2007                         case DDC_DVI:
2008                                 ddc_i2c =
2009                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2010                                 break;
2011                         case DDC_VGA:
2012                                 ddc_i2c =
2013                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2014                                 break;
2015                         case DDC_CRT2:
2016                                 ddc_i2c =
2017                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2018                                 break;
2019                         default:
2020                                 break;
2021                         }
2022
2023                         switch (connector) {
2024                         case CONNECTOR_PROPRIETARY_LEGACY:
2025                         case CONNECTOR_DVI_I_LEGACY:
2026                         case CONNECTOR_DVI_D_LEGACY:
2027                                 if ((tmp >> 4) & 0x1)
2028                                         hpd.hpd = RADEON_HPD_2;
2029                                 else
2030                                         hpd.hpd = RADEON_HPD_1;
2031                                 break;
2032                         default:
2033                                 hpd.hpd = RADEON_HPD_NONE;
2034                                 break;
2035                         }
2036
2037                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2038                                                         &ddc_i2c, &hpd))
2039                                 continue;
2040
2041                         switch (connector) {
2042                         case CONNECTOR_PROPRIETARY_LEGACY:
2043                                 if ((tmp >> 4) & 0x1)
2044                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2045                                 else
2046                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2047                                 radeon_add_legacy_encoder(dev,
2048                                                           radeon_get_encoder_id
2049                                                           (dev, devices, 0),
2050                                                           devices);
2051                                 radeon_add_legacy_connector(dev, i, devices,
2052                                                             legacy_connector_convert
2053                                                             [connector],
2054                                                             &ddc_i2c,
2055                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2056                                                             &hpd);
2057                                 break;
2058                         case CONNECTOR_CRT_LEGACY:
2059                                 if (tmp & 0x1) {
2060                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2061                                         radeon_add_legacy_encoder(dev,
2062                                                                   radeon_get_encoder_id
2063                                                                   (dev,
2064                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2065                                                                    2),
2066                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2067                                 } else {
2068                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2069                                         radeon_add_legacy_encoder(dev,
2070                                                                   radeon_get_encoder_id
2071                                                                   (dev,
2072                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2073                                                                    1),
2074                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2075                                 }
2076                                 radeon_add_legacy_connector(dev,
2077                                                             i,
2078                                                             devices,
2079                                                             legacy_connector_convert
2080                                                             [connector],
2081                                                             &ddc_i2c,
2082                                                             CONNECTOR_OBJECT_ID_VGA,
2083                                                             &hpd);
2084                                 break;
2085                         case CONNECTOR_DVI_I_LEGACY:
2086                                 devices = 0;
2087                                 if (tmp & 0x1) {
2088                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2089                                         radeon_add_legacy_encoder(dev,
2090                                                                   radeon_get_encoder_id
2091                                                                   (dev,
2092                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2093                                                                    2),
2094                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2095                                 } else {
2096                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2097                                         radeon_add_legacy_encoder(dev,
2098                                                                   radeon_get_encoder_id
2099                                                                   (dev,
2100                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2101                                                                    1),
2102                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2103                                 }
2104                                 if ((tmp >> 4) & 0x1) {
2105                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2106                                         radeon_add_legacy_encoder(dev,
2107                                                                   radeon_get_encoder_id
2108                                                                   (dev,
2109                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2110                                                                    0),
2111                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2112                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2113                                 } else {
2114                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2115                                         radeon_add_legacy_encoder(dev,
2116                                                                   radeon_get_encoder_id
2117                                                                   (dev,
2118                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2119                                                                    0),
2120                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2121                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2122                                 }
2123                                 radeon_add_legacy_connector(dev,
2124                                                             i,
2125                                                             devices,
2126                                                             legacy_connector_convert
2127                                                             [connector],
2128                                                             &ddc_i2c,
2129                                                             connector_object_id,
2130                                                             &hpd);
2131                                 break;
2132                         case CONNECTOR_DVI_D_LEGACY:
2133                                 if ((tmp >> 4) & 0x1) {
2134                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2135                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2136                                 } else {
2137                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2138                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2139                                 }
2140                                 radeon_add_legacy_encoder(dev,
2141                                                           radeon_get_encoder_id
2142                                                           (dev, devices, 0),
2143                                                           devices);
2144                                 radeon_add_legacy_connector(dev, i, devices,
2145                                                             legacy_connector_convert
2146                                                             [connector],
2147                                                             &ddc_i2c,
2148                                                             connector_object_id,
2149                                                             &hpd);
2150                                 break;
2151                         case CONNECTOR_CTV_LEGACY:
2152                         case CONNECTOR_STV_LEGACY:
2153                                 radeon_add_legacy_encoder(dev,
2154                                                           radeon_get_encoder_id
2155                                                           (dev,
2156                                                            ATOM_DEVICE_TV1_SUPPORT,
2157                                                            2),
2158                                                           ATOM_DEVICE_TV1_SUPPORT);
2159                                 radeon_add_legacy_connector(dev, i,
2160                                                             ATOM_DEVICE_TV1_SUPPORT,
2161                                                             legacy_connector_convert
2162                                                             [connector],
2163                                                             &ddc_i2c,
2164                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2165                                                             &hpd);
2166                                 break;
2167                         default:
2168                                 DRM_ERROR("Unknown connector type: %d\n",
2169                                           connector);
2170                                 continue;
2171                         }
2172
2173                 }
2174         } else {
2175                 uint16_t tmds_info =
2176                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2177                 if (tmds_info) {
2178                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2179
2180                         radeon_add_legacy_encoder(dev,
2181                                                   radeon_get_encoder_id(dev,
2182                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2183                                                                         1),
2184                                                   ATOM_DEVICE_CRT1_SUPPORT);
2185                         radeon_add_legacy_encoder(dev,
2186                                                   radeon_get_encoder_id(dev,
2187                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2188                                                                         0),
2189                                                   ATOM_DEVICE_DFP1_SUPPORT);
2190
2191                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2192                         hpd.hpd = RADEON_HPD_NONE;
2193                         radeon_add_legacy_connector(dev,
2194                                                     0,
2195                                                     ATOM_DEVICE_CRT1_SUPPORT |
2196                                                     ATOM_DEVICE_DFP1_SUPPORT,
2197                                                     DRM_MODE_CONNECTOR_DVII,
2198                                                     &ddc_i2c,
2199                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2200                                                     &hpd);
2201                 } else {
2202                         uint16_t crt_info =
2203                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2204                         DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2205                         if (crt_info) {
2206                                 radeon_add_legacy_encoder(dev,
2207                                                           radeon_get_encoder_id(dev,
2208                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2209                                                                                 1),
2210                                                           ATOM_DEVICE_CRT1_SUPPORT);
2211                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2212                                 hpd.hpd = RADEON_HPD_NONE;
2213                                 radeon_add_legacy_connector(dev,
2214                                                             0,
2215                                                             ATOM_DEVICE_CRT1_SUPPORT,
2216                                                             DRM_MODE_CONNECTOR_VGA,
2217                                                             &ddc_i2c,
2218                                                             CONNECTOR_OBJECT_ID_VGA,
2219                                                             &hpd);
2220                         } else {
2221                                 DRM_DEBUG("No connector info found\n");
2222                                 return false;
2223                         }
2224                 }
2225         }
2226
2227         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2228                 uint16_t lcd_info =
2229                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2230                 if (lcd_info) {
2231                         uint16_t lcd_ddc_info =
2232                             combios_get_table_offset(dev,
2233                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2234
2235                         radeon_add_legacy_encoder(dev,
2236                                                   radeon_get_encoder_id(dev,
2237                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2238                                                                         0),
2239                                                   ATOM_DEVICE_LCD1_SUPPORT);
2240
2241                         if (lcd_ddc_info) {
2242                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2243                                 switch (ddc_type) {
2244                                 case DDC_MONID:
2245                                         ddc_i2c =
2246                                             combios_setup_i2c_bus
2247                                                 (rdev, RADEON_GPIO_MONID);
2248                                         break;
2249                                 case DDC_DVI:
2250                                         ddc_i2c =
2251                                             combios_setup_i2c_bus
2252                                                 (rdev, RADEON_GPIO_DVI_DDC);
2253                                         break;
2254                                 case DDC_VGA:
2255                                         ddc_i2c =
2256                                             combios_setup_i2c_bus
2257                                                 (rdev, RADEON_GPIO_VGA_DDC);
2258                                         break;
2259                                 case DDC_CRT2:
2260                                         ddc_i2c =
2261                                             combios_setup_i2c_bus
2262                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2263                                         break;
2264                                 case DDC_LCD:
2265                                         ddc_i2c =
2266                                             combios_setup_i2c_bus
2267                                                 (rdev, RADEON_GPIOPAD_MASK);
2268                                         ddc_i2c.mask_clk_mask =
2269                                             RBIOS32(lcd_ddc_info + 3);
2270                                         ddc_i2c.mask_data_mask =
2271                                             RBIOS32(lcd_ddc_info + 7);
2272                                         ddc_i2c.a_clk_mask =
2273                                             RBIOS32(lcd_ddc_info + 3);
2274                                         ddc_i2c.a_data_mask =
2275                                             RBIOS32(lcd_ddc_info + 7);
2276                                         ddc_i2c.en_clk_mask =
2277                                             RBIOS32(lcd_ddc_info + 3);
2278                                         ddc_i2c.en_data_mask =
2279                                             RBIOS32(lcd_ddc_info + 7);
2280                                         ddc_i2c.y_clk_mask =
2281                                             RBIOS32(lcd_ddc_info + 3);
2282                                         ddc_i2c.y_data_mask =
2283                                             RBIOS32(lcd_ddc_info + 7);
2284                                         break;
2285                                 case DDC_GPIO:
2286                                         ddc_i2c =
2287                                             combios_setup_i2c_bus
2288                                                 (rdev, RADEON_MDGPIO_MASK);
2289                                         ddc_i2c.mask_clk_mask =
2290                                             RBIOS32(lcd_ddc_info + 3);
2291                                         ddc_i2c.mask_data_mask =
2292                                             RBIOS32(lcd_ddc_info + 7);
2293                                         ddc_i2c.a_clk_mask =
2294                                             RBIOS32(lcd_ddc_info + 3);
2295                                         ddc_i2c.a_data_mask =
2296                                             RBIOS32(lcd_ddc_info + 7);
2297                                         ddc_i2c.en_clk_mask =
2298                                             RBIOS32(lcd_ddc_info + 3);
2299                                         ddc_i2c.en_data_mask =
2300                                             RBIOS32(lcd_ddc_info + 7);
2301                                         ddc_i2c.y_clk_mask =
2302                                             RBIOS32(lcd_ddc_info + 3);
2303                                         ddc_i2c.y_data_mask =
2304                                             RBIOS32(lcd_ddc_info + 7);
2305                                         break;
2306                                 default:
2307                                         ddc_i2c.valid = false;
2308                                         break;
2309                                 }
2310                                 DRM_DEBUG("LCD DDC Info Table found!\n");
2311                         } else
2312                                 ddc_i2c.valid = false;
2313
2314                         hpd.hpd = RADEON_HPD_NONE;
2315                         radeon_add_legacy_connector(dev,
2316                                                     5,
2317                                                     ATOM_DEVICE_LCD1_SUPPORT,
2318                                                     DRM_MODE_CONNECTOR_LVDS,
2319                                                     &ddc_i2c,
2320                                                     CONNECTOR_OBJECT_ID_LVDS,
2321                                                     &hpd);
2322                 }
2323         }
2324
2325         /* check TV table */
2326         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2327                 uint32_t tv_info =
2328                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2329                 if (tv_info) {
2330                         if (RBIOS8(tv_info + 6) == 'T') {
2331                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2332                                         hpd.hpd = RADEON_HPD_NONE;
2333                                         radeon_add_legacy_encoder(dev,
2334                                                                   radeon_get_encoder_id
2335                                                                   (dev,
2336                                                                    ATOM_DEVICE_TV1_SUPPORT,
2337                                                                    2),
2338                                                                   ATOM_DEVICE_TV1_SUPPORT);
2339                                         radeon_add_legacy_connector(dev, 6,
2340                                                                     ATOM_DEVICE_TV1_SUPPORT,
2341                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2342                                                                     &ddc_i2c,
2343                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2344                                                                     &hpd);
2345                                 }
2346                         }
2347                 }
2348         }
2349
2350         radeon_link_encoder_connector(dev);
2351
2352         return true;
2353 }
2354
2355 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2356 {
2357         struct drm_device *dev = rdev->ddev;
2358         u16 offset, misc, misc2 = 0;
2359         u8 rev, blocks, tmp;
2360         int state_index = 0;
2361
2362         rdev->pm.default_power_state = NULL;
2363
2364         if (rdev->flags & RADEON_IS_MOBILITY) {
2365                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2366                 if (offset) {
2367                         rev = RBIOS8(offset);
2368                         blocks = RBIOS8(offset + 0x2);
2369                         /* power mode 0 tends to be the only valid one */
2370                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2371                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2372                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2373                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2374                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2375                                 goto default_mode;
2376                         /* skip overclock modes for now */
2377                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2378                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
2379                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
2380                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
2381                                 goto default_mode;
2382                         rdev->pm.power_state[state_index].type =
2383                                 POWER_STATE_TYPE_BATTERY;
2384                         misc = RBIOS16(offset + 0x5 + 0x0);
2385                         if (rev > 4)
2386                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2387                         if (misc & 0x4) {
2388                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2389                                 if (misc & 0x8)
2390                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2391                                                 true;
2392                                 else
2393                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2394                                                 false;
2395                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2396                                 if (rev < 6) {
2397                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2398                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2399                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2400                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2401                                 } else {
2402                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2403                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2404                                         if (entries && voltage_table_offset) {
2405                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2406                                                         RBIOS16(voltage_table_offset) * 4;
2407                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2408                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2409                                         } else
2410                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2411                                 }
2412                                 switch ((misc2 & 0x700) >> 8) {
2413                                 case 0:
2414                                 default:
2415                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2416                                         break;
2417                                 case 1:
2418                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2419                                         break;
2420                                 case 2:
2421                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2422                                         break;
2423                                 case 3:
2424                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2425                                         break;
2426                                 case 4:
2427                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2428                                         break;
2429                                 }
2430                         } else
2431                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2432                         if (rev > 6)
2433                                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2434                                         RBIOS8(offset + 0x5 + 0x10);
2435                         state_index++;
2436                 } else {
2437                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2438                 }
2439         } else {
2440                 /* XXX figure out some good default low power mode for desktop cards */
2441         }
2442
2443 default_mode:
2444         /* add the default mode */
2445         rdev->pm.power_state[state_index].type =
2446                 POWER_STATE_TYPE_DEFAULT;
2447         rdev->pm.power_state[state_index].num_clock_modes = 1;
2448         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2449         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2450         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2451         rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2452         if (rdev->asic->get_pcie_lanes)
2453                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2454         else
2455                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2456         rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2457         rdev->pm.num_power_states = state_index + 1;
2458
2459         rdev->pm.current_power_state = rdev->pm.default_power_state;
2460         rdev->pm.current_clock_mode =
2461                 rdev->pm.default_power_state->default_clock_mode;
2462 }
2463
2464 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2465 {
2466         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2467         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2468
2469         if (!tmds)
2470                 return;
2471
2472         switch (tmds->dvo_chip) {
2473         case DVO_SIL164:
2474                 /* sil 164 */
2475                 radeon_i2c_put_byte(tmds->i2c_bus,
2476                                     tmds->slave_addr,
2477                                     0x08, 0x30);
2478                 radeon_i2c_put_byte(tmds->i2c_bus,
2479                                        tmds->slave_addr,
2480                                        0x09, 0x00);
2481                 radeon_i2c_put_byte(tmds->i2c_bus,
2482                                     tmds->slave_addr,
2483                                     0x0a, 0x90);
2484                 radeon_i2c_put_byte(tmds->i2c_bus,
2485                                     tmds->slave_addr,
2486                                     0x0c, 0x89);
2487                 radeon_i2c_put_byte(tmds->i2c_bus,
2488                                        tmds->slave_addr,
2489                                        0x08, 0x3b);
2490                 break;
2491         case DVO_SIL1178:
2492                 /* sil 1178 - untested */
2493                 /*
2494                  * 0x0f, 0x44
2495                  * 0x0f, 0x4c
2496                  * 0x0e, 0x01
2497                  * 0x0a, 0x80
2498                  * 0x09, 0x30
2499                  * 0x0c, 0xc9
2500                  * 0x0d, 0x70
2501                  * 0x08, 0x32
2502                  * 0x08, 0x33
2503                  */
2504                 break;
2505         default:
2506                 break;
2507         }
2508
2509 }
2510
2511 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2512 {
2513         struct drm_device *dev = encoder->dev;
2514         struct radeon_device *rdev = dev->dev_private;
2515         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2516         uint16_t offset;
2517         uint8_t blocks, slave_addr, rev;
2518         uint32_t index, id;
2519         uint32_t reg, val, and_mask, or_mask;
2520         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2521
2522         if (!tmds)
2523                 return false;
2524
2525         if (rdev->flags & RADEON_IS_IGP) {
2526                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2527                 rev = RBIOS8(offset);
2528                 if (offset) {
2529                         rev = RBIOS8(offset);
2530                         if (rev > 1) {
2531                                 blocks = RBIOS8(offset + 3);
2532                                 index = offset + 4;
2533                                 while (blocks > 0) {
2534                                         id = RBIOS16(index);
2535                                         index += 2;
2536                                         switch (id >> 13) {
2537                                         case 0:
2538                                                 reg = (id & 0x1fff) * 4;
2539                                                 val = RBIOS32(index);
2540                                                 index += 4;
2541                                                 WREG32(reg, val);
2542                                                 break;
2543                                         case 2:
2544                                                 reg = (id & 0x1fff) * 4;
2545                                                 and_mask = RBIOS32(index);
2546                                                 index += 4;
2547                                                 or_mask = RBIOS32(index);
2548                                                 index += 4;
2549                                                 val = RREG32(reg);
2550                                                 val = (val & and_mask) | or_mask;
2551                                                 WREG32(reg, val);
2552                                                 break;
2553                                         case 3:
2554                                                 val = RBIOS16(index);
2555                                                 index += 2;
2556                                                 udelay(val);
2557                                                 break;
2558                                         case 4:
2559                                                 val = RBIOS16(index);
2560                                                 index += 2;
2561                                                 udelay(val * 1000);
2562                                                 break;
2563                                         case 6:
2564                                                 slave_addr = id & 0xff;
2565                                                 slave_addr >>= 1; /* 7 bit addressing */
2566                                                 index++;
2567                                                 reg = RBIOS8(index);
2568                                                 index++;
2569                                                 val = RBIOS8(index);
2570                                                 index++;
2571                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2572                                                                     slave_addr,
2573                                                                     reg, val);
2574                                                 break;
2575                                         default:
2576                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2577                                                 break;
2578                                         }
2579                                         blocks--;
2580                                 }
2581                                 return true;
2582                         }
2583                 }
2584         } else {
2585                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2586                 if (offset) {
2587                         index = offset + 10;
2588                         id = RBIOS16(index);
2589                         while (id != 0xffff) {
2590                                 index += 2;
2591                                 switch (id >> 13) {
2592                                 case 0:
2593                                         reg = (id & 0x1fff) * 4;
2594                                         val = RBIOS32(index);
2595                                         WREG32(reg, val);
2596                                         break;
2597                                 case 2:
2598                                         reg = (id & 0x1fff) * 4;
2599                                         and_mask = RBIOS32(index);
2600                                         index += 4;
2601                                         or_mask = RBIOS32(index);
2602                                         index += 4;
2603                                         val = RREG32(reg);
2604                                         val = (val & and_mask) | or_mask;
2605                                         WREG32(reg, val);
2606                                         break;
2607                                 case 4:
2608                                         val = RBIOS16(index);
2609                                         index += 2;
2610                                         udelay(val);
2611                                         break;
2612                                 case 5:
2613                                         reg = id & 0x1fff;
2614                                         and_mask = RBIOS32(index);
2615                                         index += 4;
2616                                         or_mask = RBIOS32(index);
2617                                         index += 4;
2618                                         val = RREG32_PLL(reg);
2619                                         val = (val & and_mask) | or_mask;
2620                                         WREG32_PLL(reg, val);
2621                                         break;
2622                                 case 6:
2623                                         reg = id & 0x1fff;
2624                                         val = RBIOS8(index);
2625                                         index += 1;
2626                                         radeon_i2c_put_byte(tmds->i2c_bus,
2627                                                             tmds->slave_addr,
2628                                                             reg, val);
2629                                         break;
2630                                 default:
2631                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2632                                         break;
2633                                 }
2634                                 id = RBIOS16(index);
2635                         }
2636                         return true;
2637                 }
2638         }
2639         return false;
2640 }
2641
2642 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2643 {
2644         struct radeon_device *rdev = dev->dev_private;
2645
2646         if (offset) {
2647                 while (RBIOS16(offset)) {
2648                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2649                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2650                         uint32_t val, and_mask, or_mask;
2651                         uint32_t tmp;
2652
2653                         offset += 2;
2654                         switch (cmd) {
2655                         case 0:
2656                                 val = RBIOS32(offset);
2657                                 offset += 4;
2658                                 WREG32(addr, val);
2659                                 break;
2660                         case 1:
2661                                 val = RBIOS32(offset);
2662                                 offset += 4;
2663                                 WREG32(addr, val);
2664                                 break;
2665                         case 2:
2666                                 and_mask = RBIOS32(offset);
2667                                 offset += 4;
2668                                 or_mask = RBIOS32(offset);
2669                                 offset += 4;
2670                                 tmp = RREG32(addr);
2671                                 tmp &= and_mask;
2672                                 tmp |= or_mask;
2673                                 WREG32(addr, tmp);
2674                                 break;
2675                         case 3:
2676                                 and_mask = RBIOS32(offset);
2677                                 offset += 4;
2678                                 or_mask = RBIOS32(offset);
2679                                 offset += 4;
2680                                 tmp = RREG32(addr);
2681                                 tmp &= and_mask;
2682                                 tmp |= or_mask;
2683                                 WREG32(addr, tmp);
2684                                 break;
2685                         case 4:
2686                                 val = RBIOS16(offset);
2687                                 offset += 2;
2688                                 udelay(val);
2689                                 break;
2690                         case 5:
2691                                 val = RBIOS16(offset);
2692                                 offset += 2;
2693                                 switch (addr) {
2694                                 case 8:
2695                                         while (val--) {
2696                                                 if (!
2697                                                     (RREG32_PLL
2698                                                      (RADEON_CLK_PWRMGT_CNTL) &
2699                                                      RADEON_MC_BUSY))
2700                                                         break;
2701                                         }
2702                                         break;
2703                                 case 9:
2704                                         while (val--) {
2705                                                 if ((RREG32(RADEON_MC_STATUS) &
2706                                                      RADEON_MC_IDLE))
2707                                                         break;
2708                                         }
2709                                         break;
2710                                 default:
2711                                         break;
2712                                 }
2713                                 break;
2714                         default:
2715                                 break;
2716                         }
2717                 }
2718         }
2719 }
2720
2721 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2722 {
2723         struct radeon_device *rdev = dev->dev_private;
2724
2725         if (offset) {
2726                 while (RBIOS8(offset)) {
2727                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2728                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2729                         uint32_t val, shift, tmp;
2730                         uint32_t and_mask, or_mask;
2731
2732                         offset++;
2733                         switch (cmd) {
2734                         case 0:
2735                                 val = RBIOS32(offset);
2736                                 offset += 4;
2737                                 WREG32_PLL(addr, val);
2738                                 break;
2739                         case 1:
2740                                 shift = RBIOS8(offset) * 8;
2741                                 offset++;
2742                                 and_mask = RBIOS8(offset) << shift;
2743                                 and_mask |= ~(0xff << shift);
2744                                 offset++;
2745                                 or_mask = RBIOS8(offset) << shift;
2746                                 offset++;
2747                                 tmp = RREG32_PLL(addr);
2748                                 tmp &= and_mask;
2749                                 tmp |= or_mask;
2750                                 WREG32_PLL(addr, tmp);
2751                                 break;
2752                         case 2:
2753                         case 3:
2754                                 tmp = 1000;
2755                                 switch (addr) {
2756                                 case 1:
2757                                         udelay(150);
2758                                         break;
2759                                 case 2:
2760                                         udelay(1000);
2761                                         break;
2762                                 case 3:
2763                                         while (tmp--) {
2764                                                 if (!
2765                                                     (RREG32_PLL
2766                                                      (RADEON_CLK_PWRMGT_CNTL) &
2767                                                      RADEON_MC_BUSY))
2768                                                         break;
2769                                         }
2770                                         break;
2771                                 case 4:
2772                                         while (tmp--) {
2773                                                 if (RREG32_PLL
2774                                                     (RADEON_CLK_PWRMGT_CNTL) &
2775                                                     RADEON_DLL_READY)
2776                                                         break;
2777                                         }
2778                                         break;
2779                                 case 5:
2780                                         tmp =
2781                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2782                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2783 #if 0
2784                                                 uint32_t mclk_cntl =
2785                                                     RREG32_PLL
2786                                                     (RADEON_MCLK_CNTL);
2787                                                 mclk_cntl &= 0xffff0000;
2788                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2789                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2790                                                            mclk_cntl);
2791                                                 udelay(10000);
2792 #endif
2793                                                 WREG32_PLL
2794                                                     (RADEON_CLK_PWRMGT_CNTL,
2795                                                      tmp &
2796                                                      ~RADEON_CG_NO1_DEBUG_0);
2797                                                 udelay(10000);
2798                                         }
2799                                         break;
2800                                 default:
2801                                         break;
2802                                 }
2803                                 break;
2804                         default:
2805                                 break;
2806                         }
2807                 }
2808         }
2809 }
2810
2811 static void combios_parse_ram_reset_table(struct drm_device *dev,
2812                                           uint16_t offset)
2813 {
2814         struct radeon_device *rdev = dev->dev_private;
2815         uint32_t tmp;
2816
2817         if (offset) {
2818                 uint8_t val = RBIOS8(offset);
2819                 while (val != 0xff) {
2820                         offset++;
2821
2822                         if (val == 0x0f) {
2823                                 uint32_t channel_complete_mask;
2824
2825                                 if (ASIC_IS_R300(rdev))
2826                                         channel_complete_mask =
2827                                             R300_MEM_PWRUP_COMPLETE;
2828                                 else
2829                                         channel_complete_mask =
2830                                             RADEON_MEM_PWRUP_COMPLETE;
2831                                 tmp = 20000;
2832                                 while (tmp--) {
2833                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2834                                              channel_complete_mask) ==
2835                                             channel_complete_mask)
2836                                                 break;
2837                                 }
2838                         } else {
2839                                 uint32_t or_mask = RBIOS16(offset);
2840                                 offset += 2;
2841
2842                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2843                                 tmp &= RADEON_SDRAM_MODE_MASK;
2844                                 tmp |= or_mask;
2845                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2846
2847                                 or_mask = val << 24;
2848                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2849                                 tmp &= RADEON_B3MEM_RESET_MASK;
2850                                 tmp |= or_mask;
2851                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2852                         }
2853                         val = RBIOS8(offset);
2854                 }
2855         }
2856 }
2857
2858 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2859                                    int mem_addr_mapping)
2860 {
2861         struct radeon_device *rdev = dev->dev_private;
2862         uint32_t mem_cntl;
2863         uint32_t mem_size;
2864         uint32_t addr = 0;
2865
2866         mem_cntl = RREG32(RADEON_MEM_CNTL);
2867         if (mem_cntl & RV100_HALF_MODE)
2868                 ram /= 2;
2869         mem_size = ram;
2870         mem_cntl &= ~(0xff << 8);
2871         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2872         WREG32(RADEON_MEM_CNTL, mem_cntl);
2873         RREG32(RADEON_MEM_CNTL);
2874
2875         /* sdram reset ? */
2876
2877         /* something like this????  */
2878         while (ram--) {
2879                 addr = ram * 1024 * 1024;
2880                 /* write to each page */
2881                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2882                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2883                 /* read back and verify */
2884                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2885                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2886                         return 0;
2887         }
2888
2889         return mem_size;
2890 }
2891
2892 static void combios_write_ram_size(struct drm_device *dev)
2893 {
2894         struct radeon_device *rdev = dev->dev_private;
2895         uint8_t rev;
2896         uint16_t offset;
2897         uint32_t mem_size = 0;
2898         uint32_t mem_cntl = 0;
2899
2900         /* should do something smarter here I guess... */
2901         if (rdev->flags & RADEON_IS_IGP)
2902                 return;
2903
2904         /* first check detected mem table */
2905         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2906         if (offset) {
2907                 rev = RBIOS8(offset);
2908                 if (rev < 3) {
2909                         mem_cntl = RBIOS32(offset + 1);
2910                         mem_size = RBIOS16(offset + 5);
2911                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2912                             ((dev->pdev->device != 0x515e)
2913                              && (dev->pdev->device != 0x5969)))
2914                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2915                 }
2916         }
2917
2918         if (!mem_size) {
2919                 offset =
2920                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2921                 if (offset) {
2922                         rev = RBIOS8(offset - 1);
2923                         if (rev < 1) {
2924                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2925                                      CHIP_R200)
2926                                     && ((dev->pdev->device != 0x515e)
2927                                         && (dev->pdev->device != 0x5969))) {
2928                                         int ram = 0;
2929                                         int mem_addr_mapping = 0;
2930
2931                                         while (RBIOS8(offset)) {
2932                                                 ram = RBIOS8(offset);
2933                                                 mem_addr_mapping =
2934                                                     RBIOS8(offset + 1);
2935                                                 if (mem_addr_mapping != 0x25)
2936                                                         ram *= 2;
2937                                                 mem_size =
2938                                                     combios_detect_ram(dev, ram,
2939                                                                        mem_addr_mapping);
2940                                                 if (mem_size)
2941                                                         break;
2942                                                 offset += 2;
2943                                         }
2944                                 } else
2945                                         mem_size = RBIOS8(offset);
2946                         } else {
2947                                 mem_size = RBIOS8(offset);
2948                                 mem_size *= 2;  /* convert to MB */
2949                         }
2950                 }
2951         }
2952
2953         mem_size *= (1024 * 1024);      /* convert to bytes */
2954         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2955 }
2956
2957 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2958 {
2959         uint16_t dyn_clk_info =
2960             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2961
2962         if (dyn_clk_info)
2963                 combios_parse_pll_table(dev, dyn_clk_info);
2964 }
2965
2966 void radeon_combios_asic_init(struct drm_device *dev)
2967 {
2968         struct radeon_device *rdev = dev->dev_private;
2969         uint16_t table;
2970
2971         /* port hardcoded mac stuff from radeonfb */
2972         if (rdev->bios == NULL)
2973                 return;
2974
2975         /* ASIC INIT 1 */
2976         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2977         if (table)
2978                 combios_parse_mmio_table(dev, table);
2979
2980         /* PLL INIT */
2981         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2982         if (table)
2983                 combios_parse_pll_table(dev, table);
2984
2985         /* ASIC INIT 2 */
2986         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2987         if (table)
2988                 combios_parse_mmio_table(dev, table);
2989
2990         if (!(rdev->flags & RADEON_IS_IGP)) {
2991                 /* ASIC INIT 4 */
2992                 table =
2993                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2994                 if (table)
2995                         combios_parse_mmio_table(dev, table);
2996
2997                 /* RAM RESET */
2998                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2999                 if (table)
3000                         combios_parse_ram_reset_table(dev, table);
3001
3002                 /* ASIC INIT 3 */
3003                 table =
3004                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3005                 if (table)
3006                         combios_parse_mmio_table(dev, table);
3007
3008                 /* write CONFIG_MEMSIZE */
3009                 combios_write_ram_size(dev);
3010         }
3011
3012         /* DYN CLK 1 */
3013         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3014         if (table)
3015                 combios_parse_pll_table(dev, table);
3016
3017 }
3018
3019 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3020 {
3021         struct radeon_device *rdev = dev->dev_private;
3022         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3023
3024         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3025         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3026         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3027
3028         /* let the bios control the backlight */
3029         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3030
3031         /* tell the bios not to handle mode switching */
3032         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3033                            RADEON_ACC_MODE_CHANGE);
3034
3035         /* tell the bios a driver is loaded */
3036         bios_7_scratch |= RADEON_DRV_LOADED;
3037
3038         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3039         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3040         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3041 }
3042
3043 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3044 {
3045         struct drm_device *dev = encoder->dev;
3046         struct radeon_device *rdev = dev->dev_private;
3047         uint32_t bios_6_scratch;
3048
3049         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3050
3051         if (lock)
3052                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3053         else
3054                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3055
3056         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3057 }
3058
3059 void
3060 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3061                                       struct drm_encoder *encoder,
3062                                       bool connected)
3063 {
3064         struct drm_device *dev = connector->dev;
3065         struct radeon_device *rdev = dev->dev_private;
3066         struct radeon_connector *radeon_connector =
3067             to_radeon_connector(connector);
3068         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3069         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3070         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3071
3072         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3073             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3074                 if (connected) {
3075                         DRM_DEBUG("TV1 connected\n");
3076                         /* fix me */
3077                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3078                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3079                         bios_5_scratch |= RADEON_TV1_ON;
3080                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3081                 } else {
3082                         DRM_DEBUG("TV1 disconnected\n");
3083                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3084                         bios_5_scratch &= ~RADEON_TV1_ON;
3085                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3086                 }
3087         }
3088         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3089             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3090                 if (connected) {
3091                         DRM_DEBUG("LCD1 connected\n");
3092                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3093                         bios_5_scratch |= RADEON_LCD1_ON;
3094                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3095                 } else {
3096                         DRM_DEBUG("LCD1 disconnected\n");
3097                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3098                         bios_5_scratch &= ~RADEON_LCD1_ON;
3099                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3100                 }
3101         }
3102         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3103             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3104                 if (connected) {
3105                         DRM_DEBUG("CRT1 connected\n");
3106                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3107                         bios_5_scratch |= RADEON_CRT1_ON;
3108                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3109                 } else {
3110                         DRM_DEBUG("CRT1 disconnected\n");
3111                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3112                         bios_5_scratch &= ~RADEON_CRT1_ON;
3113                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3114                 }
3115         }
3116         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3117             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3118                 if (connected) {
3119                         DRM_DEBUG("CRT2 connected\n");
3120                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3121                         bios_5_scratch |= RADEON_CRT2_ON;
3122                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3123                 } else {
3124                         DRM_DEBUG("CRT2 disconnected\n");
3125                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3126                         bios_5_scratch &= ~RADEON_CRT2_ON;
3127                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3128                 }
3129         }
3130         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3131             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3132                 if (connected) {
3133                         DRM_DEBUG("DFP1 connected\n");
3134                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3135                         bios_5_scratch |= RADEON_DFP1_ON;
3136                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3137                 } else {
3138                         DRM_DEBUG("DFP1 disconnected\n");
3139                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3140                         bios_5_scratch &= ~RADEON_DFP1_ON;
3141                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3142                 }
3143         }
3144         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3145             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3146                 if (connected) {
3147                         DRM_DEBUG("DFP2 connected\n");
3148                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3149                         bios_5_scratch |= RADEON_DFP2_ON;
3150                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3151                 } else {
3152                         DRM_DEBUG("DFP2 disconnected\n");
3153                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3154                         bios_5_scratch &= ~RADEON_DFP2_ON;
3155                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3156                 }
3157         }
3158         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3159         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3160 }
3161
3162 void
3163 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3164 {
3165         struct drm_device *dev = encoder->dev;
3166         struct radeon_device *rdev = dev->dev_private;
3167         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3168         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3169
3170         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3171                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3172                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3173         }
3174         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3175                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3176                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3177         }
3178         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3179                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3180                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3181         }
3182         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3183                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3184                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3185         }
3186         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3187                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3188                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3189         }
3190         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3191                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3192                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3193         }
3194         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3195 }
3196
3197 void
3198 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3199 {
3200         struct drm_device *dev = encoder->dev;
3201         struct radeon_device *rdev = dev->dev_private;
3202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3203         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3204
3205         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3206                 if (on)
3207                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3208                 else
3209                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3210         }
3211         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3212                 if (on)
3213                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3214                 else
3215                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3216         }
3217         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3218                 if (on)
3219                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3220                 else
3221                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3222         }
3223         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3224                 if (on)
3225                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3226                 else
3227                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3228         }
3229         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3230 }